From c078ca968c6c7cb62781c1843d840cb0f5c72781 Mon Sep 17 00:00:00 2001 From: Luwei Kang Date: Wed, 14 Mar 2018 03:26:31 +0800 Subject: [PATCH] i386: Disable Intel PT if packets IP payloads have LIP values Intel processor trace should be disabled when CPUID.(EAX=14H,ECX=0H).ECX.[bit31] is set. Generated packets which contain IP payloads will have LIP values when this bit is set, or IP payloads will have RIP values. Currently, The information of CPUID 14H is constant to make live migration safty and this bit is always 0 in guest even if host support LIP values. Guest sees the bit is 0 will expect IP payloads with RIP values, but the host CPU will generate IP payloads with LIP values if this bit is set in HW. To make sure the value of IP payloads correctly, Intel PT should be disabled when bit[31] is set. Signed-off-by: Luwei Kang Message-Id: <1520969191-18162-1-git-send-email-luwei.kang@intel.com> Signed-off-by: Eduardo Habkost --- target/i386/cpu.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 30b4af897b..4f62fe776d 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -195,6 +195,8 @@ * bit[02]: Support Single-Range Output scheme; */ #define INTEL_PT_MINIMAL_ECX 0x7 +/* generated packets which contain IP payloads have LIP values */ +#define INTEL_PT_IP_LIP (1 << 31) #define INTEL_PT_ADDR_RANGES_NUM 0x2 /* Number of configurable address ranges */ #define INTEL_PT_ADDR_RANGES_NUM_MASK 0x3 #define INTEL_PT_MTC_BITMAP (0x0249 << 16) /* Support ART(0,3,6,9) */ @@ -4167,7 +4169,8 @@ static int x86_cpu_filter_features(X86CPU *cpu) ((eax_1 & INTEL_PT_ADDR_RANGES_NUM_MASK) < INTEL_PT_ADDR_RANGES_NUM) || ((ebx_1 & (INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP)) != - (INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP))) { + (INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP)) || + (ecx_0 & INTEL_PT_IP_LIP)) { /* * Processor Trace capabilities aren't configurable, so if the * host can't emulate the capabilities we report on -- 2.39.2