From 0786a3b6051ed081ddaa8dfe1c1e13ce0cfabc4a Mon Sep 17 00:00:00 2001 From: Helge Deller Date: Wed, 28 Sep 2022 20:49:13 +0200 Subject: [PATCH] target/hppa: Generate illegal instruction exception for 64-bit instructions Qemu currently emulates a 32-bit CPU only, and crashes with this error when it faces a 64-bit load (e.g. "ldd 0(r26),r0") or a 64-bit store (e.g. "std r26,0(r26)") instruction in the guest: ERROR:../qemu/tcg/tcg-op.c:2822:tcg_canonicalize_memop: code should not be reached Add checks for 64-bit sizes and generate an illegal instruction exception if necessary. Signed-off-by: Helge Deller Reviewed-by: Richard Henderson --- target/hppa/translate.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 1af77473da..d15b9e27c7 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -2899,14 +2899,22 @@ static bool trans_cmpiclr(DisasContext *ctx, arg_rri_cf *a) static bool trans_ld(DisasContext *ctx, arg_ldst *a) { - return do_load(ctx, a->t, a->b, a->x, a->scale ? a->size : 0, + if (unlikely(TARGET_REGISTER_BITS == 32 && a->size > MO_32)) { + return gen_illegal(ctx); + } else { + return do_load(ctx, a->t, a->b, a->x, a->scale ? a->size : 0, a->disp, a->sp, a->m, a->size | MO_TE); + } } static bool trans_st(DisasContext *ctx, arg_ldst *a) { assert(a->x == 0 && a->scale == 0); - return do_store(ctx, a->t, a->b, a->disp, a->sp, a->m, a->size | MO_TE); + if (unlikely(TARGET_REGISTER_BITS == 32 && a->size > MO_32)) { + return gen_illegal(ctx); + } else { + return do_store(ctx, a->t, a->b, a->disp, a->sp, a->m, a->size | MO_TE); + } } static bool trans_ldc(DisasContext *ctx, arg_ldst *a) -- 2.39.5