From 2e60f9ec2ccb3906323deda7797f91c74b967b3f Mon Sep 17 00:00:00 2001 From: Weiwei Li Date: Wed, 15 Feb 2023 10:05:31 +0800 Subject: [PATCH] target/riscv: Add property check for Zvfh{min} extensions Add check for Zvfh and Zvfhmin. Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Daniel Henrique Barboza Message-ID: <20230215020539.4788-7-liweiwei@iscas.ac.cn> [Palmer: commit text] Signed-off-by: Palmer Dabbelt --- target/riscv/cpu.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 49912c9174..49ac368662 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -768,6 +768,20 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) return; } + if (cpu->cfg.ext_zvfh) { + cpu->cfg.ext_zvfhmin = true; + } + + if (cpu->cfg.ext_zvfhmin && !cpu->cfg.ext_zve32f) { + error_setg(errp, "Zvfh/Zvfhmin extensions require Zve32f extension"); + return; + } + + if (cpu->cfg.ext_zvfh && !cpu->cfg.ext_zfhmin) { + error_setg(errp, "Zvfh extensions requires Zfhmin extension"); + return; + } + /* Set the ISA extensions, checks should have happened above */ if (cpu->cfg.ext_zhinx) { cpu->cfg.ext_zhinxmin = true; -- 2.39.5