From 465af4db965322630b253691b569b40cf84a2dbc Mon Sep 17 00:00:00 2001 From: =?utf8?q?Alex=20Benn=C3=A9e?= Date: Fri, 30 Jun 2023 19:04:03 +0100 Subject: [PATCH] target/arm: make arm_casq_ptw CONFIG_TCG only MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit The ptw code is accessed by non-TCG code (specifically arm_pamax and arm_cpu_get_phys_page_attrs_debug) but most of it is really only for TCG emulation. Seeing as we already assert for a non TARGET_AARCH64 build lets extend the test rather than further messing with the ifdef ladder. Reviewed-by: Richard Henderson Signed-off-by: Alex Bennée Message-Id: <20230630180423.558337-19-alex.bennee@linaro.org> --- target/arm/ptw.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 6015121b99..42355caa9b 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -628,7 +628,7 @@ static uint64_t arm_casq_ptw(CPUARMState *env, uint64_t old_val, uint64_t new_val, S1Translate *ptw, ARMMMUFaultInfo *fi) { -#ifdef TARGET_AARCH64 +#if defined(TARGET_AARCH64) && defined(CONFIG_TCG) uint64_t cur_val; void *host = ptw->out_host; @@ -709,7 +709,7 @@ static uint64_t arm_casq_ptw(CPUARMState *env, uint64_t old_val, return cur_val; #else - /* AArch32 does not have FEAT_HADFS. */ + /* AArch32 does not have FEAT_HADFS; non-TCG guests only use debug-mode. */ g_assert_not_reached(); #endif } -- 2.39.5