From 4705b7da4b61e591a84a2deb9736ddbad24ce34a Mon Sep 17 00:00:00 2001 From: oliviermartin Date: Fri, 3 Jun 2011 09:25:51 +0000 Subject: [PATCH] ArmPkg: Add comments to ArmEnableVFP git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@11740 6f19259b-4bc3-4df7-8a09-765794883524 --- ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.S | 11 +++++++---- ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.asm | 11 +++++++---- 2 files changed, 14 insertions(+), 8 deletions(-) diff --git a/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.S b/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.S index b11c19dc59..62b8682de5 100644 --- a/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.S +++ b/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.S @@ -316,12 +316,15 @@ ASM_PFX(ArmWriteCPACR): bx lr ASM_PFX(ArmEnableVFP): - # Enable VFP registers + # Read CPACR (Coprocessor Access Control Register) mrc p15, 0, r0, c1, c0, 2 - orr r0, r0, #0x00f00000 @ Enable VPF access (V* instructions) + # Enable VPF access (Full Access to CP10, CP11) (V* instructions) + orr r0, r0, #0x00f00000 + # Write back CPACR (Coprocessor Access Control Register) mcr p15, 0, r0, c1, c0, 2 - mov r0, #0x40000000 @ Set EN bit in FPEXC - mcr p10,#0x7,r0,c8,c0,#0 @ msr FPEXC,r0 in ARM assembly + # Set EN bit in FPEXC. The Advanced SIMD and VFP extensions are enabled and operate normally. + mov r0, #0x40000000 + mcr p10,#0x7,r0,c8,c0,#0 bx lr ASM_PFX(ArmCallWFI): diff --git a/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.asm b/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.asm index 75399cb0fc..269e10bd56 100644 --- a/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.asm +++ b/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.asm @@ -314,12 +314,15 @@ ArmWriteCPACR bx lr ArmEnableVFP - // Enable VFP registers + // Read CPACR (Coprocessor Access Control Register) mrc p15, 0, r0, c1, c0, 2 - orr r0, r0, #0x00f00000 // Enable VPF access (V* instructions) + // Enable VPF access (Full Access to CP10, CP11) (V* instructions) + orr r0, r0, #0x00f00000 + // Write back CPACR (Coprocessor Access Control Register) mcr p15, 0, r0, c1, c0, 2 - mov r0, #0x40000000 // Set EN bit in FPEXC - mcr p10,#0x7,r0,c8,c0,#0 // msr FPEXC,r0 in ARM assembly + // Set EN bit in FPEXC. The Advanced SIMD and VFP extensions are enabled and operate normally. + mov r0, #0x40000000 + mcr p10,#0x7,r0,c8,c0,#0 bx lr ArmCallWFI -- 2.39.5