From 4df322593037d2700f72dfdfb967300b7ad2e696 Mon Sep 17 00:00:00 2001 From: Peter Maydell Date: Thu, 11 Feb 2016 11:17:31 +0000 Subject: [PATCH] target-arm: Fix IL bit reported for Thumb coprocessor traps All Thumb coprocessor instructions are 32 bits, so the IL bit in the syndrome register should be set. Pass false to the syn_* function's is_16bit argument rather than s->thumb so we report the correct IL bit. Signed-off-by: Peter Maydell Reviewed-by: Sergey Fedorov Message-id: 1454683067-16001-3-git-send-email-peter.maydell@linaro.org --- target-arm/translate.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/target-arm/translate.c b/target-arm/translate.c index 2c8213b07a..8e8ffee9c6 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -7184,19 +7184,19 @@ static int disas_coproc_insn(DisasContext *s, uint32_t insn) case 14: if (is64) { syndrome = syn_cp14_rrt_trap(1, 0xe, opc1, crm, rt, rt2, - isread, s->thumb); + isread, false); } else { syndrome = syn_cp14_rt_trap(1, 0xe, opc1, opc2, crn, crm, - rt, isread, s->thumb); + rt, isread, false); } break; case 15: if (is64) { syndrome = syn_cp15_rrt_trap(1, 0xe, opc1, crm, rt, rt2, - isread, s->thumb); + isread, false); } else { syndrome = syn_cp15_rt_trap(1, 0xe, opc1, opc2, crn, crm, - rt, isread, s->thumb); + rt, isread, false); } break; default: -- 2.39.5