From 51b2772f28f51b04e10e6e51f411f7246e1159d9 Mon Sep 17 00:00:00 2001
From: ths <ths@c046a42c-6fe2-441c-8c8c-71466251a162>
Date: Wed, 30 May 2007 20:46:02 +0000
Subject: [PATCH] Fix CPU (re-)selection on reset.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2900 c046a42c-6fe2-441c-8c8c-71466251a162
---
 hw/mips_malta.c              | 1 +
 hw/mips_pica61.c             | 1 +
 hw/mips_r4k.c                | 1 +
 target-mips/cpu.h            | 5 ++++-
 target-mips/translate_init.c | 8 +++++---
 5 files changed, 12 insertions(+), 4 deletions(-)

diff --git a/hw/mips_malta.c b/hw/mips_malta.c
index 6339cc941..f775c2f58 100644
--- a/hw/mips_malta.c
+++ b/hw/mips_malta.c
@@ -748,6 +748,7 @@ static void main_cpu_reset(void *opaque)
 {
     CPUState *env = opaque;
     cpu_reset(env);
+    cpu_mips_register(env, NULL);
 
     /* The bootload does not need to be rewritten as it is located in a
        read only location. The kernel location and the arguments table
diff --git a/hw/mips_pica61.c b/hw/mips_pica61.c
index 40ea8b5a6..5bb340535 100644
--- a/hw/mips_pica61.c
+++ b/hw/mips_pica61.c
@@ -51,6 +51,7 @@ static void main_cpu_reset(void *opaque)
 {
     CPUState *env = opaque;
     cpu_reset(env);
+    cpu_mips_register(env, NULL);
 }
 
 static
diff --git a/hw/mips_r4k.c b/hw/mips_r4k.c
index d600dbbb0..2208922a7 100644
--- a/hw/mips_r4k.c
+++ b/hw/mips_r4k.c
@@ -128,6 +128,7 @@ static void main_cpu_reset(void *opaque)
 {
     CPUState *env = opaque;
     cpu_reset(env);
+    cpu_mips_register(env, NULL);
 
     if (env->kernel_filename)
         load_kernel (env, env->ram_size, env->kernel_filename,
diff --git a/target-mips/cpu.h b/target-mips/cpu.h
index 36c58ec1e..9fa0ca8c6 100644
--- a/target-mips/cpu.h
+++ b/target-mips/cpu.h
@@ -48,6 +48,8 @@ struct r4k_tlb_t {
     target_ulong PFN[2];
 };
 
+typedef struct mips_def_t mips_def_t;
+
 typedef struct CPUMIPSState CPUMIPSState;
 struct CPUMIPSState {
     /* General integer registers */
@@ -295,6 +297,8 @@ struct CPUMIPSState {
     const char *kernel_cmdline;
     const char *initrd_filename;
 
+    mips_def_t *cpu_model;
+
     struct QEMUTimer *timer; /* Internal timer */
 };
 
@@ -308,7 +312,6 @@ void r4k_do_tlbwi (void);
 void r4k_do_tlbwr (void);
 void r4k_do_tlbp (void);
 void r4k_do_tlbr (void);
-typedef struct mips_def_t mips_def_t;
 int mips_find_by_name (const unsigned char *name, mips_def_t **def);
 void mips_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...));
 int cpu_mips_register (CPUMIPSState *env, mips_def_t *def);
diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c
index 7d60f19b2..e14b7348c 100644
--- a/target-mips/translate_init.c
+++ b/target-mips/translate_init.c
@@ -206,13 +206,15 @@ static void r4k_mmu_init (CPUMIPSState *env, mips_def_t *def)
 
 int cpu_mips_register (CPUMIPSState *env, mips_def_t *def)
 {
+    if (!def)
+        def = env->cpu_model;
     if (!def)
         cpu_abort(env, "Unable to find MIPS CPU definition\n");
+    env->cpu_model = def;
     env->CP0_PRid = def->CP0_PRid;
-#ifdef TARGET_WORDS_BIGENDIAN
-    env->CP0_Config0 = def->CP0_Config0 | (1 << CP0C0_BE);
-#else
     env->CP0_Config0 = def->CP0_Config0;
+#ifdef TARGET_WORDS_BIGENDIAN
+    env->CP0_Config0 |= (1 << CP0C0_BE);
 #endif
     env->CP0_Config1 = def->CP0_Config1;
     env->CP0_Config2 = def->CP0_Config2;
-- 
2.39.5