From 57de884d551dda5b58548168e6a88f428dd59524 Mon Sep 17 00:00:00 2001 From: Joel Stanley Date: Tue, 1 Sep 2020 14:21:51 +0200 Subject: [PATCH] aspeed/sdmc: Allow writes to unprotected registers MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit A subset of registers are not protected by the lock behaviour, so allow unconditionally writing to those. Signed-off-by: Joel Stanley Message-Id: <20200819100956.2216690-18-clg@kaod.org> Signed-off-by: Cédric Le Goater --- hw/misc/aspeed_sdmc.c | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/hw/misc/aspeed_sdmc.c b/hw/misc/aspeed_sdmc.c index ff2809a099..81c73450ab 100644 --- a/hw/misc/aspeed_sdmc.c +++ b/hw/misc/aspeed_sdmc.c @@ -33,15 +33,28 @@ /* Configuration Register */ #define R_CONF (0x04 / 4) +/* Interrupt control/status */ +#define R_ISR (0x50 / 4) + /* Control/Status Register #1 (ast2500) */ #define R_STATUS1 (0x60 / 4) #define PHY_BUSY_STATE BIT(0) #define PHY_PLL_LOCK_STATUS BIT(4) +/* Reserved */ +#define R_MCR6C (0x6c / 4) + #define R_ECC_TEST_CTRL (0x70 / 4) #define ECC_TEST_FINISHED BIT(12) #define ECC_TEST_FAIL BIT(13) +#define R_TEST_START_LEN (0x74 / 4) +#define R_TEST_FAIL_DQ (0x78 / 4) +#define R_TEST_INIT_VAL (0x7c / 4) +#define R_DRAM_SW (0x88 / 4) +#define R_DRAM_TIME (0x8c / 4) +#define R_ECC_ERR_INJECT (0xb4 / 4) + /* * Configuration register Ox4 (for Aspeed AST2400 SOC) * @@ -449,6 +462,20 @@ static uint32_t aspeed_2600_sdmc_compute_conf(AspeedSDMCState *s, uint32_t data) static void aspeed_2600_sdmc_write(AspeedSDMCState *s, uint32_t reg, uint32_t data) { + /* Unprotected registers */ + switch (reg) { + case R_ISR: + case R_MCR6C: + case R_TEST_START_LEN: + case R_TEST_FAIL_DQ: + case R_TEST_INIT_VAL: + case R_DRAM_SW: + case R_DRAM_TIME: + case R_ECC_ERR_INJECT: + s->regs[reg] = data; + return; + } + if (s->regs[R_PROT] == PROT_HARDLOCKED) { qemu_log_mask(LOG_GUEST_ERROR, "%s: SDMC is locked until system reset!\n", __func__); -- 2.39.5