From 8f0767611a0ed719caf975d899d8431834ace2d8 Mon Sep 17 00:00:00 2001 From: Andrea Venturi Date: Mon, 21 Mar 2016 17:10:38 +0100 Subject: [PATCH] clk: sunxi: mod1 clock should modify it's parent add CLK_SET_RATE_PARENT to modify the rate on clk upstream Signed-off-by: Marcus Cooper Signed-off-by: Maxime Ripard --- drivers/clk/sunxi/clk-a10-mod1.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/sunxi/clk-a10-mod1.c b/drivers/clk/sunxi/clk-a10-mod1.c index e9d870de165c..e2819fa09637 100644 --- a/drivers/clk/sunxi/clk-a10-mod1.c +++ b/drivers/clk/sunxi/clk-a10-mod1.c @@ -62,7 +62,7 @@ static void __init sun4i_mod1_clk_setup(struct device_node *node) clk = clk_register_composite(NULL, clk_name, parents, i, &mux->hw, &clk_mux_ops, NULL, NULL, - &gate->hw, &clk_gate_ops, 0); + &gate->hw, &clk_gate_ops, CLK_SET_RATE_PARENT); if (IS_ERR(clk)) goto err_free_gate; -- 2.39.5