From b5bae71a79d712681bdf48ee029f1953697924f7 Mon Sep 17 00:00:00 2001 From: Russell King Date: Mon, 30 Jul 2018 11:52:34 +0100 Subject: [PATCH] drm/armada: push interlace calculation into armada_drm_plane_calc() Push the interlaced frame calculation down into armada_drm_plane_calc() which needs to apply the same correction for both the overlay and primary planes. Signed-off-by: Russell King --- drivers/gpu/drm/armada/armada_overlay.c | 16 +++++------ drivers/gpu/drm/armada/armada_plane.c | 38 +++++++++++++------------ drivers/gpu/drm/armada/armada_plane.h | 4 +-- 3 files changed, 30 insertions(+), 28 deletions(-) diff --git a/drivers/gpu/drm/armada/armada_overlay.c b/drivers/gpu/drm/armada/armada_overlay.c index f36f6fb919e7..7de8b6bd7847 100644 --- a/drivers/gpu/drm/armada/armada_overlay.c +++ b/drivers/gpu/drm/armada/armada_overlay.c @@ -131,21 +131,21 @@ static void armada_drm_overlay_plane_atomic_update(struct drm_plane *plane, old_state->fb != state->fb) { const struct drm_format_info *format; u16 src_x, pitches[3]; - u32 addrs[3]; + u32 addrs[2][3]; - armada_drm_plane_calc(state, addrs, pitches); + armada_drm_plane_calc(state, addrs, pitches, false); - armada_reg_queue_set(regs, idx, addrs[0], + armada_reg_queue_set(regs, idx, addrs[0][0], LCD_SPU_DMA_START_ADDR_Y0); - armada_reg_queue_set(regs, idx, addrs[1], + armada_reg_queue_set(regs, idx, addrs[0][1], LCD_SPU_DMA_START_ADDR_U0); - armada_reg_queue_set(regs, idx, addrs[2], + armada_reg_queue_set(regs, idx, addrs[0][2], LCD_SPU_DMA_START_ADDR_V0); - armada_reg_queue_set(regs, idx, addrs[0], + armada_reg_queue_set(regs, idx, addrs[1][0], LCD_SPU_DMA_START_ADDR_Y1); - armada_reg_queue_set(regs, idx, addrs[1], + armada_reg_queue_set(regs, idx, addrs[1][1], LCD_SPU_DMA_START_ADDR_U1); - armada_reg_queue_set(regs, idx, addrs[2], + armada_reg_queue_set(regs, idx, addrs[1][2], LCD_SPU_DMA_START_ADDR_V1); val = pitches[0] << 16 | pitches[0]; diff --git a/drivers/gpu/drm/armada/armada_plane.c b/drivers/gpu/drm/armada/armada_plane.c index 3c9414c56aca..1320fec4c386 100644 --- a/drivers/gpu/drm/armada/armada_plane.c +++ b/drivers/gpu/drm/armada/armada_plane.c @@ -35,8 +35,8 @@ static const uint32_t armada_primary_formats[] = { DRM_FORMAT_BGR565, }; -void armada_drm_plane_calc(struct drm_plane_state *state, u32 addrs[3], - u16 pitches[3]) +void armada_drm_plane_calc(struct drm_plane_state *state, u32 addrs[2][3], + u16 pitches[3], bool interlaced) { struct drm_framebuffer *fb = state->fb; const struct drm_format_info *format = fb->format; @@ -52,43 +52,45 @@ void armada_drm_plane_calc(struct drm_plane_state *state, u32 addrs[3], if (num_planes > 3) num_planes = 3; - addrs[0] = addr + fb->offsets[0] + y * fb->pitches[0] + - x * format->cpp[0]; + addrs[0][0] = addr + fb->offsets[0] + y * fb->pitches[0] + + x * format->cpp[0]; pitches[0] = fb->pitches[0]; y /= format->vsub; x /= format->hsub; for (i = 1; i < num_planes; i++) { - addrs[i] = addr + fb->offsets[i] + y * fb->pitches[i] + - x * format->cpp[i]; + addrs[0][i] = addr + fb->offsets[i] + y * fb->pitches[i] + + x * format->cpp[i]; pitches[i] = fb->pitches[i]; } for (; i < 3; i++) { - addrs[i] = 0; + addrs[0][i] = 0; pitches[i] = 0; } + if (interlaced) { + for (i = 0; i < 3; i++) { + addrs[1][i] = addrs[0][i] + pitches[i]; + pitches[i] *= 2; + } + } else { + for (i = 0; i < 3; i++) + addrs[1][i] = addrs[0][i]; + } } static unsigned armada_drm_crtc_calc_fb(struct drm_plane_state *state, struct armada_regs *regs, bool interlaced) { u16 pitches[3]; - u32 addrs[3], addr_odd, addr_even; + u32 addrs[2][3]; unsigned i = 0; - armada_drm_plane_calc(state, addrs, pitches); - - addr_odd = addr_even = addrs[0]; - - if (interlaced) { - addr_even += pitches[0]; - pitches[0] *= 2; - } + armada_drm_plane_calc(state, addrs, pitches, interlaced); /* write offset, base, and pitch */ - armada_reg_queue_set(regs, i, addr_odd, LCD_CFG_GRA_START_ADDR0); - armada_reg_queue_set(regs, i, addr_even, LCD_CFG_GRA_START_ADDR1); + armada_reg_queue_set(regs, i, addrs[0][0], LCD_CFG_GRA_START_ADDR0); + armada_reg_queue_set(regs, i, addrs[1][0], LCD_CFG_GRA_START_ADDR1); armada_reg_queue_mod(regs, i, pitches[0], 0xffff, LCD_CFG_GRA_PITCH); return i; diff --git a/drivers/gpu/drm/armada/armada_plane.h b/drivers/gpu/drm/armada/armada_plane.h index 98280beaaa44..1bd8430992e0 100644 --- a/drivers/gpu/drm/armada/armada_plane.h +++ b/drivers/gpu/drm/armada/armada_plane.h @@ -1,8 +1,8 @@ #ifndef ARMADA_PLANE_H #define ARMADA_PLANE_H -void armada_drm_plane_calc(struct drm_plane_state *state, u32 addrs[3], - u16 pitches[3]); +void armada_drm_plane_calc(struct drm_plane_state *state, u32 addrs[2][3], + u16 pitches[3], bool interlaced); int armada_drm_plane_prepare_fb(struct drm_plane *plane, struct drm_plane_state *state); void armada_drm_plane_cleanup_fb(struct drm_plane *plane, -- 2.39.5