From e0ec45063609b4a583e7f4d843275888f2480321 Mon Sep 17 00:00:00 2001 From: Felix Kuehling Date: Mon, 15 May 2017 04:08:28 -0400 Subject: [PATCH] drm/amd/powerplay: Fix Vega10 power profile switching Clock index 0 is a valid index that is needed to restore the default graphics power profile. Use ~0 to indicate a failure to find a clock index. This fixes the clocks getting stuck in the compute power profile after running a compute application on Vega10. Signed-off-by: Felix Kuehling Signed-off-by: Eric Huang Reviewed-by: Tom St Denis Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c index 825178b5c284..f0c3a8bc1e11 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c @@ -4583,7 +4583,7 @@ static int vega10_set_power_profile_state(struct pp_hwmgr *hwmgr, struct amd_pp_profile *request) { struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend); - uint32_t sclk_idx = 0, mclk_idx = 0; + uint32_t sclk_idx = ~0, mclk_idx = ~0; if (hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_AUTO) return -EINVAL; @@ -4591,7 +4591,7 @@ static int vega10_set_power_profile_state(struct pp_hwmgr *hwmgr, vega10_find_min_clock_index(hwmgr, &sclk_idx, &mclk_idx, request->min_sclk, request->min_mclk); - if (sclk_idx) { + if (sclk_idx != ~0) { if (!data->registry_data.sclk_dpm_key_disabled) PP_ASSERT_WITH_CODE( !smum_send_msg_to_smc_with_parameter( @@ -4602,7 +4602,7 @@ static int vega10_set_power_profile_state(struct pp_hwmgr *hwmgr, return -EINVAL); } - if (mclk_idx) { + if (mclk_idx != ~0) { if (!data->registry_data.mclk_dpm_key_disabled) PP_ASSERT_WITH_CODE( !smum_send_msg_to_smc_with_parameter( -- 2.39.5