From e37e6ee6e100ebc355b4a48ae9a7802b38b8dac0 Mon Sep 17 00:00:00 2001 From: aurel32 Date: Tue, 7 Apr 2009 21:47:27 +0000 Subject: [PATCH] Allow 5 mmu indexes. This is necessary for alpha because it has 4 protection levels and pal mode. Signed-off-by: Tristan Gingold Signed-off-by: Aurelien Jarno git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7028 c046a42c-6fe2-441c-8c8c-71466251a162 --- exec.c | 30 +++++++++++++++++++++++++----- softmmu_exec.h | 29 ++++++++++++++++++++++++----- 2 files changed, 49 insertions(+), 10 deletions(-) diff --git a/exec.c b/exec.c index 94bc92802..b41edef48 100644 --- a/exec.c +++ b/exec.c @@ -1734,12 +1734,18 @@ void tlb_flush(CPUState *env, int flush_global) env->tlb_table[2][i].addr_read = -1; env->tlb_table[2][i].addr_write = -1; env->tlb_table[2][i].addr_code = -1; -#if (NB_MMU_MODES == 4) +#endif +#if (NB_MMU_MODES >= 4) env->tlb_table[3][i].addr_read = -1; env->tlb_table[3][i].addr_write = -1; env->tlb_table[3][i].addr_code = -1; #endif +#if (NB_MMU_MODES >= 5) + env->tlb_table[4][i].addr_read = -1; + env->tlb_table[4][i].addr_write = -1; + env->tlb_table[4][i].addr_code = -1; #endif + } memset (env->tb_jmp_cache, 0, TB_JMP_CACHE_SIZE * sizeof (void *)); @@ -1783,9 +1789,12 @@ void tlb_flush_page(CPUState *env, target_ulong addr) tlb_flush_entry(&env->tlb_table[1][i], addr); #if (NB_MMU_MODES >= 3) tlb_flush_entry(&env->tlb_table[2][i], addr); -#if (NB_MMU_MODES == 4) +#endif +#if (NB_MMU_MODES >= 4) tlb_flush_entry(&env->tlb_table[3][i], addr); #endif +#if (NB_MMU_MODES >= 5) + tlb_flush_entry(&env->tlb_table[4][i], addr); #endif tlb_flush_jmp_cache(env, addr); @@ -1869,10 +1878,14 @@ void cpu_physical_memory_reset_dirty(ram_addr_t start, ram_addr_t end, #if (NB_MMU_MODES >= 3) for(i = 0; i < CPU_TLB_SIZE; i++) tlb_reset_dirty_range(&env->tlb_table[2][i], start1, length); -#if (NB_MMU_MODES == 4) +#endif +#if (NB_MMU_MODES >= 4) for(i = 0; i < CPU_TLB_SIZE; i++) tlb_reset_dirty_range(&env->tlb_table[3][i], start1, length); #endif +#if (NB_MMU_MODES >= 5) + for(i = 0; i < CPU_TLB_SIZE; i++) + tlb_reset_dirty_range(&env->tlb_table[4][i], start1, length); #endif } } @@ -1918,10 +1931,14 @@ void cpu_tlb_update_dirty(CPUState *env) #if (NB_MMU_MODES >= 3) for(i = 0; i < CPU_TLB_SIZE; i++) tlb_update_dirty(&env->tlb_table[2][i]); -#if (NB_MMU_MODES == 4) +#endif +#if (NB_MMU_MODES >= 4) for(i = 0; i < CPU_TLB_SIZE; i++) tlb_update_dirty(&env->tlb_table[3][i]); #endif +#if (NB_MMU_MODES >= 5) + for(i = 0; i < CPU_TLB_SIZE; i++) + tlb_update_dirty(&env->tlb_table[4][i]); #endif } @@ -1943,9 +1960,12 @@ static inline void tlb_set_dirty(CPUState *env, target_ulong vaddr) tlb_set_dirty1(&env->tlb_table[1][i], vaddr); #if (NB_MMU_MODES >= 3) tlb_set_dirty1(&env->tlb_table[2][i], vaddr); -#if (NB_MMU_MODES == 4) +#endif +#if (NB_MMU_MODES >= 4) tlb_set_dirty1(&env->tlb_table[3][i], vaddr); #endif +#if (NB_MMU_MODES >= 5) + tlb_set_dirty1(&env->tlb_table[4][i], vaddr); #endif } diff --git a/softmmu_exec.h b/softmmu_exec.h index 9cc4535b6..a43e62194 100644 --- a/softmmu_exec.h +++ b/softmmu_exec.h @@ -60,6 +60,7 @@ #include "softmmu_header.h" #undef ACCESS_TYPE #undef MEMSUFFIX +#endif /* (NB_MMU_MODES >= 3) */ #if (NB_MMU_MODES >= 4) @@ -78,12 +79,30 @@ #include "softmmu_header.h" #undef ACCESS_TYPE #undef MEMSUFFIX +#endif /* (NB_MMU_MODES >= 4) */ -#if (NB_MMU_MODES > 4) -#error "NB_MMU_MODES > 4 is not supported for now" -#endif /* (NB_MMU_MODES > 4) */ -#endif /* (NB_MMU_MODES == 4) */ -#endif /* (NB_MMU_MODES >= 3) */ +#if (NB_MMU_MODES >= 5) + +#define ACCESS_TYPE 4 +#define MEMSUFFIX MMU_MODE4_SUFFIX +#define DATA_SIZE 1 +#include "softmmu_header.h" + +#define DATA_SIZE 2 +#include "softmmu_header.h" + +#define DATA_SIZE 4 +#include "softmmu_header.h" + +#define DATA_SIZE 8 +#include "softmmu_header.h" +#undef ACCESS_TYPE +#undef MEMSUFFIX +#endif /* (NB_MMU_MODES >= 5) */ + +#if (NB_MMU_MODES > 5) +#error "NB_MMU_MODES > 5 is not supported for now" +#endif /* (NB_MMU_MODES > 5) */ /* these access are slower, they must be as rare as possible */ #define ACCESS_TYPE (NB_MMU_MODES) -- 2.39.2