From fef5272652ffbbb2cfe827b79f00cf8e1c17a233 Mon Sep 17 00:00:00 2001 From: andrewfish Date: Thu, 4 Feb 2010 18:16:22 +0000 Subject: [PATCH] More disasm work. git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@9932 6f19259b-4bc3-4df7-8a09-765794883524 --- .../ArmDisassemblerLib/ThumbDisassembler.c | 91 ++++++++++++++++--- 1 file changed, 80 insertions(+), 11 deletions(-) diff --git a/ArmPkg/Library/ArmDisassemblerLib/ThumbDisassembler.c b/ArmPkg/Library/ArmDisassemblerLib/ThumbDisassembler.c index f9c84bb890..c2df0d4c72 100644 --- a/ArmPkg/Library/ArmDisassemblerLib/ThumbDisassembler.c +++ b/ArmPkg/Library/ArmDisassemblerLib/ThumbDisassembler.c @@ -90,6 +90,14 @@ extern CHAR8 *gReg[]; #define ADD_IMM5_2REG 228 #define CPD_THUMB2 229 #define THUMB2_4REGS 230 +#define ADD_IMM12_1REG 231 +#define THUMB2_IMM16 232 +#define MRC_THUMB2 233 +#define MRRC_THUMB2 234 +#define THUMB2_MRS 235 +#define THUMB2_MSR 236 + + typedef struct { @@ -210,6 +218,10 @@ THUMB_INSTRUCTIONS gOpThumb2[] = { { "TST", 0xf0100f00, 0xfff08f00, CMN_THUMB2 }, // CMP , # { "TST", 0xea100f00, 0xfff08f00, ADD_IMM5_2REG }, // TST , {, #} + { "MOV", 0xf04f0000, 0xfbef8000, ADD_IMM12_1REG }, // MOV , # + { "MOVW", 0xf2400000, 0xfbe08000, THUMB2_IMM16 }, // MOVW , # + { "MOVT", 0xf2c00000, 0xfbe08000, THUMB2_IMM16 }, // MOVT , # + { "ADC", 0xf1400000, 0xfbe08000, ADD_IMM12 }, // ADC{S} , , # { "ADC", 0xeb400000, 0xffe08000, ADD_IMM5 }, // ADC{S} , , {, #} { "ADD", 0xf1000000, 0xfbe08000, ADD_IMM12 }, // ADD{S} , , # @@ -247,6 +259,14 @@ THUMB_INSTRUCTIONS gOpThumb2[] = { { "CPD", 0xee000000, 0xff000010, CPD_THUMB2 }, // CPD ,,,,, { "CPD2", 0xfe000000, 0xff000010, CPD_THUMB2 }, // CPD ,,,,, + { "MRC", 0xee100000, 0xff100000, MRC_THUMB2 }, // MRC ,,,,, + { "MRC2", 0xfe100000, 0xff100000, MRC_THUMB2 }, // MRC2 ,,,,, + { "MRRC", 0xec500000, 0xfff00000, MRRC_THUMB2 }, // MRRC ,,,, + { "MRRC2", 0xfc500000, 0xfff00000, MRRC_THUMB2 }, // MRR2 ,,,, + + { "MRS", 0xf3ef8000, 0xfffff0ff, THUMB2_MRS }, // MRS , CPSR + { "MSR", 0xf3808000, 0xfff0fcff, THUMB2_MSR }, // MSR CPSR_fs, + { "CLREX", 0xf3bf8f2f, 0xfffffff, THUMB2_NO_ARGS }, // CLREX { "CLZ", 0xfab0f080, 0xfff0f0f0, THUMB2_2REGS }, // CLZ , @@ -267,17 +287,17 @@ THUMB_INSTRUCTIONS gOpThumb2[] = { { "SMLABT", 0xfb100010, 0xfff000f0, THUMB2_4REGS }, // SMLABT , , , { "SMLABB", 0xfb100020, 0xfff000f0, THUMB2_4REGS }, // SMLATB , , , { "SMLATT", 0xfb100030, 0xfff000f0, THUMB2_4REGS }, // SMLATT , , , - { "SMLAWB", 0xfb300000, 0xfff000f0, THUMB2_4REGS },// SMLAWB , , , - { "SMLAWT", 0xfb300010, 0xfff000f0, THUMB2_4REGS },// SMLAWT , , , - { "SMLSD", 0xfb400000, 0xfff000f0, THUMB2_4REGS },// SMLSD , , , - { "SMLSDX", 0xfb400010, 0xfff000f0, THUMB2_4REGS },// SMLSDX , , , - { "SMMLA", 0xfb500000, 0xfff000f0, THUMB2_4REGS },// SMMLA , , , - { "SMMLAR", 0xfb500010, 0xfff000f0, THUMB2_4REGS },// SMMLAR , , , - { "SMMLS", 0xfb600000, 0xfff000f0, THUMB2_4REGS },// SMMLS , , , - { "SMMLSR", 0xfb600010, 0xfff000f0, THUMB2_4REGS },// SMMLSR , , , - { "USADA8", 0xfb700000, 0xfff000f0, THUMB2_4REGS },// USADA8 , , , - { "SMLAD", 0xfb200000, 0xfff000f0, THUMB2_4REGS },// SMLAD , , , - { "SMLADX", 0xfb200010, 0xfff000f0, THUMB2_4REGS },// SMLADX , , , + { "SMLAWB", 0xfb300000, 0xfff000f0, THUMB2_4REGS }, // SMLAWB , , , + { "SMLAWT", 0xfb300010, 0xfff000f0, THUMB2_4REGS }, // SMLAWT , , , + { "SMLSD", 0xfb400000, 0xfff000f0, THUMB2_4REGS }, // SMLSD , , , + { "SMLSDX", 0xfb400010, 0xfff000f0, THUMB2_4REGS }, // SMLSDX , , , + { "SMMLA", 0xfb500000, 0xfff000f0, THUMB2_4REGS }, // SMMLA , , , + { "SMMLAR", 0xfb500010, 0xfff000f0, THUMB2_4REGS }, // SMMLAR , , , + { "SMMLS", 0xfb600000, 0xfff000f0, THUMB2_4REGS }, // SMMLS , , , + { "SMMLSR", 0xfb600010, 0xfff000f0, THUMB2_4REGS }, // SMMLSR , , , + { "USADA8", 0xfb700000, 0xfff000f0, THUMB2_4REGS }, // USADA8 , , , + { "SMLAD", 0xfb200000, 0xfff000f0, THUMB2_4REGS }, // SMLAD , , , + { "SMLADX", 0xfb200010, 0xfff000f0, THUMB2_4REGS }, // SMLADX , , , { "B", 0xf0008000, 0xf800d000, B_T3 }, // B