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drm/i915: decouple gen9 and gen10 dp signal levels.
2017-08-31 Rodrigo Vividrm/i915: decouple gen9 and gen10 dp signal levels.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...msgid/20170829232230.23051-2-rodrigo.vivi@intel.com
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2017-08-31 Rodrigo Vividrm/i915: Introduce intel_ddi_dp_level.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...msgid/20170829232230.23051-1-rodrigo.vivi@intel.com
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2017-08-31 Rodrigo Vividrm/i915/cnl: Avoid ioremap_wc on Cannonlake as well.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...msgid/20170829230907.21363-1-rodrigo.vivi@intel.com
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2017-08-31 Rodrigo Vividrm/i915/cnl: WaDisableI2mCycleOnWRPort
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...msgid/20170829230751.21047-1-rodrigo.vivi@intel.com
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2017-08-31 Rodrigo Vividrm/i915/cnl: WA FtrEnableFastAnisoL1BankingFix
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...msgid/20170829230723.20898-1-rodrigo.vivi@intel.com
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2017-08-31 Rodrigo Vividrm/i915: Stop using long platform names on clock gating...
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...msgid/20170829052026.15038-1-rodrigo.vivi@intel.com
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2017-08-24 Oscar Mateodrm/i915: Make some RPS functions static
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2017-08-23 Rodrigo Vividrm/i915/cnl: WaForceContextSaveRestoreNonCoherent
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...msgid/20170823203504.10012-1-rodrigo.vivi@intel.com
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2017-08-23 Oscar Mateodrm/i915/cnl: WaPushConstantDereferenceHoldDisable
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2017-08-22 Rodrigo Vividrm/i915/cfl: Coffee Lake works on Kaby Lake PCH.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...patch/msgid/20170821235056.9015-1-rodrigo.vivi@intel.com
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2017-08-22 Paulo Zanonidrm/i915/cnl: extract cnl_set_procmon_ref_values
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...msgid/20170822000356.17330-2-rodrigo.vivi@intel.com
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2017-08-22 Paulo Zanonidrm/i915/cnl: simplify cnl_procmon_values handling
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...msgid/20170822000356.17330-1-rodrigo.vivi@intel.com
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2017-08-18 Rodrigo Vividrm/i915/cnl: Apply large line width optimization
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...patch/msgid/20170815231651.975-4-rodrigo.vivi@intel.com
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2017-08-18 Rodrigo Vividrm/i915/cnl: WaDisableEnhancedSBEVertexCaching
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...patch/msgid/20170815231651.975-3-rodrigo.vivi@intel.com
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2017-08-18 Rodrigo Vividrm/i915/cnl: Add WaDisableReplayBufferBankArbitrationOptimi...
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...patch/msgid/20170815231651.975-2-rodrigo.vivi@intel.com
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2017-08-18 Rodrigo Vividrm/i915/cnl: Introduce initial Cannonlake Workarounds.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...patch/msgid/20170815231651.975-1-rodrigo.vivi@intel.com
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2017-08-16 Rodrigo Vividrm/i915/cnl: Reuse skl_wm_get_hw_state on Cannonlake.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...msgid/20170809205248.11917-6-rodrigo.vivi@intel.com
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2017-08-16 Paulo Zanonidrm/i915/gen10: implement gen 10 watermarks calculations
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...msgid/20170811233825.32083-1-rodrigo.vivi@intel.com
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2017-08-16 Rodrigo Vividrm/i915/cnl: Fix LSPCON support.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...msgid/20170816030403.11368-1-rodrigo.vivi@intel.com
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2017-08-15 Rodrigo Vividrm/i915/cnl: Setup PAT Index.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...patch/msgid/20170815232539.3562-1-rodrigo.vivi@intel.com
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2017-08-15 Jim Bridedrm/i915/edp: Allow alternate fixed mode for eDP if...
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2017-08-11 Rodrigo Vividrm/i915: Introduce intel_hpd_pin function.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...msgid/20170811182650.14327-2-rodrigo.vivi@intel.com
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2017-08-11 Rodrigo Vividrm/i915: Simplify hpd pin to port
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...msgid/20170811182650.14327-1-rodrigo.vivi@intel.com
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2017-08-11 Rodrigo Vividrm/i915/cnl: Dump the right pll registers when dumping...
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...msgid/20170810224525.18278-1-rodrigo.vivi@intel.com
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2017-08-11 Rodrigo Vividrm/i915/cnl: Add allowed DP rates for Cannonlake.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...msgid/20170810224008.15571-1-rodrigo.vivi@intel.com
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2017-08-11 Matthias Kaehlckedrm/i915: Return correct EDP voltage swing table for...
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2017-08-10 Rodrigo Vividrm/i915/cnl: Add slice and subslice information to...
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...msgid/20170809200702.11236-1-rodrigo.vivi@intel.com
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2017-08-10 Paulo Zanonidrm/i915/gen10: fix WM latency printing
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...msgid/20170809205248.11917-4-rodrigo.vivi@intel.com
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2017-08-10 Paulo Zanonidrm/i915/gen10: fix the gen 10 SAGV block time
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...msgid/20170809205248.11917-3-rodrigo.vivi@intel.com
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2017-08-10 Rodrigo Vividrm/i915/cnl: Enable SAGV for Cannonlake.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...msgid/20170809205248.11917-2-rodrigo.vivi@intel.com
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2017-08-10 Paulo Zanonidrm/i915/gen10+: use the SKL code for reading WM latencies
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...msgid/20170809205248.11917-1-rodrigo.vivi@intel.com
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2017-08-10 Rodrigo Vividrm/i915: Avoid null dereference if mst_port is unset.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...msgid/20170810145043.24047-1-rodrigo.vivi@intel.com
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2017-08-09 Jim Bridedrm/i915/psr: Preserve SRD_CTL bit 29 on PSR init
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2017-08-08 Rodrigo Vividrm/i915/cnl: Removing missing DDI_E bits from CNL.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...msgid/20170808193237.17410-1-rodrigo.vivi@intel.com
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2017-08-03 Praveen Paneridrm/i915: enable WaDisableDopClkGating for skl
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2017-08-03 Rodrigo Vividrm/i915: Fix PCH names for KBP and CNP.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...patch/msgid/20170731185220.758-1-rodrigo.vivi@intel.com
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2017-07-11 Rodrigo Vividrm/i915/cnl: Add missing type case.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...msgid/20170710205852.28352-1-rodrigo.vivi@intel.com
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2017-07-10 Rodrigo Vividrm/i915/cnl: Add max allowed Cannonlake DC.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...1499373908-26761-1-git-send-email-rodrigo.vivi@intel.com
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2017-07-07 Rodrigo Vividrm/i915/cnl: Get DDI clock based on PLLs.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...1499374321-31152-1-git-send-email-rodrigo.vivi@intel.com
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2017-07-07 Rodrigo Vividrm/i915/cnl: Inherit RPS stuff from previous platforms.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...1499373673-25066-1-git-send-email-rodrigo.vivi@intel.com
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2017-07-07 Rodrigo Vividrm/i915/cnl: Gen10 render context size.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...1499375184-5725-1-git-send-email-rodrigo.vivi@intel.com
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2017-07-07 Rodrigo Vividrm/i915/cnl: Don't trust VBT's alternate pin for port...
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...1499375295-6454-1-git-send-email-rodrigo.vivi@intel.com
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2017-07-06 Rodrigo Vividrm/i915/cnl: Cannonlake color init.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...1499374873-2454-1-git-send-email-rodrigo.vivi@intel.com
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2017-07-06 Rodrigo Vividrm/i915/cnl: Add force wake for gen10+.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...1499302831-17773-1-git-send-email-rodrigo.vivi@intel.com
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2017-07-06 Paulo Zanonix86/gpu: CNL uses the same GMS values as SKL
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...1499302845-17856-1-git-send-email-rodrigo.vivi@intel.com
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2017-06-30 Navare, Manasi Ddrm/i915/cnl: Fix the CURSOR_COEFF_MASK used in DDI...
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2017-06-29 Rodrigo Vividrm/i915/cfl: Fix Workarounds.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2017-06-19 Rodrigo Vividrm/i915/cnl: Fix RMW on ddi vswing sequence.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...1497897572-22520-1-git-send-email-rodrigo.vivi@intel.com
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2017-06-16 Rodrigo Vividrm/i915/cfl: Introduce Coffee Lake workarounds.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...1497653398-15722-1-git-send-email-rodrigo.vivi@intel.com
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2017-06-15 Rodrigo ViviRevert "drm/i915/skl: New ddb allocation algorithm"
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...1497376350-3400-1-git-send-email-rodrigo.vivi@intel.com
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2017-06-12 Rodrigo Vividrm/i915/cfl: Basic DDI plumbing for Coffee Lake.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...1497045770-21302-1-git-send-email-rodrigo.vivi@intel.com
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2017-06-12 Kahola, Mikadrm/i915/cnl: Enable wrpll computation for CNL
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...1497047175-27250-18-git-send-email-rodrigo.vivi@intel.com
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2017-06-12 Rodrigo Vividrm/i915/cnl: LSPCON support is gen9+
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...1497047175-27250-17-git-send-email-rodrigo.vivi@intel.com
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2017-06-12 Rodrigo Vividrm/i915/cnl: Enable fifo underrun for Cannonlake.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...1497047175-27250-16-git-send-email-rodrigo.vivi@intel.com
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2017-06-12 Rodrigo Vividrm/i915/cnl: Fix Cannonlake scaler mode programing.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...1497047175-27250-15-git-send-email-rodrigo.vivi@intel.com
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2017-06-12 Rodrigo Vividrm/i915: Use HAS_CSR instead of gen number on DMC...
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...1497047175-27250-14-git-send-email-rodrigo.vivi@intel.com
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2017-06-12 Anusha Srivatsadrm/i915/DMC/CNL: Load DMC on CNL
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...1497047175-27250-13-git-send-email-rodrigo.vivi@intel.com
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2017-06-12 Clint Taylordrm/i915/cnl: Enable loadgen_select bit for vswing...
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...1497047175-27250-12-git-send-email-rodrigo.vivi@intel.com
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2017-06-12 Rodrigo Vividrm/i915/cnl: Implement voltage swing sequence.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...1497047175-27250-11-git-send-email-rodrigo.vivi@intel.com
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2017-06-12 Rodrigo Vividrm/i915/cnl: Add DDI Buffer translation tables for...
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...1497047175-27250-10-git-send-email-rodrigo.vivi@intel.com
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2017-06-12 Rodrigo Vividrm/i915/cnl: Add registers related to voltage swing...
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...1497047175-27250-9-git-send-email-rodrigo.vivi@intel.com
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2017-06-12 Rodrigo Vividrm/i915: Add MMIO helper for 6 ports with different...
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...1497047175-27250-8-git-send-email-rodrigo.vivi@intel.com
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2017-06-12 Rodrigo Vividrm/i915/cnl: Initialize PLLs
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...1497047175-27250-7-git-send-email-rodrigo.vivi@intel.com
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2017-06-12 Kahola, Mikadrm/i915: Configure DPLL's for Cannonlake
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...1497047175-27250-6-git-send-email-rodrigo.vivi@intel.com
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2017-06-12 Rodrigo Vividrm/i915/cnl: DDI - PLL mapping
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...1497047175-27250-5-git-send-email-rodrigo.vivi@intel.com
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2017-06-12 Rodrigo Vividrm/i915/cnl: Allow dynamic cdclk changes on CNL
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...1497047175-27250-4-git-send-email-rodrigo.vivi@intel.com
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2017-06-12 Ville Syrjälädrm/i915/cnl: Implement CNL display init/unit sequence
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...1497047175-27250-3-git-send-email-rodrigo.vivi@intel.com
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2017-06-12 Ville Syrjälädrm/i915/cnl: Implement .set_cdclk() for CNL
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...1497047175-27250-2-git-send-email-rodrigo.vivi@intel.com
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2017-06-12 Ville Syrjälädrm/i915/cnl: Implement .get_display_clock_speed()...
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...1497047175-27250-1-git-send-email-rodrigo.vivi@intel.com
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2017-06-09 Rodrigo Vividrm/i915/cfl: Coffee Lake reuses Kabylake DMC.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...1497038550-30910-1-git-send-email-rodrigo.vivi@intel.com
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2017-06-09 Anusha Srivatsadrm/i915/huc: Load HuC on Coffee Lake
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2017-06-09 Anusha Srivatsadrm/i915/guc: Load GuC on Coffee Lake
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2017-06-09 Anusha Srivatsadrm/i915/cfl: Add Coffee Lake PCI IDs for U Sku.
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2017-06-09 Anusha Srivatsadrm/i915/cfl: Add Coffee Lake PCI IDs for H Sku.
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2017-06-09 Anusha Srivatsadrm/i915/cfl: Add Coffee Lake PCI IDs for S Skus.
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2017-06-08 Rodrigo Vividrm/i915/cfl: Introduce Display workarounds for Coffee...
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...1496937000-8450-3-git-send-email-rodrigo.vivi@intel.com
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2017-06-08 Rodrigo Vividrm/i915/cfl: Coffee Lake uses CNP PCH.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...1496937000-8450-2-git-send-email-rodrigo.vivi@intel.com
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2017-06-08 Rodrigo Vividrm/i915/cfl: Introduce Coffee Lake platform definition.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...1496937000-8450-1-git-send-email-rodrigo.vivi@intel.com
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2017-06-07 Rodrigo Vividrm/i915: Unify GT* and GT3 definitions
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...1496765166-7068-1-git-send-email-rodrigo.vivi@intel.com
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2017-06-07 Rodrigo Vividrm/i915: Remove unnecessary PORT3 definition.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...1496700722-13755-1-git-send-email-rodrigo.vivi@intel.com
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2017-06-07 Rodrigo Vividrm/i915/cnl: Also need power well sanitize.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...1496781040-20888-11-git-send-email-rodrigo.vivi@intel.com
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2017-06-07 Ville Syrjälädrm/i915/cnl: Add power wells for CNL
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...1496781040-20888-10-git-send-email-rodrigo.vivi@intel.com
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2017-06-07 Michel Thierrydrm/i915/gen10: Set value of Indirect Context Offset...
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...1496781040-20888-9-git-send-email-rodrigo.vivi@intel.com
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2017-06-07 Rodrigo Vividrm/i915/cnl: Cannonlake has same MOCS table than Skylake.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...1496781040-20888-8-git-send-email-rodrigo.vivi@intel.com
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2017-06-07 Rodrigo Vividrm/i915/cnl: Configure EU slice power gating.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...1496781040-20888-7-git-send-email-rodrigo.vivi@intel.com
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2017-06-07 James Irwindrm/i915/cnl: Cannonlake has 4 planes (3 sprites) per...
...1496781040-20888-6-git-send-email-rodrigo.vivi@intel.com
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2017-06-07 Paulo Zanonidrm/i915/cnl: add IS_CNL_REVID macro
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...1496781040-20888-5-git-send-email-rodrigo.vivi@intel.com
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2017-06-07 Rodrigo Vividrm/i915/cnl: Add Cannonlake PCI IDs for Y-skus.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...1496781040-20888-4-git-send-email-rodrigo.vivi@intel.com
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2017-06-07 Rodrigo Vividrm/i915/cnl: Add Cannonlake PCI IDs for U-skus.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...1496781040-20888-3-git-send-email-rodrigo.vivi@intel.com
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2017-06-07 Rodrigo Vividrm/i915/cnl: Cannonlake uses CNP PCH.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...1496781040-20888-2-git-send-email-rodrigo.vivi@intel.com
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2017-06-07 Rodrigo Vividrm/i915/cnl: Introduce Cannonlake platform defition.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...1496781040-20888-1-git-send-email-rodrigo.vivi@intel.com
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2017-06-02 Rodrigo Vividrm/i915/cnp: Panel Power sequence changes for CNP...
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...1496434004-29812-6-git-send-email-rodrigo.vivi@intel.com
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2017-06-02 Rodrigo Vividrm/i915/cnp: add CNP gmbus support
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...1496434004-29812-5-git-send-email-rodrigo.vivi@intel.com
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2017-06-02 Rodrigo Vividrm/i915/cnp: Backlight support for CNP.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...1496434004-29812-4-git-send-email-rodrigo.vivi@intel.com
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2017-06-02 Rodrigo Vividrm/i915/cnp: Get/set proper Raw clock frequency on...
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...1496434004-29812-3-git-send-email-rodrigo.vivi@intel.com
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2017-06-02 Dhinakaran Pandiyandrm/i915/cnp: Add PCI ID for Cannonpoint LP PCH
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...1496434004-29812-2-git-send-email-rodrigo.vivi@intel.com
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2017-06-02 Rodrigo Vividrm/i915/cnp: Introduce Cannonpoint PCH.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...1496434004-29812-1-git-send-email-rodrigo.vivi@intel.com
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2017-05-30 Nagaraju, Vathsaladrm/i915/psr: disable psr2 for resolution greater than...
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2017-01-24 Rodrigo Vividrm/i915: Introduce IS_GEN9_BC for Skylake and Kabylake.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...1485196357-30599-2-git-send-email-rodrigo.vivi@intel.com
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2017-01-24 Rodrigo Vividrm/i915/kbl: Apply WaIncreaseDefaultTLBEntries on...
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...1485196357-30599-1-git-send-email-rodrigo.vivi@intel.com
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