projects / mirror_edk2.git / blame
| Commit | Line | Data |
|---|---|---|
| 8bbf0f09 A |
1 | #/** @file\r |
| 2 | # ARM processor package.\r | |
| 3 | #\r | |
| d6ebcab7 | 4 | # Copyright (c) 2009 - 2010, Apple Inc. All rights reserved.<BR>\r |
| d03f71dd | 5 | # Copyright (c) 2011 - 2021, ARM Limited. All rights reserved.\r |
| 62540372 | 6 | # Copyright (c) 2021, Ampere Computing LLC. All rights reserved.\r |
| 8bbf0f09 | 7 | #\r |
| 4059386c | 8 | # SPDX-License-Identifier: BSD-2-Clause-Patent\r |
| 8bbf0f09 A |
9 | #\r |
| 10 | #**/\r | |
| 11 | \r | |
| 2ef2b01e A |
12 | [Defines]\r |
| 13 | DEC_SPECIFICATION = 0x00010005\r | |
| 14 | PACKAGE_NAME = ArmPkg\r | |
| 15 | PACKAGE_GUID = 5CFBD99E-3C43-4E7F-8054-9CDEAFF7710F\r | |
| 16 | PACKAGE_VERSION = 0.1\r | |
| 17 | \r | |
| 18 | ################################################################################\r | |
| 19 | #\r | |
| 20 | # Include Section - list of Include Paths that are provided by this package.\r | |
| 21 | # Comments are used for Keywords and Module Types.\r | |
| 22 | #\r | |
| 23 | # Supported Module Types:\r | |
| 24 | # BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION\r | |
| 25 | #\r | |
| 26 | ################################################################################\r | |
| 27 | [Includes.common]\r | |
| 28 | Include # Root include for the package\r | |
| 29 | \r | |
| 30 | [LibraryClasses.common]\r | |
| a145d5f2 | 31 | ## @libraryclass Convert Arm instructions to a human readable format.\r |
| 3093c95d | 32 | #\r |
| a145d5f2 | 33 | ArmDisassemblerLib|Include/Library/ArmDisassemblerLib.h\r |
| 3093c95d | 34 | \r |
| a145d5f2 | 35 | ## @libraryclass Provides an interface to Arm generic counters.\r |
| 3093c95d | 36 | #\r |
| a145d5f2 | 37 | ArmGenericTimerCounterLib|Include/Library/ArmGenericTimerCounterLib.h\r |
| 3093c95d | 38 | \r |
| a145d5f2 PG |
39 | ## @libraryclass Provides an interface to initialize a\r |
| 40 | # Generic Interrupt Controller (GIC).\r | |
| 3093c95d | 41 | #\r |
| a145d5f2 | 42 | ArmGicArchLib|Include/Library/ArmGicArchLib.h\r |
| 3093c95d | 43 | \r |
| a145d5f2 PG |
44 | ## @libraryclass Provides a Generic Interrupt Controller (GIC)\r |
| 45 | # configuration interface.\r | |
| 3093c95d | 46 | #\r |
| a145d5f2 | 47 | ArmGicLib|Include/Library/ArmGicLib.h\r |
| 3093c95d | 48 | \r |
| a145d5f2 | 49 | ## @libraryclass Provides a HyperVisor Call (HVC) interface.\r |
| 3093c95d | 50 | #\r |
| a145d5f2 | 51 | ArmHvcLib|Include/Library/ArmHvcLib.h\r |
| 3093c95d | 52 | \r |
| a145d5f2 | 53 | ## @libraryclass Provides an interface to Arm registers.\r |
| 3093c95d | 54 | #\r |
| a145d5f2 PG |
55 | ArmLib|Include/Library/ArmLib.h\r |
| 56 | \r | |
| 57 | ## @libraryclass Provides a Mmu interface.\r | |
| 58 | #\r | |
| 59 | ArmMmuLib|Include/Library/ArmMmuLib.h\r | |
| 3093c95d PG |
60 | \r |
| 61 | ## @libraryclass Provides a Mailbox Transport Layer (MTL) interface\r | |
| 62 | # for the System Control and Management Interface (SCMI).\r | |
| 63 | #\r | |
| d03f71dd | 64 | ArmMtlLib|Include/Library/ArmMtlLib.h\r |
| 3093c95d | 65 | \r |
| a145d5f2 | 66 | ## @libraryclass Provides a System Monitor Call (SMC) interface.\r |
| 3093c95d | 67 | #\r |
| a145d5f2 | 68 | ArmSmcLib|Include/Library/ArmSmcLib.h\r |
| 3093c95d | 69 | \r |
| a145d5f2 | 70 | ## @libraryclass Provides a SuperVisor Call (SVC) interface.\r |
| 3093c95d | 71 | #\r |
| a145d5f2 | 72 | ArmSvcLib|Include/Library/ArmSvcLib.h\r |
| 3093c95d | 73 | \r |
| a145d5f2 | 74 | ## @libraryclass Provides a default exception handler.\r |
| 3093c95d | 75 | #\r |
| a145d5f2 | 76 | DefaultExceptionHandlerLib|Include/Library/DefaultExceptionHandlerLib.h\r |
| 3093c95d PG |
77 | \r |
| 78 | ## @libraryclass Provides an interface to query miscellaneous OEM\r | |
| 79 | # information.\r | |
| 80 | #\r | |
| d03f71dd | 81 | OemMiscLib|Include/Library/OemMiscLib.h\r |
| 3093c95d | 82 | \r |
| a145d5f2 | 83 | ## @libraryclass Provides an OpTee interface.\r |
| 3093c95d | 84 | #\r |
| a145d5f2 PG |
85 | OpteeLib|Include/Library/OpteeLib.h\r |
| 86 | \r | |
| 87 | ## @libraryclass Provides a semihosting interface.\r | |
| 88 | #\r | |
| 89 | SemihostLib|Include/Library/SemihostLib.h\r | |
| d03f71dd | 90 | \r |
| a145d5f2 PG |
91 | ## @libraryclass Provides an interface for a StandaloneMm Mmu.\r |
| 92 | #\r | |
| 93 | StandaloneMmMmuLib|Include/Library/StandaloneMmMmuLib.h\r | |
| c32aaba9 | 94 | \r |
| 2ef2b01e A |
95 | [Guids.common]\r |
| 96 | gArmTokenSpaceGuid = { 0xBB11ECFE, 0x820F, 0x4968, { 0xBB, 0xA6, 0xF7, 0x6A, 0xFE, 0x30, 0x25, 0x96 } }\r | |
| 97 | \r | |
| 44788bae | 98 | ## ARM MPCore table\r |
| 99 | # Include/Guid/ArmMpCoreInfo.h\r | |
| 100 | gArmMpCoreInfoGuid = { 0xa4ee0728, 0xe5d7, 0x4ac5, {0xb2, 0x1e, 0x65, 0x8e, 0xd8, 0x57, 0xe8, 0x34} }\r | |
| 101 | \r | |
| 31b16384 AB |
102 | gArmMmuReplaceLiveTranslationEntryFuncGuid = { 0xa8b50ff3, 0x08ec, 0x4dd3, {0xbf, 0x04, 0x28, 0xbf, 0x71, 0x75, 0xc7, 0x4a} }\r |
| 103 | \r | |
| 4f2494cf GP |
104 | [Protocols.common]\r |
| 105 | ## Arm System Control and Management Interface(SCMI) Base protocol\r | |
| 106 | ## ArmPkg/Include/Protocol/ArmScmiBaseProtocol.h\r | |
| 107 | gArmScmiBaseProtocolGuid = { 0xd7e5abe9, 0x33ab, 0x418e, { 0x9f, 0x91, 0x72, 0xda, 0xe2, 0xba, 0x8e, 0x2f } }\r | |
| 108 | \r | |
| 109 | ## Arm System Control and Management Interface(SCMI) Clock management protocol\r | |
| 110 | ## ArmPkg/Include/Protocol/ArmScmiClockProtocol.h\r | |
| 111 | gArmScmiClockProtocolGuid = { 0x91ce67a8, 0xe0aa, 0x4012, { 0xb9, 0x9f, 0xb6, 0xfc, 0xf3, 0x4, 0x8e, 0xaa } }\r | |
| 559a07d8 | 112 | gArmScmiClock2ProtocolGuid = { 0xb8d8caf2, 0x9e94, 0x462c, { 0xa8, 0x34, 0x6c, 0x99, 0xfc, 0x05, 0xef, 0xcf } }\r |
| 4f2494cf GP |
113 | \r |
| 114 | ## Arm System Control and Management Interface(SCMI) Clock management protocol\r | |
| 115 | ## ArmPkg/Include/Protocol/ArmScmiPerformanceProtocol.h\r | |
| 116 | gArmScmiPerformanceProtocolGuid = { 0x9b8ba84, 0x3dd3, 0x49a6, { 0xa0, 0x5a, 0x31, 0x34, 0xa5, 0xf0, 0x7b, 0xad } }\r | |
| 117 | \r | |
| 44788bae | 118 | [Ppis]\r |
| 119 | ## Include/Ppi/ArmMpCoreInfo.h\r | |
| 120 | gArmMpCoreInfoPpiGuid = { 0x6847cc74, 0xe9ec, 0x4f8f, {0xa2, 0x9d, 0xab, 0x44, 0xe7, 0x54, 0xa8, 0xfc} }\r | |
| 121 | \r | |
| 2ef2b01e A |
122 | [PcdsFeatureFlag.common]\r |
| 123 | gArmTokenSpaceGuid.PcdCpuDxeProduceDebugSupport|FALSE|BOOLEAN|0x00000001\r | |
| 124 | \r | |
| 1bfda055 | 125 | # On ARM Architecture with the Security Extension, the address for the\r |
| 126 | # Vector Table can be mapped anywhere in the memory map. It means we can\r | |
| 127 | # point the Exception Vector Table to its location in CpuDxe.\r | |
| f0bbcdf8 | 128 | # By default we copy the Vector Table at PcdGet64(PcdCpuVectorBaseAddress)\r |
| 1bfda055 | 129 | gArmTokenSpaceGuid.PcdRelocateVectorTable|TRUE|BOOLEAN|0x00000022\r |
| eeec69c5 | 130 | # Set this PCD to TRUE if the Exception Vector is changed to add debugger support before\r |
| 131 | # it has been configured by the CPU DXE\r | |
| 132 | gArmTokenSpaceGuid.PcdDebuggerExceptionSupport|FALSE|BOOLEAN|0x00000032\r | |
| c32aaba9 | 133 | \r |
| f6d46e29 AB |
134 | # Define if the GICv3 controller should use the GICv2 legacy\r |
| 135 | gArmTokenSpaceGuid.PcdArmGicV3WithV2Legacy|FALSE|BOOLEAN|0x00000042\r | |
| 136 | \r | |
| 65ceda91 AB |
137 | [PcdsFeatureFlag.ARM]\r |
| 138 | # Whether to map normal memory as non-shareable. FALSE is the safe choice, but\r | |
| 139 | # TRUE may be appropriate to fix performance problems if you don't care about\r | |
| 140 | # hardware coherency (i.e., no virtualization or cache coherent DMA)\r | |
| 141 | gArmTokenSpaceGuid.PcdNormalMemoryNonshareableOverride|FALSE|BOOLEAN|0x00000043\r | |
| 142 | \r | |
| aee0098f | 143 | [PcdsFeatureFlag.AARCH64, PcdsFeatureFlag.ARM]\r |
| ee283e33 SG |
144 | ## Used to select method for requesting services from S-EL1.<BR><BR>\r |
| 145 | # TRUE - Selects FF-A calls for communication between S-EL0 and SPMC.<BR>\r | |
| 146 | # FALSE - Selects SVC calls for communication between S-EL0 and SPMC.<BR>\r | |
| 147 | # @Prompt Enable FF-A support.\r | |
| 148 | gArmTokenSpaceGuid.PcdFfaEnable|FALSE|BOOLEAN|0x0000005B\r | |
| 149 | \r | |
| 2ef2b01e | 150 | [PcdsFixedAtBuild.common]\r |
| 12c5ae23 | 151 | gArmTokenSpaceGuid.PcdTrustzoneSupport|FALSE|BOOLEAN|0x00000006\r |
| 152 | \r | |
| 1bfda055 | 153 | # This PCD should be a FeaturePcd. But we used this PCD as an '#if' in an ASM file.\r |
| 154 | # Using a FeaturePcd make a '(BOOLEAN) casting for its value which is not understood by the preprocessor.\r | |
| 155 | gArmTokenSpaceGuid.PcdVFPEnabled|0|UINT32|0x00000024\r | |
| 156 | \r | |
| f0bbcdf8 | 157 | gArmTokenSpaceGuid.PcdCpuVectorBaseAddress|0xffff0000|UINT64|0x00000004\r |
| 2ef2b01e | 158 | gArmTokenSpaceGuid.PcdCpuResetAddress|0x00000000|UINT32|0x00000005\r |
| c32aaba9 | 159 | \r |
| 1bfda055 | 160 | #\r |
| 262a9b04 | 161 | # ARM Secure Firmware PCDs\r |
| 1bfda055 | 162 | #\r |
| bb5420bb | 163 | gArmTokenSpaceGuid.PcdSecureFdBaseAddress|0|UINT64|0x00000015\r |
| 1bfda055 | 164 | gArmTokenSpaceGuid.PcdSecureFdSize|0|UINT32|0x00000016\r |
| bb5420bb | 165 | gArmTokenSpaceGuid.PcdSecureFvBaseAddress|0x0|UINT64|0x0000002F\r |
| 1ad14bc8 | 166 | gArmTokenSpaceGuid.PcdSecureFvSize|0x0|UINT32|0x00000030\r |
| 1bfda055 | 167 | \r |
| 7245b435 | 168 | #\r |
| 169 | # ARM Hypervisor Firmware PCDs\r | |
| c32aaba9 | 170 | #\r |
| 7245b435 | 171 | gArmTokenSpaceGuid.PcdHypFdBaseAddress|0|UINT32|0x0000003A\r |
| 172 | gArmTokenSpaceGuid.PcdHypFdSize|0|UINT32|0x0000003B\r | |
| 173 | gArmTokenSpaceGuid.PcdHypFvBaseAddress|0|UINT32|0x0000003C\r | |
| 174 | gArmTokenSpaceGuid.PcdHypFvSize|0|UINT32|0x0000003D\r | |
| d6dc67ba | 175 | \r |
| 0787bc61 | 176 | # Use ClusterId + CoreId to identify the PrimaryCore\r |
| 177 | gArmTokenSpaceGuid.PcdArmPrimaryCoreMask|0xF03|UINT32|0x00000031\r | |
| c32aaba9 | 178 | # The Primary Core is ClusterId[0] & CoreId[0]\r |
| 0787bc61 | 179 | gArmTokenSpaceGuid.PcdArmPrimaryCore|0|UINT32|0x00000037\r |
| 180 | \r | |
| 660d4faa RC |
181 | #\r |
| 182 | # SMBIOS PCDs\r | |
| 183 | #\r | |
| 184 | gArmTokenSpaceGuid.PcdSystemProductName|L""|VOID*|0x30000053\r | |
| 185 | gArmTokenSpaceGuid.PcdSystemVersion|L""|VOID*|0x30000054\r | |
| 186 | gArmTokenSpaceGuid.PcdBaseBoardManufacturer|L""|VOID*|0x30000055\r | |
| 187 | gArmTokenSpaceGuid.PcdBaseBoardProductName|L""|VOID*|0x30000056\r | |
| 188 | gArmTokenSpaceGuid.PcdBaseBoardVersion|L""|VOID*|0x30000057\r | |
| 189 | gArmTokenSpaceGuid.PcdProcessorManufacturer|L""|VOID*|0x30000071\r | |
| 190 | gArmTokenSpaceGuid.PcdProcessorVersion|L""|VOID*|0x30000072\r | |
| 191 | gArmTokenSpaceGuid.PcdProcessorSerialNumber|L""|VOID*|0x30000073\r | |
| 192 | gArmTokenSpaceGuid.PcdProcessorAssetTag|L""|VOID*|0x30000074\r | |
| 193 | gArmTokenSpaceGuid.PcdProcessorPartNumber|L""|VOID*|0x30000075\r | |
| 194 | \r | |
| 1bfda055 | 195 | #\r |
| 196 | # ARM L2x0 PCDs\r | |
| 197 | #\r | |
| 198 | gArmTokenSpaceGuid.PcdL2x0ControllerBase|0|UINT32|0x0000001B\r | |
| c32aaba9 | 199 | \r |
| 523b5266 AB |
200 | #\r |
| 201 | # ARM Normal (or Non Secure) Firmware PCDs\r | |
| 202 | #\r | |
| 203 | gArmTokenSpaceGuid.PcdFdSize|0|UINT32|0x0000002C\r | |
| 204 | gArmTokenSpaceGuid.PcdFvSize|0|UINT32|0x0000002E\r | |
| 205 | \r | |
| bfe34275 AB |
206 | #\r |
| 207 | # Value to add to a host address to obtain a device address, using\r | |
| 208 | # unsigned 64-bit integer arithmetic on both ARM and AArch64. This\r | |
| 209 | # means we can rely on truncation on overflow to specify negative\r | |
| 210 | # offsets.\r | |
| 211 | #\r | |
| 212 | gArmTokenSpaceGuid.PcdArmDmaDeviceOffset|0x0|UINT64|0x0000044\r | |
| 213 | \r | |
| 523b5266 AB |
214 | [PcdsFixedAtBuild.common, PcdsPatchableInModule.common]\r |
| 215 | gArmTokenSpaceGuid.PcdFdBaseAddress|0|UINT64|0x0000002B\r | |
| 216 | gArmTokenSpaceGuid.PcdFvBaseAddress|0|UINT64|0x0000002D\r | |
| 387653a4 | 217 | \r |
| 218 | [PcdsFixedAtBuild.ARM]\r | |
| cc935544 OM |
219 | #\r |
| 220 | # ARM Security Extension\r | |
| 221 | #\r | |
| 222 | \r | |
| 223 | # Secure Configuration Register\r | |
| 224 | # - BIT0 : NS - Non Secure bit\r | |
| 225 | # - BIT1 : IRQ Handler\r | |
| 226 | # - BIT2 : FIQ Handler\r | |
| 227 | # - BIT3 : EA - External Abort\r | |
| 228 | # - BIT4 : FW - F bit writable\r | |
| 229 | # - BIT5 : AW - A bit writable\r | |
| 230 | # - BIT6 : nET - Not Early Termination\r | |
| 231 | # - BIT7 : SCD - Secure Monitor Call Disable\r | |
| 232 | # - BIT8 : HCE - Hyp Call enable\r | |
| 233 | # - BIT9 : SIF - Secure Instruction Fetch\r | |
| 234 | # 0x31 = NS | EA | FW\r | |
| 235 | gArmTokenSpaceGuid.PcdArmScr|0x31|UINT32|0x00000038\r | |
| 236 | \r | |
| 387653a4 | 237 | # By default we do not do a transition to non-secure mode\r |
| 238 | gArmTokenSpaceGuid.PcdArmNonSecModeTransition|0x0|UINT32|0x0000003E\r | |
| 2425e1d4 | 239 | \r |
| d6dc67ba OM |
240 | # Non Secure Access Control Register\r |
| 241 | # - BIT15 : NSASEDIS - Disable Non-secure Advanced SIMD functionality\r | |
| 242 | # - BIT14 : NSD32DIS - Disable Non-secure use of D16-D31\r | |
| 243 | # - BIT11 : cp11 - Non-secure access to coprocessor 11 enable\r | |
| 244 | # - BIT10 : cp10 - Non-secure access to coprocessor 10 enable\r | |
| 245 | # 0xC00 = cp10 | cp11\r | |
| 246 | gArmTokenSpaceGuid.PcdArmNsacr|0xC00|UINT32|0x00000039\r | |
| 247 | \r | |
| 25402f5d | 248 | [PcdsFixedAtBuild.AARCH64]\r |
| cc935544 OM |
249 | #\r |
| 250 | # AArch64 Security Extension\r | |
| 251 | #\r | |
| 252 | \r | |
| 253 | # Secure Configuration Register\r | |
| 254 | # - BIT0 : NS - Non Secure bit\r | |
| 255 | # - BIT1 : IRQ Handler\r | |
| 256 | # - BIT2 : FIQ Handler\r | |
| 257 | # - BIT3 : EA - External Abort\r | |
| 258 | # - BIT4 : FW - F bit writable\r | |
| 259 | # - BIT5 : AW - A bit writable\r | |
| 260 | # - BIT6 : nET - Not Early Termination\r | |
| 261 | # - BIT7 : SCD - Secure Monitor Call Disable\r | |
| 262 | # - BIT8 : HCE - Hyp Call enable\r | |
| 263 | # - BIT9 : SIF - Secure Instruction Fetch\r | |
| 264 | # - BIT10: RW - Register width control for lower exception levels\r | |
| 265 | # - BIT11: SIF - Enables Secure EL1 access to EL1 Architectural Timer\r | |
| 266 | # - BIT12: TWI - Trap WFI\r | |
| 267 | # - BIT13: TWE - Trap WFE\r | |
| 268 | # 0x501 = NS | HCE | RW\r | |
| 269 | gArmTokenSpaceGuid.PcdArmScr|0x501|UINT32|0x00000038\r | |
| 270 | \r | |
| 25402f5d HL |
271 | # By default we do transition to EL2 non-secure mode with Stack for EL2.\r |
| 272 | # Mode Description Bits\r | |
| c32aaba9 OM |
273 | # NS EL2 SP2 all interrupts disabled = 0x3c9\r |
| 274 | # NS EL1 SP1 all interrupts disabled = 0x3c5\r | |
| 25402f5d HL |
275 | # Other modes include using SP0 or switching to Aarch32, but these are\r |
| 276 | # not currently supported.\r | |
| 277 | gArmTokenSpaceGuid.PcdArmNonSecModeTransition|0x3c9|UINT32|0x0000003E\r | |
| e1e2e66c AB |
278 | \r |
| 279 | \r | |
| dc63be24 | 280 | #\r |
| 523b5266 AB |
281 | # These PCDs are also defined as 'PcdsDynamic' or 'PcdsPatchableInModule' to be\r |
| 282 | # redefined when using UEFI in a context of virtual machine.\r | |
| dc63be24 | 283 | #\r |
| 523b5266 AB |
284 | [PcdsFixedAtBuild.common, PcdsDynamic.common, PcdsPatchableInModule.common]\r |
| 285 | \r | |
| f8d7d6e1 | 286 | # System Memory (DRAM): These PCDs define the region of in-built system memory\r |
| 142fa386 AB |
287 | # Some platforms can get DRAM extensions, these additional regions may be\r |
| 288 | # declared to UEFI using separate resource descriptor HOBs\r | |
| f8d7d6e1 AB |
289 | gArmTokenSpaceGuid.PcdSystemMemoryBase|0|UINT64|0x00000029\r |
| 290 | gArmTokenSpaceGuid.PcdSystemMemorySize|0|UINT64|0x0000002A\r | |
| 291 | \r | |
| 767febf8 AG |
292 | gArmTokenSpaceGuid.PcdMmBufferBase|0|UINT64|0x00000045\r |
| 293 | gArmTokenSpaceGuid.PcdMmBufferSize|0|UINT64|0x00000046\r | |
| 294 | \r | |
| 660d4faa RC |
295 | gArmTokenSpaceGuid.PcdSystemBiosRelease|0xFFFF|UINT16|0x30000058\r |
| 296 | gArmTokenSpaceGuid.PcdEmbeddedControllerFirmwareRelease|0xFFFF|UINT16|0x30000059\r | |
| 297 | \r | |
| 523b5266 | 298 | [PcdsFixedAtBuild.common, PcdsDynamic.common]\r |
| e1e2e66c AB |
299 | #\r |
| 300 | # ARM Architectural Timer\r | |
| 301 | #\r | |
| 302 | gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz|0|UINT32|0x00000034\r | |
| 303 | \r | |
| 304 | # ARM Architectural Timer Interrupt(GIC PPI) numbers\r | |
| 305 | gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum|29|UINT32|0x00000035\r | |
| 306 | gArmTokenSpaceGuid.PcdArmArchTimerIntrNum|30|UINT32|0x00000036\r | |
| 307 | gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum|26|UINT32|0x00000040\r | |
| 308 | gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum|27|UINT32|0x00000041\r | |
| dc63be24 | 309 | \r |
| 0b4d97a0 RC |
310 | #\r |
| 311 | # ARM Generic Watchdog\r | |
| 312 | #\r | |
| 313 | \r | |
| 7c609a14 A |
314 | gArmTokenSpaceGuid.PcdGenericWatchdogControlBase|0x2A440000|UINT64|0x00000007\r |
| 315 | gArmTokenSpaceGuid.PcdGenericWatchdogRefreshBase|0x2A450000|UINT64|0x00000008\r | |
| 0b4d97a0 RC |
316 | gArmTokenSpaceGuid.PcdGenericWatchdogEl2IntrNum|93|UINT32|0x00000009\r |
| 317 | \r | |
| dc63be24 AB |
318 | #\r |
| 319 | # ARM Generic Interrupt Controller\r | |
| 320 | #\r | |
| 8a1f2378 | 321 | gArmTokenSpaceGuid.PcdGicDistributorBase|0|UINT64|0x0000000C\r |
| 919697ae | 322 | # Base address for the GIC Redistributor region that contains the boot CPU\r |
| 8a1f2378 DC |
323 | gArmTokenSpaceGuid.PcdGicRedistributorsBase|0|UINT64|0x0000000E\r |
| 324 | gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0|UINT64|0x0000000D\r | |
| dc63be24 | 325 | gArmTokenSpaceGuid.PcdGicSgiIntId|0|UINT32|0x00000025\r |
| d7c06eb0 AB |
326 | \r |
| 327 | #\r | |
| 328 | # Bases, sizes and translation offsets of IO and MMIO spaces, respectively.\r | |
| 329 | # Note that "IO" is just another MMIO range that simulates IO space; there\r | |
| 330 | # are no special instructions to access it.\r | |
| 331 | #\r | |
| 332 | # The base addresses PcdPciIoBase, PcdPciMmio32Base and PcdPciMmio64Base are\r | |
| 333 | # specific to their containing address spaces. In order to get the physical\r | |
| 334 | # address for the CPU, for a given access, the respective translation value\r | |
| 335 | # has to be added.\r | |
| 336 | #\r | |
| 337 | # The translations always have to be initialized like this, using UINT64:\r | |
| 338 | #\r | |
| 339 | # UINT64 IoCpuBase; // mapping target in 64-bit cpu-physical space\r | |
| 340 | # UINT64 Mmio32CpuBase; // mapping target in 64-bit cpu-physical space\r | |
| 341 | # UINT64 Mmio64CpuBase; // mapping target in 64-bit cpu-physical space\r | |
| 342 | #\r | |
| 7d78a86e | 343 | # gEfiMdePkgTokenSpaceGuid.PcdPciIoTranslation = IoCpuBase - PcdPciIoBase;\r |
| 9a7509e4 AC |
344 | # gEfiMdePkgTokenSpaceGuid.PcdPciMmio32Translation = Mmio32CpuBase - (UINT64)PcdPciMmio32Base;\r |
| 345 | # gEfiMdePkgTokenSpaceGuid.PcdPciMmio64Translation = Mmio64CpuBase - PcdPciMmio64Base;\r | |
| d7c06eb0 AB |
346 | #\r |
| 347 | # because (a) the target address space (ie. the cpu-physical space) is\r | |
| 348 | # 64-bit, and (b) the translation values are meant as offsets for *modular*\r | |
| 349 | # arithmetic.\r | |
| 350 | #\r | |
| 351 | # Accordingly, the translation itself needs to be implemented as:\r | |
| 352 | #\r | |
| 353 | # UINT64 UntranslatedIoAddress; // input parameter\r | |
| 354 | # UINT32 UntranslatedMmio32Address; // input parameter\r | |
| 355 | # UINT64 UntranslatedMmio64Address; // input parameter\r | |
| 356 | #\r | |
| 357 | # UINT64 TranslatedIoAddress; // output parameter\r | |
| 358 | # UINT64 TranslatedMmio32Address; // output parameter\r | |
| 359 | # UINT64 TranslatedMmio64Address; // output parameter\r | |
| 360 | #\r | |
| 361 | # TranslatedIoAddress = UntranslatedIoAddress +\r | |
| 7d78a86e | 362 | # gEfiMdePkgTokenSpaceGuid.PcdPciIoTranslation;\r |
| d7c06eb0 | 363 | # TranslatedMmio32Address = (UINT64)UntranslatedMmio32Address +\r |
| 9a7509e4 | 364 | # gEfiMdePkgTokenSpaceGuid.PcdPciMmio32Translation;\r |
| d7c06eb0 | 365 | # TranslatedMmio64Address = UntranslatedMmio64Address +\r |
| 9a7509e4 | 366 | # gEfiMdePkgTokenSpaceGuid.PcdPciMmio64Translation;\r |
| d7c06eb0 AB |
367 | #\r |
| 368 | # The modular arithmetic performed in UINT64 ensures that the translation\r | |
| 369 | # works correctly regardless of the relation between IoCpuBase and\r | |
| 370 | # PcdPciIoBase, Mmio32CpuBase and PcdPciMmio32Base, and Mmio64CpuBase and\r | |
| 371 | # PcdPciMmio64Base.\r | |
| 372 | #\r | |
| 373 | gArmTokenSpaceGuid.PcdPciIoBase|0x0|UINT64|0x00000050\r | |
| 374 | gArmTokenSpaceGuid.PcdPciIoSize|0x0|UINT64|0x00000051\r | |
| d7c06eb0 AB |
375 | gArmTokenSpaceGuid.PcdPciMmio32Base|0x0|UINT32|0x00000053\r |
| 376 | gArmTokenSpaceGuid.PcdPciMmio32Size|0x0|UINT32|0x00000054\r | |
| d7c06eb0 AB |
377 | gArmTokenSpaceGuid.PcdPciMmio64Base|0x0|UINT64|0x00000056\r |
| 378 | gArmTokenSpaceGuid.PcdPciMmio64Size|0x0|UINT64|0x00000057\r | |
| d7c06eb0 AB |
379 | \r |
| 380 | #\r | |
| 381 | # Inclusive range of allowed PCI buses.\r | |
| 382 | #\r | |
| 383 | gArmTokenSpaceGuid.PcdPciBusMin|0x0|UINT32|0x00000059\r | |
| 384 | gArmTokenSpaceGuid.PcdPciBusMax|0x0|UINT32|0x0000005A\r | |
| 62540372 NP |
385 | \r |
| 386 | [PcdsDynamicEx]\r | |
| 387 | #\r | |
| 388 | # This dynamic PCD hold the GUID of a firmware FFS which contains\r | |
| 389 | # the LinuxBoot payload.\r | |
| 390 | #\r | |
| 391 | gArmTokenSpaceGuid.PcdLinuxBootFileGuid|{0x0}|VOID*|0x0000005C\r |