projects / mirror_edk2.git / blame
| Commit | Line | Data |
|---|---|---|
| 8bbf0f09 A |
1 | #/** @file\r |
| 2 | # ARM processor package.\r | |
| 3 | #\r | |
| d6ebcab7 | 4 | # Copyright (c) 2009 - 2010, Apple Inc. All rights reserved.<BR>\r |
| d03f71dd | 5 | # Copyright (c) 2011 - 2021, ARM Limited. All rights reserved.\r |
| 8bbf0f09 | 6 | #\r |
| 4059386c | 7 | # SPDX-License-Identifier: BSD-2-Clause-Patent\r |
| 8bbf0f09 A |
8 | #\r |
| 9 | #**/\r | |
| 10 | \r | |
| 2ef2b01e A |
11 | [Defines]\r |
| 12 | DEC_SPECIFICATION = 0x00010005\r | |
| 13 | PACKAGE_NAME = ArmPkg\r | |
| 14 | PACKAGE_GUID = 5CFBD99E-3C43-4E7F-8054-9CDEAFF7710F\r | |
| 15 | PACKAGE_VERSION = 0.1\r | |
| 16 | \r | |
| 17 | ################################################################################\r | |
| 18 | #\r | |
| 19 | # Include Section - list of Include Paths that are provided by this package.\r | |
| 20 | # Comments are used for Keywords and Module Types.\r | |
| 21 | #\r | |
| 22 | # Supported Module Types:\r | |
| 23 | # BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION\r | |
| 24 | #\r | |
| 25 | ################################################################################\r | |
| 26 | [Includes.common]\r | |
| 27 | Include # Root include for the package\r | |
| 28 | \r | |
| 29 | [LibraryClasses.common]\r | |
| a145d5f2 | 30 | ## @libraryclass Convert Arm instructions to a human readable format.\r |
| 3093c95d | 31 | #\r |
| a145d5f2 | 32 | ArmDisassemblerLib|Include/Library/ArmDisassemblerLib.h\r |
| 3093c95d | 33 | \r |
| a145d5f2 | 34 | ## @libraryclass Provides an interface to Arm generic counters.\r |
| 3093c95d | 35 | #\r |
| a145d5f2 | 36 | ArmGenericTimerCounterLib|Include/Library/ArmGenericTimerCounterLib.h\r |
| 3093c95d | 37 | \r |
| a145d5f2 PG |
38 | ## @libraryclass Provides an interface to initialize a\r |
| 39 | # Generic Interrupt Controller (GIC).\r | |
| 3093c95d | 40 | #\r |
| a145d5f2 | 41 | ArmGicArchLib|Include/Library/ArmGicArchLib.h\r |
| 3093c95d | 42 | \r |
| a145d5f2 PG |
43 | ## @libraryclass Provides a Generic Interrupt Controller (GIC)\r |
| 44 | # configuration interface.\r | |
| 3093c95d | 45 | #\r |
| a145d5f2 | 46 | ArmGicLib|Include/Library/ArmGicLib.h\r |
| 3093c95d | 47 | \r |
| a145d5f2 | 48 | ## @libraryclass Provides a HyperVisor Call (HVC) interface.\r |
| 3093c95d | 49 | #\r |
| a145d5f2 | 50 | ArmHvcLib|Include/Library/ArmHvcLib.h\r |
| 3093c95d | 51 | \r |
| a145d5f2 | 52 | ## @libraryclass Provides an interface to Arm registers.\r |
| 3093c95d | 53 | #\r |
| a145d5f2 PG |
54 | ArmLib|Include/Library/ArmLib.h\r |
| 55 | \r | |
| 56 | ## @libraryclass Provides a Mmu interface.\r | |
| 57 | #\r | |
| 58 | ArmMmuLib|Include/Library/ArmMmuLib.h\r | |
| 3093c95d PG |
59 | \r |
| 60 | ## @libraryclass Provides a Mailbox Transport Layer (MTL) interface\r | |
| 61 | # for the System Control and Management Interface (SCMI).\r | |
| 62 | #\r | |
| d03f71dd | 63 | ArmMtlLib|Include/Library/ArmMtlLib.h\r |
| 3093c95d | 64 | \r |
| a145d5f2 | 65 | ## @libraryclass Provides a System Monitor Call (SMC) interface.\r |
| 3093c95d | 66 | #\r |
| a145d5f2 | 67 | ArmSmcLib|Include/Library/ArmSmcLib.h\r |
| 3093c95d | 68 | \r |
| a145d5f2 | 69 | ## @libraryclass Provides a SuperVisor Call (SVC) interface.\r |
| 3093c95d | 70 | #\r |
| a145d5f2 | 71 | ArmSvcLib|Include/Library/ArmSvcLib.h\r |
| 3093c95d | 72 | \r |
| a145d5f2 | 73 | ## @libraryclass Provides a default exception handler.\r |
| 3093c95d | 74 | #\r |
| a145d5f2 | 75 | DefaultExceptionHandlerLib|Include/Library/DefaultExceptionHandlerLib.h\r |
| 3093c95d PG |
76 | \r |
| 77 | ## @libraryclass Provides an interface to query miscellaneous OEM\r | |
| 78 | # information.\r | |
| 79 | #\r | |
| d03f71dd | 80 | OemMiscLib|Include/Library/OemMiscLib.h\r |
| 3093c95d | 81 | \r |
| a145d5f2 | 82 | ## @libraryclass Provides an OpTee interface.\r |
| 3093c95d | 83 | #\r |
| a145d5f2 PG |
84 | OpteeLib|Include/Library/OpteeLib.h\r |
| 85 | \r | |
| 86 | ## @libraryclass Provides a semihosting interface.\r | |
| 87 | #\r | |
| 88 | SemihostLib|Include/Library/SemihostLib.h\r | |
| d03f71dd | 89 | \r |
| a145d5f2 PG |
90 | ## @libraryclass Provides an interface for a StandaloneMm Mmu.\r |
| 91 | #\r | |
| 92 | StandaloneMmMmuLib|Include/Library/StandaloneMmMmuLib.h\r | |
| c32aaba9 | 93 | \r |
| 2ef2b01e A |
94 | [Guids.common]\r |
| 95 | gArmTokenSpaceGuid = { 0xBB11ECFE, 0x820F, 0x4968, { 0xBB, 0xA6, 0xF7, 0x6A, 0xFE, 0x30, 0x25, 0x96 } }\r | |
| 96 | \r | |
| 44788bae | 97 | ## ARM MPCore table\r |
| 98 | # Include/Guid/ArmMpCoreInfo.h\r | |
| 99 | gArmMpCoreInfoGuid = { 0xa4ee0728, 0xe5d7, 0x4ac5, {0xb2, 0x1e, 0x65, 0x8e, 0xd8, 0x57, 0xe8, 0x34} }\r | |
| 100 | \r | |
| 4f2494cf GP |
101 | [Protocols.common]\r |
| 102 | ## Arm System Control and Management Interface(SCMI) Base protocol\r | |
| 103 | ## ArmPkg/Include/Protocol/ArmScmiBaseProtocol.h\r | |
| 104 | gArmScmiBaseProtocolGuid = { 0xd7e5abe9, 0x33ab, 0x418e, { 0x9f, 0x91, 0x72, 0xda, 0xe2, 0xba, 0x8e, 0x2f } }\r | |
| 105 | \r | |
| 106 | ## Arm System Control and Management Interface(SCMI) Clock management protocol\r | |
| 107 | ## ArmPkg/Include/Protocol/ArmScmiClockProtocol.h\r | |
| 108 | gArmScmiClockProtocolGuid = { 0x91ce67a8, 0xe0aa, 0x4012, { 0xb9, 0x9f, 0xb6, 0xfc, 0xf3, 0x4, 0x8e, 0xaa } }\r | |
| 559a07d8 | 109 | gArmScmiClock2ProtocolGuid = { 0xb8d8caf2, 0x9e94, 0x462c, { 0xa8, 0x34, 0x6c, 0x99, 0xfc, 0x05, 0xef, 0xcf } }\r |
| 4f2494cf GP |
110 | \r |
| 111 | ## Arm System Control and Management Interface(SCMI) Clock management protocol\r | |
| 112 | ## ArmPkg/Include/Protocol/ArmScmiPerformanceProtocol.h\r | |
| 113 | gArmScmiPerformanceProtocolGuid = { 0x9b8ba84, 0x3dd3, 0x49a6, { 0xa0, 0x5a, 0x31, 0x34, 0xa5, 0xf0, 0x7b, 0xad } }\r | |
| 114 | \r | |
| 44788bae | 115 | [Ppis]\r |
| 116 | ## Include/Ppi/ArmMpCoreInfo.h\r | |
| 117 | gArmMpCoreInfoPpiGuid = { 0x6847cc74, 0xe9ec, 0x4f8f, {0xa2, 0x9d, 0xab, 0x44, 0xe7, 0x54, 0xa8, 0xfc} }\r | |
| 118 | \r | |
| 2ef2b01e A |
119 | [PcdsFeatureFlag.common]\r |
| 120 | gArmTokenSpaceGuid.PcdCpuDxeProduceDebugSupport|FALSE|BOOLEAN|0x00000001\r | |
| 121 | \r | |
| 1bfda055 | 122 | # On ARM Architecture with the Security Extension, the address for the\r |
| 123 | # Vector Table can be mapped anywhere in the memory map. It means we can\r | |
| 124 | # point the Exception Vector Table to its location in CpuDxe.\r | |
| f0bbcdf8 | 125 | # By default we copy the Vector Table at PcdGet64(PcdCpuVectorBaseAddress)\r |
| 1bfda055 | 126 | gArmTokenSpaceGuid.PcdRelocateVectorTable|TRUE|BOOLEAN|0x00000022\r |
| eeec69c5 | 127 | # Set this PCD to TRUE if the Exception Vector is changed to add debugger support before\r |
| 128 | # it has been configured by the CPU DXE\r | |
| 129 | gArmTokenSpaceGuid.PcdDebuggerExceptionSupport|FALSE|BOOLEAN|0x00000032\r | |
| c32aaba9 | 130 | \r |
| f6d46e29 AB |
131 | # Define if the GICv3 controller should use the GICv2 legacy\r |
| 132 | gArmTokenSpaceGuid.PcdArmGicV3WithV2Legacy|FALSE|BOOLEAN|0x00000042\r | |
| 133 | \r | |
| 65ceda91 AB |
134 | [PcdsFeatureFlag.ARM]\r |
| 135 | # Whether to map normal memory as non-shareable. FALSE is the safe choice, but\r | |
| 136 | # TRUE may be appropriate to fix performance problems if you don't care about\r | |
| 137 | # hardware coherency (i.e., no virtualization or cache coherent DMA)\r | |
| 138 | gArmTokenSpaceGuid.PcdNormalMemoryNonshareableOverride|FALSE|BOOLEAN|0x00000043\r | |
| 139 | \r | |
| aee0098f | 140 | [PcdsFeatureFlag.AARCH64, PcdsFeatureFlag.ARM]\r |
| ee283e33 SG |
141 | ## Used to select method for requesting services from S-EL1.<BR><BR>\r |
| 142 | # TRUE - Selects FF-A calls for communication between S-EL0 and SPMC.<BR>\r | |
| 143 | # FALSE - Selects SVC calls for communication between S-EL0 and SPMC.<BR>\r | |
| 144 | # @Prompt Enable FF-A support.\r | |
| 145 | gArmTokenSpaceGuid.PcdFfaEnable|FALSE|BOOLEAN|0x0000005B\r | |
| 146 | \r | |
| 2ef2b01e | 147 | [PcdsFixedAtBuild.common]\r |
| 12c5ae23 | 148 | gArmTokenSpaceGuid.PcdTrustzoneSupport|FALSE|BOOLEAN|0x00000006\r |
| 149 | \r | |
| 1bfda055 | 150 | # This PCD should be a FeaturePcd. But we used this PCD as an '#if' in an ASM file.\r |
| 151 | # Using a FeaturePcd make a '(BOOLEAN) casting for its value which is not understood by the preprocessor.\r | |
| 152 | gArmTokenSpaceGuid.PcdVFPEnabled|0|UINT32|0x00000024\r | |
| 153 | \r | |
| f0bbcdf8 | 154 | gArmTokenSpaceGuid.PcdCpuVectorBaseAddress|0xffff0000|UINT64|0x00000004\r |
| 2ef2b01e | 155 | gArmTokenSpaceGuid.PcdCpuResetAddress|0x00000000|UINT32|0x00000005\r |
| c32aaba9 | 156 | \r |
| 1bfda055 | 157 | #\r |
| 262a9b04 | 158 | # ARM Secure Firmware PCDs\r |
| 1bfda055 | 159 | #\r |
| bb5420bb | 160 | gArmTokenSpaceGuid.PcdSecureFdBaseAddress|0|UINT64|0x00000015\r |
| 1bfda055 | 161 | gArmTokenSpaceGuid.PcdSecureFdSize|0|UINT32|0x00000016\r |
| bb5420bb | 162 | gArmTokenSpaceGuid.PcdSecureFvBaseAddress|0x0|UINT64|0x0000002F\r |
| 1ad14bc8 | 163 | gArmTokenSpaceGuid.PcdSecureFvSize|0x0|UINT32|0x00000030\r |
| 1bfda055 | 164 | \r |
| 7245b435 | 165 | #\r |
| 166 | # ARM Hypervisor Firmware PCDs\r | |
| c32aaba9 | 167 | #\r |
| 7245b435 | 168 | gArmTokenSpaceGuid.PcdHypFdBaseAddress|0|UINT32|0x0000003A\r |
| 169 | gArmTokenSpaceGuid.PcdHypFdSize|0|UINT32|0x0000003B\r | |
| 170 | gArmTokenSpaceGuid.PcdHypFvBaseAddress|0|UINT32|0x0000003C\r | |
| 171 | gArmTokenSpaceGuid.PcdHypFvSize|0|UINT32|0x0000003D\r | |
| d6dc67ba | 172 | \r |
| 0787bc61 | 173 | # Use ClusterId + CoreId to identify the PrimaryCore\r |
| 174 | gArmTokenSpaceGuid.PcdArmPrimaryCoreMask|0xF03|UINT32|0x00000031\r | |
| c32aaba9 | 175 | # The Primary Core is ClusterId[0] & CoreId[0]\r |
| 0787bc61 | 176 | gArmTokenSpaceGuid.PcdArmPrimaryCore|0|UINT32|0x00000037\r |
| 177 | \r | |
| 660d4faa RC |
178 | #\r |
| 179 | # SMBIOS PCDs\r | |
| 180 | #\r | |
| 181 | gArmTokenSpaceGuid.PcdSystemProductName|L""|VOID*|0x30000053\r | |
| 182 | gArmTokenSpaceGuid.PcdSystemVersion|L""|VOID*|0x30000054\r | |
| 183 | gArmTokenSpaceGuid.PcdBaseBoardManufacturer|L""|VOID*|0x30000055\r | |
| 184 | gArmTokenSpaceGuid.PcdBaseBoardProductName|L""|VOID*|0x30000056\r | |
| 185 | gArmTokenSpaceGuid.PcdBaseBoardVersion|L""|VOID*|0x30000057\r | |
| 186 | gArmTokenSpaceGuid.PcdProcessorManufacturer|L""|VOID*|0x30000071\r | |
| 187 | gArmTokenSpaceGuid.PcdProcessorVersion|L""|VOID*|0x30000072\r | |
| 188 | gArmTokenSpaceGuid.PcdProcessorSerialNumber|L""|VOID*|0x30000073\r | |
| 189 | gArmTokenSpaceGuid.PcdProcessorAssetTag|L""|VOID*|0x30000074\r | |
| 190 | gArmTokenSpaceGuid.PcdProcessorPartNumber|L""|VOID*|0x30000075\r | |
| 191 | \r | |
| 1bfda055 | 192 | #\r |
| 193 | # ARM L2x0 PCDs\r | |
| 194 | #\r | |
| 195 | gArmTokenSpaceGuid.PcdL2x0ControllerBase|0|UINT32|0x0000001B\r | |
| c32aaba9 | 196 | \r |
| 523b5266 AB |
197 | #\r |
| 198 | # ARM Normal (or Non Secure) Firmware PCDs\r | |
| 199 | #\r | |
| 200 | gArmTokenSpaceGuid.PcdFdSize|0|UINT32|0x0000002C\r | |
| 201 | gArmTokenSpaceGuid.PcdFvSize|0|UINT32|0x0000002E\r | |
| 202 | \r | |
| bfe34275 AB |
203 | #\r |
| 204 | # Value to add to a host address to obtain a device address, using\r | |
| 205 | # unsigned 64-bit integer arithmetic on both ARM and AArch64. This\r | |
| 206 | # means we can rely on truncation on overflow to specify negative\r | |
| 207 | # offsets.\r | |
| 208 | #\r | |
| 209 | gArmTokenSpaceGuid.PcdArmDmaDeviceOffset|0x0|UINT64|0x0000044\r | |
| 210 | \r | |
| 523b5266 AB |
211 | [PcdsFixedAtBuild.common, PcdsPatchableInModule.common]\r |
| 212 | gArmTokenSpaceGuid.PcdFdBaseAddress|0|UINT64|0x0000002B\r | |
| 213 | gArmTokenSpaceGuid.PcdFvBaseAddress|0|UINT64|0x0000002D\r | |
| 387653a4 | 214 | \r |
| 215 | [PcdsFixedAtBuild.ARM]\r | |
| cc935544 OM |
216 | #\r |
| 217 | # ARM Security Extension\r | |
| 218 | #\r | |
| 219 | \r | |
| 220 | # Secure Configuration Register\r | |
| 221 | # - BIT0 : NS - Non Secure bit\r | |
| 222 | # - BIT1 : IRQ Handler\r | |
| 223 | # - BIT2 : FIQ Handler\r | |
| 224 | # - BIT3 : EA - External Abort\r | |
| 225 | # - BIT4 : FW - F bit writable\r | |
| 226 | # - BIT5 : AW - A bit writable\r | |
| 227 | # - BIT6 : nET - Not Early Termination\r | |
| 228 | # - BIT7 : SCD - Secure Monitor Call Disable\r | |
| 229 | # - BIT8 : HCE - Hyp Call enable\r | |
| 230 | # - BIT9 : SIF - Secure Instruction Fetch\r | |
| 231 | # 0x31 = NS | EA | FW\r | |
| 232 | gArmTokenSpaceGuid.PcdArmScr|0x31|UINT32|0x00000038\r | |
| 233 | \r | |
| 387653a4 | 234 | # By default we do not do a transition to non-secure mode\r |
| 235 | gArmTokenSpaceGuid.PcdArmNonSecModeTransition|0x0|UINT32|0x0000003E\r | |
| 2425e1d4 | 236 | \r |
| d6dc67ba OM |
237 | # Non Secure Access Control Register\r |
| 238 | # - BIT15 : NSASEDIS - Disable Non-secure Advanced SIMD functionality\r | |
| 239 | # - BIT14 : NSD32DIS - Disable Non-secure use of D16-D31\r | |
| 240 | # - BIT11 : cp11 - Non-secure access to coprocessor 11 enable\r | |
| 241 | # - BIT10 : cp10 - Non-secure access to coprocessor 10 enable\r | |
| 242 | # 0xC00 = cp10 | cp11\r | |
| 243 | gArmTokenSpaceGuid.PcdArmNsacr|0xC00|UINT32|0x00000039\r | |
| 244 | \r | |
| 25402f5d | 245 | [PcdsFixedAtBuild.AARCH64]\r |
| cc935544 OM |
246 | #\r |
| 247 | # AArch64 Security Extension\r | |
| 248 | #\r | |
| 249 | \r | |
| 250 | # Secure Configuration Register\r | |
| 251 | # - BIT0 : NS - Non Secure bit\r | |
| 252 | # - BIT1 : IRQ Handler\r | |
| 253 | # - BIT2 : FIQ Handler\r | |
| 254 | # - BIT3 : EA - External Abort\r | |
| 255 | # - BIT4 : FW - F bit writable\r | |
| 256 | # - BIT5 : AW - A bit writable\r | |
| 257 | # - BIT6 : nET - Not Early Termination\r | |
| 258 | # - BIT7 : SCD - Secure Monitor Call Disable\r | |
| 259 | # - BIT8 : HCE - Hyp Call enable\r | |
| 260 | # - BIT9 : SIF - Secure Instruction Fetch\r | |
| 261 | # - BIT10: RW - Register width control for lower exception levels\r | |
| 262 | # - BIT11: SIF - Enables Secure EL1 access to EL1 Architectural Timer\r | |
| 263 | # - BIT12: TWI - Trap WFI\r | |
| 264 | # - BIT13: TWE - Trap WFE\r | |
| 265 | # 0x501 = NS | HCE | RW\r | |
| 266 | gArmTokenSpaceGuid.PcdArmScr|0x501|UINT32|0x00000038\r | |
| 267 | \r | |
| 25402f5d HL |
268 | # By default we do transition to EL2 non-secure mode with Stack for EL2.\r |
| 269 | # Mode Description Bits\r | |
| c32aaba9 OM |
270 | # NS EL2 SP2 all interrupts disabled = 0x3c9\r |
| 271 | # NS EL1 SP1 all interrupts disabled = 0x3c5\r | |
| 25402f5d HL |
272 | # Other modes include using SP0 or switching to Aarch32, but these are\r |
| 273 | # not currently supported.\r | |
| 274 | gArmTokenSpaceGuid.PcdArmNonSecModeTransition|0x3c9|UINT32|0x0000003E\r | |
| e1e2e66c AB |
275 | \r |
| 276 | \r | |
| dc63be24 | 277 | #\r |
| 523b5266 AB |
278 | # These PCDs are also defined as 'PcdsDynamic' or 'PcdsPatchableInModule' to be\r |
| 279 | # redefined when using UEFI in a context of virtual machine.\r | |
| dc63be24 | 280 | #\r |
| 523b5266 AB |
281 | [PcdsFixedAtBuild.common, PcdsDynamic.common, PcdsPatchableInModule.common]\r |
| 282 | \r | |
| f8d7d6e1 | 283 | # System Memory (DRAM): These PCDs define the region of in-built system memory\r |
| 142fa386 AB |
284 | # Some platforms can get DRAM extensions, these additional regions may be\r |
| 285 | # declared to UEFI using separate resource descriptor HOBs\r | |
| f8d7d6e1 AB |
286 | gArmTokenSpaceGuid.PcdSystemMemoryBase|0|UINT64|0x00000029\r |
| 287 | gArmTokenSpaceGuid.PcdSystemMemorySize|0|UINT64|0x0000002A\r | |
| 288 | \r | |
| 767febf8 AG |
289 | gArmTokenSpaceGuid.PcdMmBufferBase|0|UINT64|0x00000045\r |
| 290 | gArmTokenSpaceGuid.PcdMmBufferSize|0|UINT64|0x00000046\r | |
| 291 | \r | |
| 660d4faa RC |
292 | gArmTokenSpaceGuid.PcdSystemBiosRelease|0xFFFF|UINT16|0x30000058\r |
| 293 | gArmTokenSpaceGuid.PcdEmbeddedControllerFirmwareRelease|0xFFFF|UINT16|0x30000059\r | |
| 294 | \r | |
| 523b5266 | 295 | [PcdsFixedAtBuild.common, PcdsDynamic.common]\r |
| e1e2e66c AB |
296 | #\r |
| 297 | # ARM Architectural Timer\r | |
| 298 | #\r | |
| 299 | gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz|0|UINT32|0x00000034\r | |
| 300 | \r | |
| 301 | # ARM Architectural Timer Interrupt(GIC PPI) numbers\r | |
| 302 | gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum|29|UINT32|0x00000035\r | |
| 303 | gArmTokenSpaceGuid.PcdArmArchTimerIntrNum|30|UINT32|0x00000036\r | |
| 304 | gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum|26|UINT32|0x00000040\r | |
| 305 | gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum|27|UINT32|0x00000041\r | |
| dc63be24 | 306 | \r |
| 0b4d97a0 RC |
307 | #\r |
| 308 | # ARM Generic Watchdog\r | |
| 309 | #\r | |
| 310 | \r | |
| 7c609a14 A |
311 | gArmTokenSpaceGuid.PcdGenericWatchdogControlBase|0x2A440000|UINT64|0x00000007\r |
| 312 | gArmTokenSpaceGuid.PcdGenericWatchdogRefreshBase|0x2A450000|UINT64|0x00000008\r | |
| 0b4d97a0 RC |
313 | gArmTokenSpaceGuid.PcdGenericWatchdogEl2IntrNum|93|UINT32|0x00000009\r |
| 314 | \r | |
| dc63be24 AB |
315 | #\r |
| 316 | # ARM Generic Interrupt Controller\r | |
| 317 | #\r | |
| 8a1f2378 | 318 | gArmTokenSpaceGuid.PcdGicDistributorBase|0|UINT64|0x0000000C\r |
| 919697ae | 319 | # Base address for the GIC Redistributor region that contains the boot CPU\r |
| 8a1f2378 DC |
320 | gArmTokenSpaceGuid.PcdGicRedistributorsBase|0|UINT64|0x0000000E\r |
| 321 | gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0|UINT64|0x0000000D\r | |
| dc63be24 | 322 | gArmTokenSpaceGuid.PcdGicSgiIntId|0|UINT32|0x00000025\r |
| d7c06eb0 AB |
323 | \r |
| 324 | #\r | |
| 325 | # Bases, sizes and translation offsets of IO and MMIO spaces, respectively.\r | |
| 326 | # Note that "IO" is just another MMIO range that simulates IO space; there\r | |
| 327 | # are no special instructions to access it.\r | |
| 328 | #\r | |
| 329 | # The base addresses PcdPciIoBase, PcdPciMmio32Base and PcdPciMmio64Base are\r | |
| 330 | # specific to their containing address spaces. In order to get the physical\r | |
| 331 | # address for the CPU, for a given access, the respective translation value\r | |
| 332 | # has to be added.\r | |
| 333 | #\r | |
| 334 | # The translations always have to be initialized like this, using UINT64:\r | |
| 335 | #\r | |
| 336 | # UINT64 IoCpuBase; // mapping target in 64-bit cpu-physical space\r | |
| 337 | # UINT64 Mmio32CpuBase; // mapping target in 64-bit cpu-physical space\r | |
| 338 | # UINT64 Mmio64CpuBase; // mapping target in 64-bit cpu-physical space\r | |
| 339 | #\r | |
| 7d78a86e | 340 | # gEfiMdePkgTokenSpaceGuid.PcdPciIoTranslation = IoCpuBase - PcdPciIoBase;\r |
| 9a7509e4 AC |
341 | # gEfiMdePkgTokenSpaceGuid.PcdPciMmio32Translation = Mmio32CpuBase - (UINT64)PcdPciMmio32Base;\r |
| 342 | # gEfiMdePkgTokenSpaceGuid.PcdPciMmio64Translation = Mmio64CpuBase - PcdPciMmio64Base;\r | |
| d7c06eb0 AB |
343 | #\r |
| 344 | # because (a) the target address space (ie. the cpu-physical space) is\r | |
| 345 | # 64-bit, and (b) the translation values are meant as offsets for *modular*\r | |
| 346 | # arithmetic.\r | |
| 347 | #\r | |
| 348 | # Accordingly, the translation itself needs to be implemented as:\r | |
| 349 | #\r | |
| 350 | # UINT64 UntranslatedIoAddress; // input parameter\r | |
| 351 | # UINT32 UntranslatedMmio32Address; // input parameter\r | |
| 352 | # UINT64 UntranslatedMmio64Address; // input parameter\r | |
| 353 | #\r | |
| 354 | # UINT64 TranslatedIoAddress; // output parameter\r | |
| 355 | # UINT64 TranslatedMmio32Address; // output parameter\r | |
| 356 | # UINT64 TranslatedMmio64Address; // output parameter\r | |
| 357 | #\r | |
| 358 | # TranslatedIoAddress = UntranslatedIoAddress +\r | |
| 7d78a86e | 359 | # gEfiMdePkgTokenSpaceGuid.PcdPciIoTranslation;\r |
| d7c06eb0 | 360 | # TranslatedMmio32Address = (UINT64)UntranslatedMmio32Address +\r |
| 9a7509e4 | 361 | # gEfiMdePkgTokenSpaceGuid.PcdPciMmio32Translation;\r |
| d7c06eb0 | 362 | # TranslatedMmio64Address = UntranslatedMmio64Address +\r |
| 9a7509e4 | 363 | # gEfiMdePkgTokenSpaceGuid.PcdPciMmio64Translation;\r |
| d7c06eb0 AB |
364 | #\r |
| 365 | # The modular arithmetic performed in UINT64 ensures that the translation\r | |
| 366 | # works correctly regardless of the relation between IoCpuBase and\r | |
| 367 | # PcdPciIoBase, Mmio32CpuBase and PcdPciMmio32Base, and Mmio64CpuBase and\r | |
| 368 | # PcdPciMmio64Base.\r | |
| 369 | #\r | |
| 370 | gArmTokenSpaceGuid.PcdPciIoBase|0x0|UINT64|0x00000050\r | |
| 371 | gArmTokenSpaceGuid.PcdPciIoSize|0x0|UINT64|0x00000051\r | |
| d7c06eb0 AB |
372 | gArmTokenSpaceGuid.PcdPciMmio32Base|0x0|UINT32|0x00000053\r |
| 373 | gArmTokenSpaceGuid.PcdPciMmio32Size|0x0|UINT32|0x00000054\r | |
| d7c06eb0 AB |
374 | gArmTokenSpaceGuid.PcdPciMmio64Base|0x0|UINT64|0x00000056\r |
| 375 | gArmTokenSpaceGuid.PcdPciMmio64Size|0x0|UINT64|0x00000057\r | |
| d7c06eb0 AB |
376 | \r |
| 377 | #\r | |
| 378 | # Inclusive range of allowed PCI buses.\r | |
| 379 | #\r | |
| 380 | gArmTokenSpaceGuid.PcdPciBusMin|0x0|UINT32|0x00000059\r | |
| 381 | gArmTokenSpaceGuid.PcdPciBusMax|0x0|UINT32|0x0000005A\r |