ArmPkg/ArmSmcPsciResetSystemLib: implement fallback for warm reboot
[mirror_edk2.git] / ArmPkg / ArmPkg.dec
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1#/** @file\r
2# ARM processor package.\r
3#\r
d6ebcab7 4# Copyright (c) 2009 - 2010, Apple Inc. All rights reserved.<BR>\r
38a00bae 5# Copyright (c) 2011 - 2018, ARM Limited. All rights reserved.\r
8bbf0f09 6#\r
d6ebcab7 7# This program and the accompanying materials\r
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8# are licensed and made available under the terms and conditions of the BSD License\r
9# which accompanies this distribution. The full text of the license may be found at\r
10# http://opensource.org/licenses/bsd-license.php\r
11#\r
12# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
13# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
14#\r
15#**/\r
16\r
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17[Defines]\r
18 DEC_SPECIFICATION = 0x00010005\r
19 PACKAGE_NAME = ArmPkg\r
20 PACKAGE_GUID = 5CFBD99E-3C43-4E7F-8054-9CDEAFF7710F\r
21 PACKAGE_VERSION = 0.1\r
22\r
23################################################################################\r
24#\r
25# Include Section - list of Include Paths that are provided by this package.\r
26# Comments are used for Keywords and Module Types.\r
27#\r
28# Supported Module Types:\r
29# BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION\r
30#\r
31################################################################################\r
32[Includes.common]\r
33 Include # Root include for the package\r
34\r
35[LibraryClasses.common]\r
8bbf0f09 36 ArmLib|Include/Library/ArmLib.h\r
12728e11 37 ArmMmuLib|Include/Library/ArmMmuLib.h\r
2ef2b01e 38 SemihostLib|Include/Library/Semihosting.h\r
11c20f4e 39 DefaultExceptionHandlerLib|Include/Library/DefaultExceptionHandlerLib.h\r
097bd461 40 ArmDisassemblerLib|Include/Library/ArmDisassemblerLib.h\r
8d13298b 41 ArmGicArchLib|Include/Library/ArmGicArchLib.h\r
38a00bae 42 ArmMtlLib|ArmPlatformPkg/Include/Library/ArmMtlLib.h\r
4d163696 43 ArmSvcLib|Include/Library/ArmSvcLib.h\r
c32aaba9 44\r
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45[Guids.common]\r
46 gArmTokenSpaceGuid = { 0xBB11ECFE, 0x820F, 0x4968, { 0xBB, 0xA6, 0xF7, 0x6A, 0xFE, 0x30, 0x25, 0x96 } }\r
47\r
44788bae 48 ## ARM MPCore table\r
49 # Include/Guid/ArmMpCoreInfo.h\r
50 gArmMpCoreInfoGuid = { 0xa4ee0728, 0xe5d7, 0x4ac5, {0xb2, 0x1e, 0x65, 0x8e, 0xd8, 0x57, 0xe8, 0x34} }\r
51\r
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52[Protocols.common]\r
53 ## Arm System Control and Management Interface(SCMI) Base protocol\r
54 ## ArmPkg/Include/Protocol/ArmScmiBaseProtocol.h\r
55 gArmScmiBaseProtocolGuid = { 0xd7e5abe9, 0x33ab, 0x418e, { 0x9f, 0x91, 0x72, 0xda, 0xe2, 0xba, 0x8e, 0x2f } }\r
56\r
57 ## Arm System Control and Management Interface(SCMI) Clock management protocol\r
58 ## ArmPkg/Include/Protocol/ArmScmiClockProtocol.h\r
59 gArmScmiClockProtocolGuid = { 0x91ce67a8, 0xe0aa, 0x4012, { 0xb9, 0x9f, 0xb6, 0xfc, 0xf3, 0x4, 0x8e, 0xaa } }\r
60\r
61 ## Arm System Control and Management Interface(SCMI) Clock management protocol\r
62 ## ArmPkg/Include/Protocol/ArmScmiPerformanceProtocol.h\r
63 gArmScmiPerformanceProtocolGuid = { 0x9b8ba84, 0x3dd3, 0x49a6, { 0xa0, 0x5a, 0x31, 0x34, 0xa5, 0xf0, 0x7b, 0xad } }\r
64\r
44788bae 65[Ppis]\r
66 ## Include/Ppi/ArmMpCoreInfo.h\r
67 gArmMpCoreInfoPpiGuid = { 0x6847cc74, 0xe9ec, 0x4f8f, {0xa2, 0x9d, 0xab, 0x44, 0xe7, 0x54, 0xa8, 0xfc} }\r
68\r
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69[PcdsFeatureFlag.common]\r
70 gArmTokenSpaceGuid.PcdCpuDxeProduceDebugSupport|FALSE|BOOLEAN|0x00000001\r
71\r
1bfda055 72 # On ARM Architecture with the Security Extension, the address for the\r
73 # Vector Table can be mapped anywhere in the memory map. It means we can\r
74 # point the Exception Vector Table to its location in CpuDxe.\r
f0bbcdf8 75 # By default we copy the Vector Table at PcdGet64(PcdCpuVectorBaseAddress)\r
1bfda055 76 gArmTokenSpaceGuid.PcdRelocateVectorTable|TRUE|BOOLEAN|0x00000022\r
eeec69c5 77 # Set this PCD to TRUE if the Exception Vector is changed to add debugger support before\r
78 # it has been configured by the CPU DXE\r
79 gArmTokenSpaceGuid.PcdDebuggerExceptionSupport|FALSE|BOOLEAN|0x00000032\r
c32aaba9 80\r
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81 # Define if the spin-table mechanism is used by the secondary cores when booting\r
82 # Linux (instead of PSCI)\r
83 gArmTokenSpaceGuid.PcdArmLinuxSpinTable|FALSE|BOOLEAN|0x00000033\r
c32aaba9 84\r
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85 # Define if the GICv3 controller should use the GICv2 legacy\r
86 gArmTokenSpaceGuid.PcdArmGicV3WithV2Legacy|FALSE|BOOLEAN|0x00000042\r
87\r
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88 # Whether to implement warm reboot for capsule update using a jump back to the\r
89 # PEI entry point with caches and interrupts disabled.\r
90 gArmTokenSpaceGuid.PcdArmReenterPeiForCapsuleWarmReboot|FALSE|BOOLEAN|0x0000001F\r
91\r
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92[PcdsFeatureFlag.ARM]\r
93 # Whether to map normal memory as non-shareable. FALSE is the safe choice, but\r
94 # TRUE may be appropriate to fix performance problems if you don't care about\r
95 # hardware coherency (i.e., no virtualization or cache coherent DMA)\r
96 gArmTokenSpaceGuid.PcdNormalMemoryNonshareableOverride|FALSE|BOOLEAN|0x00000043\r
97\r
2ef2b01e 98[PcdsFixedAtBuild.common]\r
12c5ae23 99 gArmTokenSpaceGuid.PcdTrustzoneSupport|FALSE|BOOLEAN|0x00000006\r
100\r
1bfda055 101 # This PCD should be a FeaturePcd. But we used this PCD as an '#if' in an ASM file.\r
102 # Using a FeaturePcd make a '(BOOLEAN) casting for its value which is not understood by the preprocessor.\r
103 gArmTokenSpaceGuid.PcdVFPEnabled|0|UINT32|0x00000024\r
104\r
f0bbcdf8 105 gArmTokenSpaceGuid.PcdCpuVectorBaseAddress|0xffff0000|UINT64|0x00000004\r
2ef2b01e 106 gArmTokenSpaceGuid.PcdCpuResetAddress|0x00000000|UINT32|0x00000005\r
c32aaba9 107\r
1bfda055 108 #\r
262a9b04 109 # ARM Secure Firmware PCDs\r
1bfda055 110 #\r
bb5420bb 111 gArmTokenSpaceGuid.PcdSecureFdBaseAddress|0|UINT64|0x00000015\r
1bfda055 112 gArmTokenSpaceGuid.PcdSecureFdSize|0|UINT32|0x00000016\r
bb5420bb 113 gArmTokenSpaceGuid.PcdSecureFvBaseAddress|0x0|UINT64|0x0000002F\r
1ad14bc8 114 gArmTokenSpaceGuid.PcdSecureFvSize|0x0|UINT32|0x00000030\r
1bfda055 115\r
7245b435 116 #\r
117 # ARM Hypervisor Firmware PCDs\r
c32aaba9 118 #\r
7245b435 119 gArmTokenSpaceGuid.PcdHypFdBaseAddress|0|UINT32|0x0000003A\r
120 gArmTokenSpaceGuid.PcdHypFdSize|0|UINT32|0x0000003B\r
121 gArmTokenSpaceGuid.PcdHypFvBaseAddress|0|UINT32|0x0000003C\r
122 gArmTokenSpaceGuid.PcdHypFvSize|0|UINT32|0x0000003D\r
d6dc67ba 123\r
0787bc61 124 # Use ClusterId + CoreId to identify the PrimaryCore\r
125 gArmTokenSpaceGuid.PcdArmPrimaryCoreMask|0xF03|UINT32|0x00000031\r
c32aaba9 126 # The Primary Core is ClusterId[0] & CoreId[0]\r
0787bc61 127 gArmTokenSpaceGuid.PcdArmPrimaryCore|0|UINT32|0x00000037\r
128\r
1bfda055 129 #\r
130 # ARM L2x0 PCDs\r
131 #\r
132 gArmTokenSpaceGuid.PcdL2x0ControllerBase|0|UINT32|0x0000001B\r
c32aaba9 133\r
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134 #\r
135 # ARM Normal (or Non Secure) Firmware PCDs\r
136 #\r
137 gArmTokenSpaceGuid.PcdFdSize|0|UINT32|0x0000002C\r
138 gArmTokenSpaceGuid.PcdFvSize|0|UINT32|0x0000002E\r
139\r
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140 #\r
141 # Value to add to a host address to obtain a device address, using\r
142 # unsigned 64-bit integer arithmetic on both ARM and AArch64. This\r
143 # means we can rely on truncation on overflow to specify negative\r
144 # offsets.\r
145 #\r
146 gArmTokenSpaceGuid.PcdArmDmaDeviceOffset|0x0|UINT64|0x0000044\r
147\r
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148[PcdsFixedAtBuild.common, PcdsPatchableInModule.common]\r
149 gArmTokenSpaceGuid.PcdFdBaseAddress|0|UINT64|0x0000002B\r
150 gArmTokenSpaceGuid.PcdFvBaseAddress|0|UINT64|0x0000002D\r
387653a4 151\r
152[PcdsFixedAtBuild.ARM]\r
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153 #\r
154 # ARM Security Extension\r
155 #\r
156\r
157 # Secure Configuration Register\r
158 # - BIT0 : NS - Non Secure bit\r
159 # - BIT1 : IRQ Handler\r
160 # - BIT2 : FIQ Handler\r
161 # - BIT3 : EA - External Abort\r
162 # - BIT4 : FW - F bit writable\r
163 # - BIT5 : AW - A bit writable\r
164 # - BIT6 : nET - Not Early Termination\r
165 # - BIT7 : SCD - Secure Monitor Call Disable\r
166 # - BIT8 : HCE - Hyp Call enable\r
167 # - BIT9 : SIF - Secure Instruction Fetch\r
168 # 0x31 = NS | EA | FW\r
169 gArmTokenSpaceGuid.PcdArmScr|0x31|UINT32|0x00000038\r
170\r
387653a4 171 # By default we do not do a transition to non-secure mode\r
172 gArmTokenSpaceGuid.PcdArmNonSecModeTransition|0x0|UINT32|0x0000003E\r
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173\r
174 # The Linux ATAGs are expected to be under 0x4000 (16KB) from the beginning of the System Memory\r
175 gArmTokenSpaceGuid.PcdArmLinuxAtagMaxOffset|0x4000|UINT32|0x00000020\r
176\r
387653a4 177 # If the fixed FDT address is not available, then it should be loaded below the kernel.\r
178 # The recommendation from the Linux kernel is to have the FDT below 16KB.\r
179 # (see the kernel doc: Documentation/arm/Booting)\r
180 gArmTokenSpaceGuid.PcdArmLinuxFdtMaxOffset|0x4000|UINT32|0x00000023\r
181 # The FDT blob must be loaded at a 64bit aligned address.\r
182 gArmTokenSpaceGuid.PcdArmLinuxFdtAlignment|0x8|UINT32|0x00000026\r
25402f5d 183\r
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184 # Non Secure Access Control Register\r
185 # - BIT15 : NSASEDIS - Disable Non-secure Advanced SIMD functionality\r
186 # - BIT14 : NSD32DIS - Disable Non-secure use of D16-D31\r
187 # - BIT11 : cp11 - Non-secure access to coprocessor 11 enable\r
188 # - BIT10 : cp10 - Non-secure access to coprocessor 10 enable\r
189 # 0xC00 = cp10 | cp11\r
190 gArmTokenSpaceGuid.PcdArmNsacr|0xC00|UINT32|0x00000039\r
191\r
25402f5d 192[PcdsFixedAtBuild.AARCH64]\r
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193 #\r
194 # AArch64 Security Extension\r
195 #\r
196\r
197 # Secure Configuration Register\r
198 # - BIT0 : NS - Non Secure bit\r
199 # - BIT1 : IRQ Handler\r
200 # - BIT2 : FIQ Handler\r
201 # - BIT3 : EA - External Abort\r
202 # - BIT4 : FW - F bit writable\r
203 # - BIT5 : AW - A bit writable\r
204 # - BIT6 : nET - Not Early Termination\r
205 # - BIT7 : SCD - Secure Monitor Call Disable\r
206 # - BIT8 : HCE - Hyp Call enable\r
207 # - BIT9 : SIF - Secure Instruction Fetch\r
208 # - BIT10: RW - Register width control for lower exception levels\r
209 # - BIT11: SIF - Enables Secure EL1 access to EL1 Architectural Timer\r
210 # - BIT12: TWI - Trap WFI\r
211 # - BIT13: TWE - Trap WFE\r
212 # 0x501 = NS | HCE | RW\r
213 gArmTokenSpaceGuid.PcdArmScr|0x501|UINT32|0x00000038\r
214\r
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215 # By default we do transition to EL2 non-secure mode with Stack for EL2.\r
216 # Mode Description Bits\r
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217 # NS EL2 SP2 all interrupts disabled = 0x3c9\r
218 # NS EL1 SP1 all interrupts disabled = 0x3c5\r
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219 # Other modes include using SP0 or switching to Aarch32, but these are\r
220 # not currently supported.\r
221 gArmTokenSpaceGuid.PcdArmNonSecModeTransition|0x3c9|UINT32|0x0000003E\r
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222 # If the fixed FDT address is not available, then it should be loaded above the kernel.\r
223 # The recommendation from the AArch64 Linux kernel is to have the FDT below 512MB.\r
224 # (see the kernel doc: Documentation/arm64/booting.txt)\r
225 gArmTokenSpaceGuid.PcdArmLinuxFdtMaxOffset|0x20000000|UINT32|0x00000023\r
226 # The FDT blob must be loaded at a 2MB aligned address.\r
227 gArmTokenSpaceGuid.PcdArmLinuxFdtAlignment|0x00200000|UINT32|0x00000026\r
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228\r
229\r
dc63be24 230#\r
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231# These PCDs are also defined as 'PcdsDynamic' or 'PcdsPatchableInModule' to be\r
232# redefined when using UEFI in a context of virtual machine.\r
dc63be24 233#\r
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234[PcdsFixedAtBuild.common, PcdsDynamic.common, PcdsPatchableInModule.common]\r
235\r
f8d7d6e1 236 # System Memory (DRAM): These PCDs define the region of in-built system memory\r
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237 # Some platforms can get DRAM extensions, these additional regions may be\r
238 # declared to UEFI using separate resource descriptor HOBs\r
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239 gArmTokenSpaceGuid.PcdSystemMemoryBase|0|UINT64|0x00000029\r
240 gArmTokenSpaceGuid.PcdSystemMemorySize|0|UINT64|0x0000002A\r
241\r
523b5266 242[PcdsFixedAtBuild.common, PcdsDynamic.common]\r
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243 #\r
244 # ARM Architectural Timer\r
245 #\r
246 gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz|0|UINT32|0x00000034\r
247\r
248 # ARM Architectural Timer Interrupt(GIC PPI) numbers\r
249 gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum|29|UINT32|0x00000035\r
250 gArmTokenSpaceGuid.PcdArmArchTimerIntrNum|30|UINT32|0x00000036\r
251 gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum|26|UINT32|0x00000040\r
252 gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum|27|UINT32|0x00000041\r
dc63be24 253\r
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254 #\r
255 # ARM Generic Watchdog\r
256 #\r
257\r
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258 gArmTokenSpaceGuid.PcdGenericWatchdogControlBase|0x2A440000|UINT64|0x00000007\r
259 gArmTokenSpaceGuid.PcdGenericWatchdogRefreshBase|0x2A450000|UINT64|0x00000008\r
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260 gArmTokenSpaceGuid.PcdGenericWatchdogEl2IntrNum|93|UINT32|0x00000009\r
261\r
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262 #\r
263 # ARM Generic Interrupt Controller\r
264 #\r
8a1f2378 265 gArmTokenSpaceGuid.PcdGicDistributorBase|0|UINT64|0x0000000C\r
919697ae 266 # Base address for the GIC Redistributor region that contains the boot CPU\r
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267 gArmTokenSpaceGuid.PcdGicRedistributorsBase|0|UINT64|0x0000000E\r
268 gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0|UINT64|0x0000000D\r
dc63be24 269 gArmTokenSpaceGuid.PcdGicSgiIntId|0|UINT32|0x00000025\r
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270\r
271 #\r
272 # Bases, sizes and translation offsets of IO and MMIO spaces, respectively.\r
273 # Note that "IO" is just another MMIO range that simulates IO space; there\r
274 # are no special instructions to access it.\r
275 #\r
276 # The base addresses PcdPciIoBase, PcdPciMmio32Base and PcdPciMmio64Base are\r
277 # specific to their containing address spaces. In order to get the physical\r
278 # address for the CPU, for a given access, the respective translation value\r
279 # has to be added.\r
280 #\r
281 # The translations always have to be initialized like this, using UINT64:\r
282 #\r
283 # UINT64 IoCpuBase; // mapping target in 64-bit cpu-physical space\r
284 # UINT64 Mmio32CpuBase; // mapping target in 64-bit cpu-physical space\r
285 # UINT64 Mmio64CpuBase; // mapping target in 64-bit cpu-physical space\r
286 #\r
287 # PcdPciIoTranslation = IoCpuBase - PcdPciIoBase;\r
288 # PcdPciMmio32Translation = Mmio32CpuBase - (UINT64)PcdPciMmio32Base;\r
289 # PcdPciMmio64Translation = Mmio64CpuBase - PcdPciMmio64Base;\r
290 #\r
291 # because (a) the target address space (ie. the cpu-physical space) is\r
292 # 64-bit, and (b) the translation values are meant as offsets for *modular*\r
293 # arithmetic.\r
294 #\r
295 # Accordingly, the translation itself needs to be implemented as:\r
296 #\r
297 # UINT64 UntranslatedIoAddress; // input parameter\r
298 # UINT32 UntranslatedMmio32Address; // input parameter\r
299 # UINT64 UntranslatedMmio64Address; // input parameter\r
300 #\r
301 # UINT64 TranslatedIoAddress; // output parameter\r
302 # UINT64 TranslatedMmio32Address; // output parameter\r
303 # UINT64 TranslatedMmio64Address; // output parameter\r
304 #\r
305 # TranslatedIoAddress = UntranslatedIoAddress +\r
306 # PcdPciIoTranslation;\r
307 # TranslatedMmio32Address = (UINT64)UntranslatedMmio32Address +\r
308 # PcdPciMmio32Translation;\r
309 # TranslatedMmio64Address = UntranslatedMmio64Address +\r
310 # PcdPciMmio64Translation;\r
311 #\r
312 # The modular arithmetic performed in UINT64 ensures that the translation\r
313 # works correctly regardless of the relation between IoCpuBase and\r
314 # PcdPciIoBase, Mmio32CpuBase and PcdPciMmio32Base, and Mmio64CpuBase and\r
315 # PcdPciMmio64Base.\r
316 #\r
317 gArmTokenSpaceGuid.PcdPciIoBase|0x0|UINT64|0x00000050\r
318 gArmTokenSpaceGuid.PcdPciIoSize|0x0|UINT64|0x00000051\r
319 gArmTokenSpaceGuid.PcdPciIoTranslation|0x0|UINT64|0x00000052\r
320 gArmTokenSpaceGuid.PcdPciMmio32Base|0x0|UINT32|0x00000053\r
321 gArmTokenSpaceGuid.PcdPciMmio32Size|0x0|UINT32|0x00000054\r
322 gArmTokenSpaceGuid.PcdPciMmio32Translation|0x0|UINT64|0x00000055\r
323 gArmTokenSpaceGuid.PcdPciMmio64Base|0x0|UINT64|0x00000056\r
324 gArmTokenSpaceGuid.PcdPciMmio64Size|0x0|UINT64|0x00000057\r
325 gArmTokenSpaceGuid.PcdPciMmio64Translation|0x0|UINT64|0x00000058\r
326\r
327 #\r
328 # Inclusive range of allowed PCI buses.\r
329 #\r
330 gArmTokenSpaceGuid.PcdPciBusMin|0x0|UINT32|0x00000059\r
331 gArmTokenSpaceGuid.PcdPciBusMax|0x0|UINT32|0x0000005A\r