ArmPkg: Replace BSD License with BSD+Patent License

[mirror_edk2.git] / ArmPkg / Drivers / ArmGic / GicV2 / ArmGicV2Dxe.c

/*++\r
\r
Copyright (c) 2009, Hewlett-Packard Company. All rights reserved.<BR>\r
Portions copyright (c) 2010, Apple Inc. All rights reserved.<BR>\r
Portions copyright (c) 2011-2017, ARM Ltd. All rights reserved.<BR>\r
\r
SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
Module Name:\r
\r
  GicV2/ArmGicV2Dxe.c\r
\r
Abstract:\r
\r
  Driver implementing the GicV2 interrupt controller protocol\r
\r
--*/\r
\r
#include <Library/ArmGicLib.h>\r
\r
#include "ArmGicDxe.h"\r
\r
#define ARM_GIC_DEFAULT_PRIORITY  0x80\r
\r
extern EFI_HARDWARE_INTERRUPT_PROTOCOL gHardwareInterruptV2Protocol;\r
extern EFI_HARDWARE_INTERRUPT2_PROTOCOL gHardwareInterrupt2V2Protocol;\r
\r
STATIC UINT32 mGicInterruptInterfaceBase;\r
STATIC UINT32 mGicDistributorBase;\r
\r
/**\r
  Enable interrupt source Source.\r
\r
  @param This     Instance pointer for this protocol\r
  @param Source   Hardware source of the interrupt\r
\r
  @retval EFI_SUCCESS       Source interrupt enabled.\r
  @retval EFI_UNSUPPORTED   Source interrupt is not supported\r
\r
**/\r
STATIC\r
EFI_STATUS\r
EFIAPI\r
GicV2EnableInterruptSource (\r
  IN EFI_HARDWARE_INTERRUPT_PROTOCOL    *This,\r
  IN HARDWARE_INTERRUPT_SOURCE          Source\r
  )\r
{\r
  if (Source >= mGicNumInterrupts) {\r
    ASSERT(FALSE);\r
    return EFI_UNSUPPORTED;\r
  }\r
\r
  ArmGicEnableInterrupt (mGicDistributorBase, 0, Source);\r
\r
  return EFI_SUCCESS;\r
}\r
\r
/**\r
  Disable interrupt source Source.\r
\r
  @param This     Instance pointer for this protocol\r
  @param Source   Hardware source of the interrupt\r
\r
  @retval EFI_SUCCESS       Source interrupt disabled.\r
  @retval EFI_UNSUPPORTED   Source interrupt is not supported\r
\r
**/\r
STATIC\r
EFI_STATUS\r
EFIAPI\r
GicV2DisableInterruptSource (\r
  IN EFI_HARDWARE_INTERRUPT_PROTOCOL    *This,\r
  IN HARDWARE_INTERRUPT_SOURCE          Source\r
  )\r
{\r
  if (Source >= mGicNumInterrupts) {\r
    ASSERT(FALSE);\r
    return EFI_UNSUPPORTED;\r
  }\r
\r
  ArmGicDisableInterrupt (mGicDistributorBase, 0, Source);\r
\r
  return EFI_SUCCESS;\r
}\r
\r
/**\r
  Return current state of interrupt source Source.\r
\r
  @param This     Instance pointer for this protocol\r
  @param Source   Hardware source of the interrupt\r
  @param InterruptState  TRUE: source enabled, FALSE: source disabled.\r
\r
  @retval EFI_SUCCESS       InterruptState is valid\r
  @retval EFI_UNSUPPORTED   Source interrupt is not supported\r
\r
**/\r
STATIC\r
EFI_STATUS\r
EFIAPI\r
GicV2GetInterruptSourceState (\r
  IN EFI_HARDWARE_INTERRUPT_PROTOCOL    *This,\r
  IN HARDWARE_INTERRUPT_SOURCE          Source,\r
  IN BOOLEAN                            *InterruptState\r
  )\r
{\r
  if (Source >= mGicNumInterrupts) {\r
    ASSERT(FALSE);\r
    return EFI_UNSUPPORTED;\r
  }\r
\r
  *InterruptState = ArmGicIsInterruptEnabled (mGicDistributorBase, 0, Source);\r
\r
  return EFI_SUCCESS;\r
}\r
\r
/**\r
  Signal to the hardware that the End Of Interrupt state\r
  has been reached.\r
\r
  @param This     Instance pointer for this protocol\r
  @param Source   Hardware source of the interrupt\r
\r
  @retval EFI_SUCCESS       Source interrupt EOI'ed.\r
  @retval EFI_UNSUPPORTED   Source interrupt is not supported\r
\r
**/\r
STATIC\r
EFI_STATUS\r
EFIAPI\r
GicV2EndOfInterrupt (\r
  IN EFI_HARDWARE_INTERRUPT_PROTOCOL    *This,\r
  IN HARDWARE_INTERRUPT_SOURCE          Source\r
  )\r
{\r
  if (Source >= mGicNumInterrupts) {\r
    ASSERT(FALSE);\r
    return EFI_UNSUPPORTED;\r
  }\r
\r
  ArmGicV2EndOfInterrupt (mGicInterruptInterfaceBase, Source);\r
  return EFI_SUCCESS;\r
}\r
\r
/**\r
  EFI_CPU_INTERRUPT_HANDLER that is called when a processor interrupt occurs.\r
\r
  @param  InterruptType    Defines the type of interrupt or exception that\r
                           occurred on the processor.This parameter is\r
                           processor architecture specific.\r
  @param  SystemContext    A pointer to the processor context when\r
                           the interrupt occurred on the processor.\r
\r
  @return None\r
\r
**/\r
STATIC\r
VOID\r
EFIAPI\r
GicV2IrqInterruptHandler (\r
  IN EFI_EXCEPTION_TYPE           InterruptType,\r
  IN EFI_SYSTEM_CONTEXT           SystemContext\r
  )\r
{\r
  UINT32                      GicInterrupt;\r
  HARDWARE_INTERRUPT_HANDLER  InterruptHandler;\r
\r
  GicInterrupt = ArmGicV2AcknowledgeInterrupt (mGicInterruptInterfaceBase);\r
\r
  // Special Interrupts (ID1020-ID1023) have an Interrupt ID greater than the\r
  // number of interrupt (ie: Spurious interrupt).\r
  if ((GicInterrupt & ARM_GIC_ICCIAR_ACKINTID) >= mGicNumInterrupts) {\r
    // The special interrupts do not need to be acknowledged\r
    return;\r
  }\r
\r
  InterruptHandler = gRegisteredInterruptHandlers[GicInterrupt];\r
  if (InterruptHandler != NULL) {\r
    // Call the registered interrupt handler.\r
    InterruptHandler (GicInterrupt, SystemContext);\r
  } else {\r
    DEBUG ((DEBUG_ERROR, "Spurious GIC interrupt: 0x%x\n", GicInterrupt));\r
    GicV2EndOfInterrupt (&gHardwareInterruptV2Protocol, GicInterrupt);\r
  }\r
}\r
\r
// The protocol instance produced by this driver\r
EFI_HARDWARE_INTERRUPT_PROTOCOL gHardwareInterruptV2Protocol = {\r
  RegisterInterruptSource,\r
  GicV2EnableInterruptSource,\r
  GicV2DisableInterruptSource,\r
  GicV2GetInterruptSourceState,\r
  GicV2EndOfInterrupt\r
};\r
\r
/**\r
  Get interrupt trigger type of an interrupt\r
\r
  @param This          Instance pointer for this protocol\r
  @param Source        Hardware source of the interrupt.\r
  @param TriggerType   Returns interrupt trigger type.\r
\r
  @retval EFI_SUCCESS       Source interrupt supported.\r
  @retval EFI_UNSUPPORTED   Source interrupt is not supported.\r
**/\r
STATIC\r
EFI_STATUS\r
EFIAPI\r
GicV2GetTriggerType (\r
  IN  EFI_HARDWARE_INTERRUPT2_PROTOCOL      *This,\r
  IN  HARDWARE_INTERRUPT_SOURCE              Source,\r
  OUT EFI_HARDWARE_INTERRUPT2_TRIGGER_TYPE  *TriggerType\r
  )\r
{\r
  UINTN                   RegAddress;\r
  UINTN                   Config1Bit;\r
  EFI_STATUS              Status;\r
\r
  Status = GicGetDistributorIcfgBaseAndBit (\r
              Source,\r
              &RegAddress,\r
              &Config1Bit\r
              );\r
\r
  if (EFI_ERROR (Status)) {\r
    return Status;\r
  }\r
\r
  if ((MmioRead32 (RegAddress) & (1 << Config1Bit)) == 0) {\r
     *TriggerType = EFI_HARDWARE_INTERRUPT2_TRIGGER_LEVEL_HIGH;\r
  } else {\r
     *TriggerType = EFI_HARDWARE_INTERRUPT2_TRIGGER_EDGE_RISING;\r
  }\r
\r
  return EFI_SUCCESS;\r
}\r
\r
/**\r
  Set interrupt trigger type of an interrupt\r
\r
  @param This          Instance pointer for this protocol\r
  @param Source        Hardware source of the interrupt.\r
  @param TriggerType   Interrupt trigger type.\r
\r
  @retval EFI_SUCCESS       Source interrupt supported.\r
  @retval EFI_UNSUPPORTED   Source interrupt is not supported.\r
**/\r
STATIC\r
EFI_STATUS\r
EFIAPI\r
GicV2SetTriggerType (\r
  IN  EFI_HARDWARE_INTERRUPT2_PROTOCOL      *This,\r
  IN  HARDWARE_INTERRUPT_SOURCE             Source,\r
  IN  EFI_HARDWARE_INTERRUPT2_TRIGGER_TYPE  TriggerType\r
  )\r
{\r
  UINTN                   RegAddress;\r
  UINTN                   Config1Bit;\r
  UINT32                  Value;\r
  EFI_STATUS              Status;\r
  BOOLEAN                 SourceEnabled;\r
\r
  if (   (TriggerType != EFI_HARDWARE_INTERRUPT2_TRIGGER_EDGE_RISING)\r
      && (TriggerType != EFI_HARDWARE_INTERRUPT2_TRIGGER_LEVEL_HIGH)) {\r
          DEBUG ((DEBUG_ERROR, "Invalid interrupt trigger type: %d\n", \\r
                  TriggerType));\r
          ASSERT (FALSE);\r
          return EFI_UNSUPPORTED;\r
  }\r
\r
  Status = GicGetDistributorIcfgBaseAndBit (\r
             Source,\r
             &RegAddress,\r
             &Config1Bit\r
             );\r
\r
  if (EFI_ERROR (Status)) {\r
    return Status;\r
  }\r
\r
  Status = GicV2GetInterruptSourceState (\r
             (EFI_HARDWARE_INTERRUPT_PROTOCOL*)This,\r
             Source,\r
             &SourceEnabled\r
             );\r
\r
  if (EFI_ERROR (Status)) {\r
    return Status;\r
  }\r
\r
  Value = (TriggerType == EFI_HARDWARE_INTERRUPT2_TRIGGER_EDGE_RISING)\r
          ?  ARM_GIC_ICDICFR_EDGE_TRIGGERED\r
          :  ARM_GIC_ICDICFR_LEVEL_TRIGGERED;\r
\r
  // Before changing the value, we must disable the interrupt,\r
  // otherwise GIC behavior is UNPREDICTABLE.\r
  if (SourceEnabled) {\r
    GicV2DisableInterruptSource (\r
      (EFI_HARDWARE_INTERRUPT_PROTOCOL*)This,\r
      Source\r
      );\r
  }\r
\r
  MmioAndThenOr32 (\r
    RegAddress,\r
    ~(0x1 << Config1Bit),\r
    Value << Config1Bit\r
    );\r
\r
  // Restore interrupt state\r
  if (SourceEnabled) {\r
    GicV2EnableInterruptSource (\r
      (EFI_HARDWARE_INTERRUPT_PROTOCOL*)This,\r
      Source\r
      );\r
  }\r
\r
  return EFI_SUCCESS;\r
}\r
\r
EFI_HARDWARE_INTERRUPT2_PROTOCOL gHardwareInterrupt2V2Protocol = {\r
  (HARDWARE_INTERRUPT2_REGISTER)RegisterInterruptSource,\r
  (HARDWARE_INTERRUPT2_ENABLE)GicV2EnableInterruptSource,\r
  (HARDWARE_INTERRUPT2_DISABLE)GicV2DisableInterruptSource,\r
  (HARDWARE_INTERRUPT2_INTERRUPT_STATE)GicV2GetInterruptSourceState,\r
  (HARDWARE_INTERRUPT2_END_OF_INTERRUPT)GicV2EndOfInterrupt,\r
  GicV2GetTriggerType,\r
  GicV2SetTriggerType\r
};\r
\r
/**\r
  Shutdown our hardware\r
\r
  DXE Core will disable interrupts and turn off the timer and disable\r
  interrupts after all the event handlers have run.\r
\r
  @param[in]  Event   The Event that is being processed\r
  @param[in]  Context Event Context\r
**/\r
STATIC\r
VOID\r
EFIAPI\r
GicV2ExitBootServicesEvent (\r
  IN EFI_EVENT  Event,\r
  IN VOID       *Context\r
  )\r
{\r
  UINTN    Index;\r
  UINT32   GicInterrupt;\r
\r
  // Disable all the interrupts\r
  for (Index = 0; Index < mGicNumInterrupts; Index++) {\r
    GicV2DisableInterruptSource (&gHardwareInterruptV2Protocol, Index);\r
  }\r
\r
  // Acknowledge all pending interrupts\r
  do {\r
    GicInterrupt = ArmGicV2AcknowledgeInterrupt (mGicInterruptInterfaceBase);\r
\r
    if ((GicInterrupt & ARM_GIC_ICCIAR_ACKINTID) < mGicNumInterrupts) {\r
      GicV2EndOfInterrupt (&gHardwareInterruptV2Protocol, GicInterrupt);\r
    }\r
  } while (!ARM_GIC_IS_SPECIAL_INTERRUPTS (GicInterrupt));\r
\r
  // Disable Gic Interface\r
  ArmGicV2DisableInterruptInterface (mGicInterruptInterfaceBase);\r
\r
  // Disable Gic Distributor\r
  ArmGicDisableDistributor (mGicDistributorBase);\r
}\r
\r
/**\r
  Initialize the state information for the CPU Architectural Protocol\r
\r
  @param  ImageHandle   of the loaded driver\r
  @param  SystemTable   Pointer to the System Table\r
\r
  @retval EFI_SUCCESS           Protocol registered\r
  @retval EFI_OUT_OF_RESOURCES  Cannot allocate protocol data structure\r
  @retval EFI_DEVICE_ERROR      Hardware problems\r
\r
**/\r
EFI_STATUS\r
GicV2DxeInitialize (\r
  IN EFI_HANDLE         ImageHandle,\r
  IN EFI_SYSTEM_TABLE   *SystemTable\r
  )\r
{\r
  EFI_STATUS              Status;\r
  UINTN                   Index;\r
  UINT32                  RegOffset;\r
  UINTN                   RegShift;\r
  UINT32                  CpuTarget;\r
\r
  // Make sure the Interrupt Controller Protocol is not already installed in\r
  // the system.\r
  ASSERT_PROTOCOL_ALREADY_INSTALLED (NULL, &gHardwareInterruptProtocolGuid);\r
\r
  mGicInterruptInterfaceBase = PcdGet64 (PcdGicInterruptInterfaceBase);\r
  mGicDistributorBase = PcdGet64 (PcdGicDistributorBase);\r
  mGicNumInterrupts = ArmGicGetMaxNumInterrupts (mGicDistributorBase);\r
\r
  for (Index = 0; Index < mGicNumInterrupts; Index++) {\r
    GicV2DisableInterruptSource (&gHardwareInterruptV2Protocol, Index);\r
\r
    // Set Priority\r
    RegOffset = Index / 4;\r
    RegShift = (Index % 4) * 8;\r
    MmioAndThenOr32 (\r
      mGicDistributorBase + ARM_GIC_ICDIPR + (4 * RegOffset),\r
      ~(0xff << RegShift),\r
      ARM_GIC_DEFAULT_PRIORITY << RegShift\r
      );\r
  }\r
\r
  // Targets the interrupts to the Primary Cpu\r
\r
  // Only Primary CPU will run this code. We can identify our GIC CPU ID by\r
  // reading the GIC Distributor Target register. The 8 first GICD_ITARGETSRn\r
  // are banked to each connected CPU. These 8 registers hold the CPU targets\r
  // fields for interrupts 0-31. More Info in the GIC Specification about\r
  // "Interrupt Processor Targets Registers"\r
\r
  // Read the first Interrupt Processor Targets Register (that corresponds to\r
  // the 4 first SGIs)\r
  CpuTarget = MmioRead32 (mGicDistributorBase + ARM_GIC_ICDIPTR);\r
\r
  // The CPU target is a bit field mapping each CPU to a GIC CPU Interface.\r
  // This value is 0 when we run on a uniprocessor platform.\r
  if (CpuTarget != 0) {\r
    // The 8 first Interrupt Processor Targets Registers are read-only\r
    for (Index = 8; Index < (mGicNumInterrupts / 4); Index++) {\r
      MmioWrite32 (\r
        mGicDistributorBase + ARM_GIC_ICDIPTR + (Index * 4),\r
        CpuTarget\r
        );\r
    }\r
  }\r
\r
  // Set binary point reg to 0x7 (no preemption)\r
  MmioWrite32 (mGicInterruptInterfaceBase + ARM_GIC_ICCBPR, 0x7);\r
\r
  // Set priority mask reg to 0xff to allow all priorities through\r
  MmioWrite32 (mGicInterruptInterfaceBase + ARM_GIC_ICCPMR, 0xff);\r
\r
  // Enable gic cpu interface\r
  ArmGicEnableInterruptInterface (mGicInterruptInterfaceBase);\r
\r
  // Enable gic distributor\r
  ArmGicEnableDistributor (mGicDistributorBase);\r
\r
  Status = InstallAndRegisterInterruptService (\r
             &gHardwareInterruptV2Protocol,\r
             &gHardwareInterrupt2V2Protocol,\r
             GicV2IrqInterruptHandler,\r
             GicV2ExitBootServicesEvent\r
             );\r
\r
  return Status;\r
}\r