projects / mirror_edk2.git / blame
| Commit | Line | Data |
|---|---|---|
| d7133859 OM |
1 | #\r |
| 2 | # Copyright (c) 2014, ARM Limited. All rights reserved.\r | |
| 3 | #\r | |
| 4059386c | 4 | # SPDX-License-Identifier: BSD-2-Clause-Patent\r |
| d7133859 OM |
5 | #\r |
| 6 | #\r | |
| 7 | \r | |
| 8 | #include <AsmMacroIoLibV8.h>\r | |
| 9 | \r | |
| 906e8ce4 AB |
10 | #if !defined(__clang__)\r |
| 11 | \r | |
| 12 | //\r | |
| 13 | // Clang versions before v3.6 do not support the GNU extension that allows\r | |
| 14 | // system registers outside of the IMPLEMENTATION DEFINED range to be specified\r | |
| 15 | // using the generic notation below. However, clang knows these registers by\r | |
| 16 | // their architectural names, so it has no need for these aliases anyway.\r | |
| 17 | //\r | |
| d7133859 OM |
18 | #define ICC_SRE_EL1 S3_0_C12_C12_5\r |
| 19 | #define ICC_SRE_EL2 S3_4_C12_C9_5\r | |
| 20 | #define ICC_SRE_EL3 S3_6_C12_C12_5\r | |
| 21 | #define ICC_IGRPEN1_EL1 S3_0_C12_C12_7\r | |
| 22 | #define ICC_EOIR1_EL1 S3_0_C12_C12_1\r | |
| 23 | #define ICC_IAR1_EL1 S3_0_C12_C12_0\r | |
| 24 | #define ICC_PMR_EL1 S3_0_C4_C6_0\r | |
| 25 | #define ICC_BPR1_EL1 S3_0_C12_C12_3\r | |
| 26 | \r | |
| 906e8ce4 AB |
27 | #endif\r |
| 28 | \r | |
| d7133859 OM |
29 | //UINT32\r |
| 30 | //EFIAPI\r | |
| 5f81082e | 31 | //ArmGicV3GetControlSystemRegisterEnable (\r |
| d7133859 OM |
32 | // VOID\r |
| 33 | // );\r | |
| f0883e35 | 34 | ASM_FUNC(ArmGicV3GetControlSystemRegisterEnable)\r |
| d7133859 OM |
35 | EL1_OR_EL2_OR_EL3(x1)\r |
| 36 | 1: mrs x0, ICC_SRE_EL1\r | |
| 37 | b 4f\r | |
| 38 | 2: mrs x0, ICC_SRE_EL2\r | |
| 39 | b 4f\r | |
| 40 | 3: mrs x0, ICC_SRE_EL3\r | |
| 41 | 4: ret\r | |
| 42 | \r | |
| 43 | //VOID\r | |
| 44 | //EFIAPI\r | |
| 5f81082e | 45 | //ArmGicV3SetControlSystemRegisterEnable (\r |
| d7133859 OM |
46 | // IN UINT32 ControlSystemRegisterEnable\r |
| 47 | // );\r | |
| f0883e35 | 48 | ASM_FUNC(ArmGicV3SetControlSystemRegisterEnable)\r |
| d7133859 OM |
49 | EL1_OR_EL2_OR_EL3(x1)\r |
| 50 | 1: msr ICC_SRE_EL1, x0\r | |
| 51 | b 4f\r | |
| 52 | 2: msr ICC_SRE_EL2, x0\r | |
| 53 | b 4f\r | |
| 54 | 3: msr ICC_SRE_EL3, x0\r | |
| 55 | 4: isb\r | |
| 56 | ret\r | |
| 57 | \r | |
| 58 | //VOID\r | |
| 59 | //ArmGicV3EnableInterruptInterface (\r | |
| 60 | // VOID\r | |
| 61 | // );\r | |
| f0883e35 | 62 | ASM_FUNC(ArmGicV3EnableInterruptInterface)\r |
| d7133859 OM |
63 | mov x0, #1\r |
| 64 | msr ICC_IGRPEN1_EL1, x0\r | |
| 65 | ret\r | |
| 66 | \r | |
| 67 | //VOID\r | |
| 68 | //ArmGicV3DisableInterruptInterface (\r | |
| 69 | // VOID\r | |
| 70 | // );\r | |
| f0883e35 | 71 | ASM_FUNC(ArmGicV3DisableInterruptInterface)\r |
| d7133859 OM |
72 | mov x0, #0\r |
| 73 | msr ICC_IGRPEN1_EL1, x0\r | |
| 74 | ret\r | |
| 75 | \r | |
| 76 | //VOID\r | |
| 77 | //ArmGicV3EndOfInterrupt (\r | |
| 78 | // IN UINTN InterruptId\r | |
| 79 | // );\r | |
| f0883e35 | 80 | ASM_FUNC(ArmGicV3EndOfInterrupt)\r |
| d7133859 OM |
81 | msr ICC_EOIR1_EL1, x0\r |
| 82 | ret\r | |
| 83 | \r | |
| 84 | //UINTN\r | |
| 85 | //ArmGicV3AcknowledgeInterrupt (\r | |
| 86 | // VOID\r | |
| 87 | // );\r | |
| f0883e35 | 88 | ASM_FUNC(ArmGicV3AcknowledgeInterrupt)\r |
| d7133859 OM |
89 | mrs x0, ICC_IAR1_EL1\r |
| 90 | ret\r | |
| 91 | \r | |
| 92 | //VOID\r | |
| 93 | //ArmGicV3SetPriorityMask (\r | |
| 94 | // IN UINTN Priority\r | |
| 95 | // );\r | |
| f0883e35 | 96 | ASM_FUNC(ArmGicV3SetPriorityMask)\r |
| d7133859 OM |
97 | msr ICC_PMR_EL1, x0\r |
| 98 | ret\r | |
| 99 | \r | |
| 100 | //VOID\r | |
| 101 | //ArmGicV3SetBinaryPointer (\r | |
| 102 | // IN UINTN BinaryPoint\r | |
| 103 | // );\r | |
| f0883e35 | 104 | ASM_FUNC(ArmGicV3SetBinaryPointer)\r |
| d7133859 OM |
105 | msr ICC_BPR1_EL1, x0\r |
| 106 | ret\r |