[mirror_edk2.git] / ArmPkg / Drivers / CpuDxe / ArmV4 / ExceptionSupport.asm

//------------------------------------------------------------------------------ \r
//\r
// Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
//\r
// This program and the accompanying materials\r
// are licensed and made available under the terms and conditions of the BSD License\r
// which accompanies this distribution.  The full text of the license may be found at\r
// http://opensource.org/licenses/bsd-license.php\r
//\r
// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
//\r
//------------------------------------------------------------------------------\r
\r
  EXPORT  ExceptionHandlersStart\r
  EXPORT  ExceptionHandlersEnd\r
  EXPORT  CommonExceptionEntry\r
  EXPORT  AsmCommonExceptionEntry\r
  IMPORT  CommonCExceptionHandler\r
\r
  PRESERVE8\r
  AREA  DxeExceptionHandlers, CODE, READONLY\r
  \r
ExceptionHandlersStart\r
\r
Reset\r
  b   ResetEntry\r
\r
UndefinedInstruction\r
  b   UndefinedInstructionEntry\r
\r
SoftwareInterrupt\r
  b   SoftwareInterruptEntry\r
\r
PrefetchAbort\r
  b   PrefetchAbortEntry\r
\r
DataAbort\r
  b   DataAbortEntry\r
\r
ReservedException\r
  b   ReservedExceptionEntry\r
\r
Irq\r
  b   IrqEntry\r
\r
Fiq\r
  b   FiqEntry\r
\r
ResetEntry\r
  stmfd     SP!,{R0-R1}\r
  mov       R0,#0\r
  ldr       R1,CommonExceptionEntry\r
  bx        R1\r
\r
UndefinedInstructionEntry\r
  stmfd     SP!,{R0-R1}\r
  mov       R0,#1\r
  ldr       R1,CommonExceptionEntry\r
  bx        R1\r
\r
SoftwareInterruptEntry\r
  stmfd     SP!,{R0-R1}\r
  mov       R0,#2\r
  ldr       R1,CommonExceptionEntry\r
  bx        R1\r
\r
PrefetchAbortEntry\r
  stmfd     SP!,{R0-R1}\r
  mov       R0,#3\r
  SUB       LR,LR,#4\r
  ldr       R1,CommonExceptionEntry\r
  bx        R1\r
\r
DataAbortEntry\r
  stmfd     SP!,{R0-R1}\r
  mov       R0,#4\r
  SUB       LR,LR,#8\r
  ldr       R1,CommonExceptionEntry\r
  bx        R1\r
\r
ReservedExceptionEntry\r
  stmfd     SP!,{R0-R1}\r
  mov       R0,#5\r
  ldr       R1,CommonExceptionEntry\r
  bx        R1\r
\r
IrqEntry\r
  stmfd     SP!,{R0-R1}\r
  mov       R0,#6\r
  SUB       LR,LR,#4\r
  ldr       R1,CommonExceptionEntry\r
  bx        R1\r
\r
FiqEntry\r
  stmfd     SP!,{R0-R1}\r
  mov       R0,#7\r
  SUB       LR,LR,#4\r
  ldr       R1,CommonExceptionEntry\r
  bx        R1\r
\r
CommonExceptionEntry\r
  dcd       0x12345678\r
\r
ExceptionHandlersEnd\r
\r
AsmCommonExceptionEntry\r
  mrc       p15, 0, r1, c6, c0, 2   ; Read IFAR\r
  stmfd     SP!,{R1}                ; Store the IFAR\r
  \r
  mrc       p15, 0, r1, c5, c0, 1   ; Read IFSR\r
  stmfd     SP!,{R1}                ; Store the IFSR\r
  \r
  mrc       p15, 0, r1, c6, c0, 0   ; Read DFAR\r
  stmfd     SP!,{R1}                ; Store the DFAR\r
  \r
  mrc       p15, 0, r1, c5, c0, 0   ; Read DFSR\r
  stmfd     SP!,{R1}                ; Store the DFSR\r
  \r
  mrs       R1,SPSR                 ; Read SPSR (which is the pre-exception CPSR)\r
  stmfd     SP!,{R1}                ; Store the SPSR\r
  \r
  stmfd     SP!,{LR}                ; Store the link register (which is the pre-exception PC)\r
  stmfd     SP,{SP,LR}^             ; Store user/system mode stack pointer and link register\r
  nop                               ; Required by ARM architecture\r
  SUB       SP,SP,#0x08             ; Adjust stack pointer\r
  stmfd     SP!,{R2-R12}            ; Store general purpose registers\r
  \r
  ldr       R3,[SP,#0x50]           ; Read saved R1 from the stack (it was saved by the exception entry routine)\r
  ldr       R2,[SP,#0x4C]           ; Read saved R0 from the stack (it was saved by the exception entry routine)\r
  stmfd     SP!,{R2-R3}             ; Store general purpose registers R0 and R1\r
  \r
  mov       R1,SP                   ; Prepare System Context pointer as an argument for the exception handler\r
  \r
  sub       SP,SP,#4                ; Adjust SP to preserve 8-byte alignment\r
  blx       CommonCExceptionHandler ; Call exception handler\r
  add       SP,SP,#4                ; Adjust SP back to where we were\r
  \r
  ldr       R2,[SP,#0x40]           ; Load CPSR from context, in case it has changed\r
  MSR       SPSR_cxsf,R2            ; Store it back to the SPSR to be restored when exiting this handler\r
\r
  ldmfd     SP!,{R0-R12}            ; Restore general purpose registers\r
  ldm       SP,{SP,LR}^             ; Restore user/system mode stack pointer and link register\r
  nop                               ; Required by ARM architecture\r
  add       SP,SP,#0x08             ; Adjust stack pointer\r
  ldmfd     SP!,{LR}                ; Restore the link register (which is the pre-exception PC)\r
  add       SP,SP,#0x1C             ; Clear out the remaining stack space\r
  movs      PC,LR                   ; Return from exception\r
  \r
  END\r
\r
\r
Commit	Line	Data
1e57a462	1	//------------------------------------------------------------------------------ \r
	2	//\r
	3	// Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
	4	//\r
	5	// This program and the accompanying materials\r
	6	// are licensed and made available under the terms and conditions of the BSD License\r
	7	// which accompanies this distribution. The full text of the license may be found at\r
	8	// http://opensource.org/licenses/bsd-license.php\r
	9	//\r
	10	// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
	11	// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
	12	//\r
	13	//------------------------------------------------------------------------------\r
	14	\r
	15	EXPORT ExceptionHandlersStart\r
	16	EXPORT ExceptionHandlersEnd\r
	17	EXPORT CommonExceptionEntry\r
	18	EXPORT AsmCommonExceptionEntry\r
	19	IMPORT CommonCExceptionHandler\r
	20	\r
	21	PRESERVE8\r
	22	AREA DxeExceptionHandlers, CODE, READONLY\r
	23	\r
	24	ExceptionHandlersStart\r
	25	\r
	26	Reset\r
	27	b ResetEntry\r
	28	\r
	29	UndefinedInstruction\r
	30	b UndefinedInstructionEntry\r
	31	\r
	32	SoftwareInterrupt\r
	33	b SoftwareInterruptEntry\r
	34	\r
	35	PrefetchAbort\r
	36	b PrefetchAbortEntry\r
	37	\r
	38	DataAbort\r
	39	b DataAbortEntry\r
	40	\r
	41	ReservedException\r
	42	b ReservedExceptionEntry\r
	43	\r
	44	Irq\r
	45	b IrqEntry\r
	46	\r
	47	Fiq\r
	48	b FiqEntry\r
	49	\r
	50	ResetEntry\r
	51	stmfd SP!,{R0-R1}\r
	52	mov R0,#0\r
	53	ldr R1,CommonExceptionEntry\r
	54	bx R1\r
	55	\r
	56	UndefinedInstructionEntry\r
	57	stmfd SP!,{R0-R1}\r
	58	mov R0,#1\r
	59	ldr R1,CommonExceptionEntry\r
	60	bx R1\r
	61	\r
	62	SoftwareInterruptEntry\r
	63	stmfd SP!,{R0-R1}\r
	64	mov R0,#2\r
65	ldr R1,CommonExceptionEntry\r
66	bx R1\r
67	\r
68	PrefetchAbortEntry\r
69	stmfd SP!,{R0-R1}\r
70	mov R0,#3\r
71	SUB LR,LR,#4\r
72	ldr R1,CommonExceptionEntry\r
73	bx R1\r
74	\r
75	DataAbortEntry\r
76	stmfd SP!,{R0-R1}\r
77	mov R0,#4\r
78	SUB LR,LR,#8\r
79	ldr R1,CommonExceptionEntry\r
80	bx R1\r
81	\r
82	ReservedExceptionEntry\r
83	stmfd SP!,{R0-R1}\r
84	mov R0,#5\r
85	ldr R1,CommonExceptionEntry\r
86	bx R1\r
87	\r
88	IrqEntry\r
89	stmfd SP!,{R0-R1}\r
90	mov R0,#6\r
91	SUB LR,LR,#4\r
92	ldr R1,CommonExceptionEntry\r
93	bx R1\r
94	\r
95	FiqEntry\r
96	stmfd SP!,{R0-R1}\r
97	mov R0,#7\r
98	SUB LR,LR,#4\r
99	ldr R1,CommonExceptionEntry\r
100	bx R1\r
101	\r
102	CommonExceptionEntry\r
103	dcd 0x12345678\r
104	\r
105	ExceptionHandlersEnd\r
106	\r
107	AsmCommonExceptionEntry\r
108	mrc p15, 0, r1, c6, c0, 2 ; Read IFAR\r
109	stmfd SP!,{R1} ; Store the IFAR\r
110	\r
111	mrc p15, 0, r1, c5, c0, 1 ; Read IFSR\r
112	stmfd SP!,{R1} ; Store the IFSR\r
113	\r
114	mrc p15, 0, r1, c6, c0, 0 ; Read DFAR\r
115	stmfd SP!,{R1} ; Store the DFAR\r
116	\r
117	mrc p15, 0, r1, c5, c0, 0 ; Read DFSR\r
118	stmfd SP!,{R1} ; Store the DFSR\r
119	\r
120	mrs R1,SPSR ; Read SPSR (which is the pre-exception CPSR)\r
121	stmfd SP!,{R1} ; Store the SPSR\r
122	\r
123	stmfd SP!,{LR} ; Store the link register (which is the pre-exception PC)\r
124	stmfd SP,{SP,LR}^ ; Store user/system mode stack pointer and link register\r
125	nop ; Required by ARM architecture\r
126	SUB SP,SP,#0x08 ; Adjust stack pointer\r
127	stmfd SP!,{R2-R12} ; Store general purpose registers\r
128	\r
129	ldr R3,[SP,#0x50] ; Read saved R1 from the stack (it was saved by the exception entry routine)\r
130	ldr R2,[SP,#0x4C] ; Read saved R0 from the stack (it was saved by the exception entry routine)\r
131	stmfd SP!,{R2-R3} ; Store general purpose registers R0 and R1\r
132	\r
133	mov R1,SP ; Prepare System Context pointer as an argument for the exception handler\r
134	\r
135	sub SP,SP,#4 ; Adjust SP to preserve 8-byte alignment\r
136	blx CommonCExceptionHandler ; Call exception handler\r
137	add SP,SP,#4 ; Adjust SP back to where we were\r
138	\r
139	ldr R2,[SP,#0x40] ; Load CPSR from context, in case it has changed\r
140	MSR SPSR_cxsf,R2 ; Store it back to the SPSR to be restored when exiting this handler\r
141	\r
142	ldmfd SP!,{R0-R12} ; Restore general purpose registers\r
143	ldm SP,{SP,LR}^ ; Restore user/system mode stack pointer and link register\r
144	nop ; Required by ARM architecture\r
145	add SP,SP,#0x08 ; Adjust stack pointer\r
146	ldmfd SP!,{LR} ; Restore the link register (which is the pre-exception PC)\r
147	add SP,SP,#0x1C ; Clear out the remaining stack space\r
148	movs PC,LR ; Return from exception\r
149	\r
150	END\r
151	\r
152	\r