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2ef2b01e A |
1 | /** @file\r |
2 | \r | |
d6ebcab7 | 3 | Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r |
8513037f | 4 | Copyright (c) 2011, ARM Limited. All rights reserved.\r |
3402aac7 | 5 | \r |
4059386c | 6 | SPDX-License-Identifier: BSD-2-Clause-Patent\r |
2ef2b01e A |
7 | \r |
8 | **/\r | |
9 | \r | |
10 | #include "CpuDxe.h"\r | |
11 | \r | |
8513037f | 12 | #include <Guid/IdleLoopEvent.h>\r |
13 | \r | |
429309e0 | 14 | BOOLEAN mIsFlushingGCD;\r |
f659880b A |
15 | \r |
16 | /**\r | |
3402aac7 RC |
17 | This function flushes the range of addresses from Start to Start+Length\r |
18 | from the processor's data cache. If Start is not aligned to a cache line\r | |
19 | boundary, then the bytes before Start to the preceding cache line boundary\r | |
20 | are also flushed. If Start+Length is not aligned to a cache line boundary,\r | |
21 | then the bytes past Start+Length to the end of the next cache line boundary\r | |
22 | are also flushed. The FlushType of EfiCpuFlushTypeWriteBackInvalidate must be\r | |
23 | supported. If the data cache is fully coherent with all DMA operations, then\r | |
24 | this function can just return EFI_SUCCESS. If the processor does not support\r | |
f659880b A |
25 | flushing a range of the data cache, then the entire data cache can be flushed.\r |
26 | \r | |
27 | @param This The EFI_CPU_ARCH_PROTOCOL instance.\r | |
28 | @param Start The beginning physical address to flush from the processor's data\r | |
29 | cache.\r | |
30 | @param Length The number of bytes to flush from the processor's data cache. This\r | |
31 | function may flush more bytes than Length specifies depending upon\r | |
32 | the granularity of the flush operation that the processor supports.\r | |
33 | @param FlushType Specifies the type of flush operation to perform.\r | |
34 | \r | |
35 | @retval EFI_SUCCESS The address range from Start to Start+Length was flushed from\r | |
36 | the processor's data cache.\r | |
fcb880ec | 37 | @retval EFI_UNSUPPORTED The processor does not support the cache flush type specified\r |
f659880b A |
38 | by FlushType.\r |
39 | @retval EFI_DEVICE_ERROR The address range from Start to Start+Length could not be flushed\r | |
40 | from the processor's data cache.\r | |
41 | \r | |
42 | **/\r | |
2ef2b01e A |
43 | EFI_STATUS\r |
44 | EFIAPI\r | |
45 | CpuFlushCpuDataCache (\r | |
429309e0 MK |
46 | IN EFI_CPU_ARCH_PROTOCOL *This,\r |
47 | IN EFI_PHYSICAL_ADDRESS Start,\r | |
48 | IN UINT64 Length,\r | |
49 | IN EFI_CPU_FLUSH_TYPE FlushType\r | |
2ef2b01e A |
50 | )\r |
51 | {\r | |
52 | switch (FlushType) {\r | |
53 | case EfiCpuFlushTypeWriteBack:\r | |
8a4d81e6 | 54 | WriteBackDataCacheRange ((VOID *)(UINTN)Start, (UINTN)Length);\r |
2ef2b01e A |
55 | break;\r |
56 | case EfiCpuFlushTypeInvalidate:\r | |
8a4d81e6 | 57 | InvalidateDataCacheRange ((VOID *)(UINTN)Start, (UINTN)Length);\r |
2ef2b01e A |
58 | break;\r |
59 | case EfiCpuFlushTypeWriteBackInvalidate:\r | |
8a4d81e6 | 60 | WriteBackInvalidateDataCacheRange ((VOID *)(UINTN)Start, (UINTN)Length);\r |
2ef2b01e A |
61 | break;\r |
62 | default:\r | |
63 | return EFI_INVALID_PARAMETER;\r | |
64 | }\r | |
3402aac7 | 65 | \r |
2ef2b01e A |
66 | return EFI_SUCCESS;\r |
67 | }\r | |
68 | \r | |
f659880b | 69 | /**\r |
3402aac7 | 70 | This function enables interrupt processing by the processor.\r |
f659880b A |
71 | \r |
72 | @param This The EFI_CPU_ARCH_PROTOCOL instance.\r | |
73 | \r | |
74 | @retval EFI_SUCCESS Interrupts are enabled on the processor.\r | |
75 | @retval EFI_DEVICE_ERROR Interrupts could not be enabled on the processor.\r | |
76 | \r | |
77 | **/\r | |
2ef2b01e A |
78 | EFI_STATUS\r |
79 | EFIAPI\r | |
80 | CpuEnableInterrupt (\r | |
429309e0 | 81 | IN EFI_CPU_ARCH_PROTOCOL *This\r |
2ef2b01e A |
82 | )\r |
83 | {\r | |
d213712d | 84 | ArmEnableInterrupts ();\r |
8a4d81e6 | 85 | \r |
2ef2b01e A |
86 | return EFI_SUCCESS;\r |
87 | }\r | |
88 | \r | |
f659880b A |
89 | /**\r |
90 | This function disables interrupt processing by the processor.\r | |
91 | \r | |
92 | @param This The EFI_CPU_ARCH_PROTOCOL instance.\r | |
93 | \r | |
94 | @retval EFI_SUCCESS Interrupts are disabled on the processor.\r | |
95 | @retval EFI_DEVICE_ERROR Interrupts could not be disabled on the processor.\r | |
96 | \r | |
97 | **/\r | |
2ef2b01e A |
98 | EFI_STATUS\r |
99 | EFIAPI\r | |
100 | CpuDisableInterrupt (\r | |
429309e0 | 101 | IN EFI_CPU_ARCH_PROTOCOL *This\r |
2ef2b01e A |
102 | )\r |
103 | {\r | |
d213712d | 104 | ArmDisableInterrupts ();\r |
8a4d81e6 | 105 | \r |
2ef2b01e A |
106 | return EFI_SUCCESS;\r |
107 | }\r | |
108 | \r | |
f659880b | 109 | /**\r |
3402aac7 RC |
110 | This function retrieves the processor's current interrupt state a returns it in\r |
111 | State. If interrupts are currently enabled, then TRUE is returned. If interrupts\r | |
f659880b A |
112 | are currently disabled, then FALSE is returned.\r |
113 | \r | |
114 | @param This The EFI_CPU_ARCH_PROTOCOL instance.\r | |
115 | @param State A pointer to the processor's current interrupt state. Set to TRUE if\r | |
116 | interrupts are enabled and FALSE if interrupts are disabled.\r | |
117 | \r | |
118 | @retval EFI_SUCCESS The processor's current interrupt state was returned in State.\r | |
119 | @retval EFI_INVALID_PARAMETER State is NULL.\r | |
120 | \r | |
121 | **/\r | |
2ef2b01e A |
122 | EFI_STATUS\r |
123 | EFIAPI\r | |
124 | CpuGetInterruptState (\r | |
429309e0 MK |
125 | IN EFI_CPU_ARCH_PROTOCOL *This,\r |
126 | OUT BOOLEAN *State\r | |
2ef2b01e A |
127 | )\r |
128 | {\r | |
129 | if (State == NULL) {\r | |
130 | return EFI_INVALID_PARAMETER;\r | |
131 | }\r | |
132 | \r | |
429309e0 | 133 | *State = ArmGetInterruptState ();\r |
2ef2b01e A |
134 | return EFI_SUCCESS;\r |
135 | }\r | |
136 | \r | |
f659880b A |
137 | /**\r |
138 | This function generates an INIT on the processor. If this function succeeds, then the\r | |
3402aac7 RC |
139 | processor will be reset, and control will not be returned to the caller. If InitType is\r |
140 | not supported by this processor, or the processor cannot programmatically generate an\r | |
141 | INIT without help from external hardware, then EFI_UNSUPPORTED is returned. If an error\r | |
f659880b A |
142 | occurs attempting to generate an INIT, then EFI_DEVICE_ERROR is returned.\r |
143 | \r | |
144 | @param This The EFI_CPU_ARCH_PROTOCOL instance.\r | |
145 | @param InitType The type of processor INIT to perform.\r | |
146 | \r | |
147 | @retval EFI_SUCCESS The processor INIT was performed. This return code should never be seen.\r | |
148 | @retval EFI_UNSUPPORTED The processor INIT operation specified by InitType is not supported\r | |
149 | by this processor.\r | |
150 | @retval EFI_DEVICE_ERROR The processor INIT failed.\r | |
151 | \r | |
152 | **/\r | |
2ef2b01e A |
153 | EFI_STATUS\r |
154 | EFIAPI\r | |
155 | CpuInit (\r | |
429309e0 MK |
156 | IN EFI_CPU_ARCH_PROTOCOL *This,\r |
157 | IN EFI_CPU_INIT_TYPE InitType\r | |
2ef2b01e A |
158 | )\r |
159 | {\r | |
160 | return EFI_UNSUPPORTED;\r | |
161 | }\r | |
162 | \r | |
163 | EFI_STATUS\r | |
164 | EFIAPI\r | |
165 | CpuRegisterInterruptHandler (\r | |
429309e0 MK |
166 | IN EFI_CPU_ARCH_PROTOCOL *This,\r |
167 | IN EFI_EXCEPTION_TYPE InterruptType,\r | |
168 | IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler\r | |
2ef2b01e A |
169 | )\r |
170 | {\r | |
8a4d81e6 | 171 | return RegisterInterruptHandler (InterruptType, InterruptHandler);\r |
2ef2b01e A |
172 | }\r |
173 | \r | |
174 | EFI_STATUS\r | |
175 | EFIAPI\r | |
176 | CpuGetTimerValue (\r | |
429309e0 MK |
177 | IN EFI_CPU_ARCH_PROTOCOL *This,\r |
178 | IN UINT32 TimerIndex,\r | |
179 | OUT UINT64 *TimerValue,\r | |
180 | OUT UINT64 *TimerPeriod OPTIONAL\r | |
2ef2b01e A |
181 | )\r |
182 | {\r | |
183 | return EFI_UNSUPPORTED;\r | |
184 | }\r | |
185 | \r | |
8513037f | 186 | /**\r |
187 | Callback function for idle events.\r | |
3402aac7 | 188 | \r |
8513037f | 189 | @param Event Event whose notification function is being invoked.\r |
190 | @param Context The pointer to the notification function's context,\r | |
191 | which is implementation-dependent.\r | |
192 | \r | |
193 | **/\r | |
194 | VOID\r | |
195 | EFIAPI\r | |
196 | IdleLoopEventCallback (\r | |
429309e0 MK |
197 | IN EFI_EVENT Event,\r |
198 | IN VOID *Context\r | |
8513037f | 199 | )\r |
200 | {\r | |
201 | CpuSleep ();\r | |
202 | }\r | |
2ef2b01e A |
203 | \r |
204 | //\r | |
205 | // Globals used to initialize the protocol\r | |
206 | //\r | |
429309e0 MK |
207 | EFI_HANDLE mCpuHandle = NULL;\r |
208 | EFI_CPU_ARCH_PROTOCOL mCpu = {\r | |
2ef2b01e A |
209 | CpuFlushCpuDataCache,\r |
210 | CpuEnableInterrupt,\r | |
211 | CpuDisableInterrupt,\r | |
212 | CpuGetInterruptState,\r | |
213 | CpuInit,\r | |
214 | CpuRegisterInterruptHandler,\r | |
215 | CpuGetTimerValue,\r | |
216 | CpuSetMemoryAttributes,\r | |
217 | 0, // NumberOfTimers\r | |
756a514a | 218 | 2048, // DmaBufferAlignment\r |
2ef2b01e A |
219 | };\r |
220 | \r | |
756a514a AB |
221 | STATIC\r |
222 | VOID\r | |
223 | InitializeDma (\r | |
429309e0 | 224 | IN OUT EFI_CPU_ARCH_PROTOCOL *CpuArchProtocol\r |
756a514a AB |
225 | )\r |
226 | {\r | |
227 | CpuArchProtocol->DmaBufferAlignment = ArmCacheWritebackGranule ();\r | |
228 | }\r | |
229 | \r | |
2ef2b01e A |
230 | EFI_STATUS\r |
231 | CpuDxeInitialize (\r | |
429309e0 MK |
232 | IN EFI_HANDLE ImageHandle,\r |
233 | IN EFI_SYSTEM_TABLE *SystemTable\r | |
2ef2b01e | 234 | )\r |
f659880b A |
235 | {\r |
236 | EFI_STATUS Status;\r | |
429309e0 | 237 | EFI_EVENT IdleLoopEvent;\r |
f659880b | 238 | \r |
3402aac7 RC |
239 | InitializeExceptions (&mCpu);\r |
240 | \r | |
756a514a AB |
241 | InitializeDma (&mCpu);\r |
242 | \r | |
f659880b | 243 | Status = gBS->InstallMultipleProtocolInterfaces (\r |
429309e0 MK |
244 | &mCpuHandle,\r |
245 | &gEfiCpuArchProtocolGuid,\r | |
246 | &mCpu,\r | |
247 | NULL\r | |
248 | );\r | |
3402aac7 | 249 | \r |
f659880b A |
250 | //\r |
251 | // Make sure GCD and MMU settings match. This API calls gDS->SetMemorySpaceAttributes ()\r | |
252 | // and that calls EFI_CPU_ARCH_PROTOCOL.SetMemoryAttributes, so this code needs to go\r | |
253 | // after the protocol is installed\r | |
254 | //\r | |
3b44bb55 | 255 | mIsFlushingGCD = TRUE;\r |
f659880b | 256 | SyncCacheConfig (&mCpu);\r |
3b44bb55 | 257 | mIsFlushingGCD = FALSE;\r |
3402aac7 | 258 | \r |
8513037f | 259 | //\r |
260 | // Setup a callback for idle events\r | |
261 | //\r | |
262 | Status = gBS->CreateEventEx (\r | |
263 | EVT_NOTIFY_SIGNAL,\r | |
264 | TPL_NOTIFY,\r | |
265 | IdleLoopEventCallback,\r | |
266 | NULL,\r | |
267 | &gIdleLoopEventGuid,\r | |
268 | &IdleLoopEvent\r | |
269 | );\r | |
270 | ASSERT_EFI_ERROR (Status);\r | |
271 | \r | |
f659880b | 272 | return Status;\r |
2ef2b01e | 273 | }\r |