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2ef2b01e A |
1 | /** @file\r |
2 | \r | |
d6ebcab7 | 3 | Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r |
8513037f | 4 | Copyright (c) 2011, ARM Limited. All rights reserved.\r |
3402aac7 | 5 | \r |
4059386c | 6 | SPDX-License-Identifier: BSD-2-Clause-Patent\r |
2ef2b01e A |
7 | \r |
8 | **/\r | |
9 | \r | |
10 | #include "CpuDxe.h"\r | |
11 | \r | |
8513037f | 12 | #include <Guid/IdleLoopEvent.h>\r |
13 | \r | |
3b44bb55 | 14 | BOOLEAN mIsFlushingGCD;\r |
f659880b A |
15 | \r |
16 | /**\r | |
3402aac7 RC |
17 | This function flushes the range of addresses from Start to Start+Length\r |
18 | from the processor's data cache. If Start is not aligned to a cache line\r | |
19 | boundary, then the bytes before Start to the preceding cache line boundary\r | |
20 | are also flushed. If Start+Length is not aligned to a cache line boundary,\r | |
21 | then the bytes past Start+Length to the end of the next cache line boundary\r | |
22 | are also flushed. The FlushType of EfiCpuFlushTypeWriteBackInvalidate must be\r | |
23 | supported. If the data cache is fully coherent with all DMA operations, then\r | |
24 | this function can just return EFI_SUCCESS. If the processor does not support\r | |
f659880b A |
25 | flushing a range of the data cache, then the entire data cache can be flushed.\r |
26 | \r | |
27 | @param This The EFI_CPU_ARCH_PROTOCOL instance.\r | |
28 | @param Start The beginning physical address to flush from the processor's data\r | |
29 | cache.\r | |
30 | @param Length The number of bytes to flush from the processor's data cache. This\r | |
31 | function may flush more bytes than Length specifies depending upon\r | |
32 | the granularity of the flush operation that the processor supports.\r | |
33 | @param FlushType Specifies the type of flush operation to perform.\r | |
34 | \r | |
35 | @retval EFI_SUCCESS The address range from Start to Start+Length was flushed from\r | |
36 | the processor's data cache.\r | |
fcb880ec | 37 | @retval EFI_UNSUPPORTED The processor does not support the cache flush type specified\r |
f659880b A |
38 | by FlushType.\r |
39 | @retval EFI_DEVICE_ERROR The address range from Start to Start+Length could not be flushed\r | |
40 | from the processor's data cache.\r | |
41 | \r | |
42 | **/\r | |
2ef2b01e A |
43 | EFI_STATUS\r |
44 | EFIAPI\r | |
45 | CpuFlushCpuDataCache (\r | |
46 | IN EFI_CPU_ARCH_PROTOCOL *This,\r | |
47 | IN EFI_PHYSICAL_ADDRESS Start,\r | |
48 | IN UINT64 Length,\r | |
49 | IN EFI_CPU_FLUSH_TYPE FlushType\r | |
50 | )\r | |
51 | {\r | |
f659880b | 52 | \r |
2ef2b01e A |
53 | switch (FlushType) {\r |
54 | case EfiCpuFlushTypeWriteBack:\r | |
8a4d81e6 | 55 | WriteBackDataCacheRange ((VOID *)(UINTN)Start, (UINTN)Length);\r |
2ef2b01e A |
56 | break;\r |
57 | case EfiCpuFlushTypeInvalidate:\r | |
8a4d81e6 | 58 | InvalidateDataCacheRange ((VOID *)(UINTN)Start, (UINTN)Length);\r |
2ef2b01e A |
59 | break;\r |
60 | case EfiCpuFlushTypeWriteBackInvalidate:\r | |
8a4d81e6 | 61 | WriteBackInvalidateDataCacheRange ((VOID *)(UINTN)Start, (UINTN)Length);\r |
2ef2b01e A |
62 | break;\r |
63 | default:\r | |
64 | return EFI_INVALID_PARAMETER;\r | |
65 | }\r | |
3402aac7 | 66 | \r |
2ef2b01e A |
67 | return EFI_SUCCESS;\r |
68 | }\r | |
69 | \r | |
f659880b A |
70 | \r |
71 | /**\r | |
3402aac7 | 72 | This function enables interrupt processing by the processor.\r |
f659880b A |
73 | \r |
74 | @param This The EFI_CPU_ARCH_PROTOCOL instance.\r | |
75 | \r | |
76 | @retval EFI_SUCCESS Interrupts are enabled on the processor.\r | |
77 | @retval EFI_DEVICE_ERROR Interrupts could not be enabled on the processor.\r | |
78 | \r | |
79 | **/\r | |
2ef2b01e A |
80 | EFI_STATUS\r |
81 | EFIAPI\r | |
82 | CpuEnableInterrupt (\r | |
83 | IN EFI_CPU_ARCH_PROTOCOL *This\r | |
84 | )\r | |
85 | {\r | |
d213712d | 86 | ArmEnableInterrupts ();\r |
8a4d81e6 | 87 | \r |
2ef2b01e A |
88 | return EFI_SUCCESS;\r |
89 | }\r | |
90 | \r | |
91 | \r | |
f659880b A |
92 | /**\r |
93 | This function disables interrupt processing by the processor.\r | |
94 | \r | |
95 | @param This The EFI_CPU_ARCH_PROTOCOL instance.\r | |
96 | \r | |
97 | @retval EFI_SUCCESS Interrupts are disabled on the processor.\r | |
98 | @retval EFI_DEVICE_ERROR Interrupts could not be disabled on the processor.\r | |
99 | \r | |
100 | **/\r | |
2ef2b01e A |
101 | EFI_STATUS\r |
102 | EFIAPI\r | |
103 | CpuDisableInterrupt (\r | |
104 | IN EFI_CPU_ARCH_PROTOCOL *This\r | |
105 | )\r | |
106 | {\r | |
d213712d | 107 | ArmDisableInterrupts ();\r |
8a4d81e6 | 108 | \r |
2ef2b01e A |
109 | return EFI_SUCCESS;\r |
110 | }\r | |
111 | \r | |
f659880b A |
112 | \r |
113 | /**\r | |
3402aac7 RC |
114 | This function retrieves the processor's current interrupt state a returns it in\r |
115 | State. If interrupts are currently enabled, then TRUE is returned. If interrupts\r | |
f659880b A |
116 | are currently disabled, then FALSE is returned.\r |
117 | \r | |
118 | @param This The EFI_CPU_ARCH_PROTOCOL instance.\r | |
119 | @param State A pointer to the processor's current interrupt state. Set to TRUE if\r | |
120 | interrupts are enabled and FALSE if interrupts are disabled.\r | |
121 | \r | |
122 | @retval EFI_SUCCESS The processor's current interrupt state was returned in State.\r | |
123 | @retval EFI_INVALID_PARAMETER State is NULL.\r | |
124 | \r | |
125 | **/\r | |
2ef2b01e A |
126 | EFI_STATUS\r |
127 | EFIAPI\r | |
128 | CpuGetInterruptState (\r | |
129 | IN EFI_CPU_ARCH_PROTOCOL *This,\r | |
130 | OUT BOOLEAN *State\r | |
131 | )\r | |
132 | {\r | |
133 | if (State == NULL) {\r | |
134 | return EFI_INVALID_PARAMETER;\r | |
135 | }\r | |
136 | \r | |
e3aa7252 | 137 | *State = ArmGetInterruptState();\r |
2ef2b01e A |
138 | return EFI_SUCCESS;\r |
139 | }\r | |
140 | \r | |
f659880b A |
141 | \r |
142 | /**\r | |
143 | This function generates an INIT on the processor. If this function succeeds, then the\r | |
3402aac7 RC |
144 | processor will be reset, and control will not be returned to the caller. If InitType is\r |
145 | not supported by this processor, or the processor cannot programmatically generate an\r | |
146 | INIT without help from external hardware, then EFI_UNSUPPORTED is returned. If an error\r | |
f659880b A |
147 | occurs attempting to generate an INIT, then EFI_DEVICE_ERROR is returned.\r |
148 | \r | |
149 | @param This The EFI_CPU_ARCH_PROTOCOL instance.\r | |
150 | @param InitType The type of processor INIT to perform.\r | |
151 | \r | |
152 | @retval EFI_SUCCESS The processor INIT was performed. This return code should never be seen.\r | |
153 | @retval EFI_UNSUPPORTED The processor INIT operation specified by InitType is not supported\r | |
154 | by this processor.\r | |
155 | @retval EFI_DEVICE_ERROR The processor INIT failed.\r | |
156 | \r | |
157 | **/\r | |
2ef2b01e A |
158 | EFI_STATUS\r |
159 | EFIAPI\r | |
160 | CpuInit (\r | |
161 | IN EFI_CPU_ARCH_PROTOCOL *This,\r | |
162 | IN EFI_CPU_INIT_TYPE InitType\r | |
163 | )\r | |
164 | {\r | |
165 | return EFI_UNSUPPORTED;\r | |
166 | }\r | |
167 | \r | |
168 | EFI_STATUS\r | |
169 | EFIAPI\r | |
170 | CpuRegisterInterruptHandler (\r | |
171 | IN EFI_CPU_ARCH_PROTOCOL *This,\r | |
172 | IN EFI_EXCEPTION_TYPE InterruptType,\r | |
173 | IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler\r | |
174 | )\r | |
175 | {\r | |
8a4d81e6 | 176 | return RegisterInterruptHandler (InterruptType, InterruptHandler);\r |
2ef2b01e A |
177 | }\r |
178 | \r | |
179 | EFI_STATUS\r | |
180 | EFIAPI\r | |
181 | CpuGetTimerValue (\r | |
182 | IN EFI_CPU_ARCH_PROTOCOL *This,\r | |
183 | IN UINT32 TimerIndex,\r | |
184 | OUT UINT64 *TimerValue,\r | |
185 | OUT UINT64 *TimerPeriod OPTIONAL\r | |
186 | )\r | |
187 | {\r | |
188 | return EFI_UNSUPPORTED;\r | |
189 | }\r | |
190 | \r | |
8513037f | 191 | /**\r |
192 | Callback function for idle events.\r | |
3402aac7 | 193 | \r |
8513037f | 194 | @param Event Event whose notification function is being invoked.\r |
195 | @param Context The pointer to the notification function's context,\r | |
196 | which is implementation-dependent.\r | |
197 | \r | |
198 | **/\r | |
199 | VOID\r | |
200 | EFIAPI\r | |
201 | IdleLoopEventCallback (\r | |
202 | IN EFI_EVENT Event,\r | |
203 | IN VOID *Context\r | |
204 | )\r | |
205 | {\r | |
206 | CpuSleep ();\r | |
207 | }\r | |
2ef2b01e A |
208 | \r |
209 | //\r | |
210 | // Globals used to initialize the protocol\r | |
211 | //\r | |
212 | EFI_HANDLE mCpuHandle = NULL;\r | |
213 | EFI_CPU_ARCH_PROTOCOL mCpu = {\r | |
214 | CpuFlushCpuDataCache,\r | |
215 | CpuEnableInterrupt,\r | |
216 | CpuDisableInterrupt,\r | |
217 | CpuGetInterruptState,\r | |
218 | CpuInit,\r | |
219 | CpuRegisterInterruptHandler,\r | |
220 | CpuGetTimerValue,\r | |
221 | CpuSetMemoryAttributes,\r | |
222 | 0, // NumberOfTimers\r | |
756a514a | 223 | 2048, // DmaBufferAlignment\r |
2ef2b01e A |
224 | };\r |
225 | \r | |
756a514a AB |
226 | STATIC\r |
227 | VOID\r | |
228 | InitializeDma (\r | |
229 | IN OUT EFI_CPU_ARCH_PROTOCOL *CpuArchProtocol\r | |
230 | )\r | |
231 | {\r | |
232 | CpuArchProtocol->DmaBufferAlignment = ArmCacheWritebackGranule ();\r | |
233 | }\r | |
234 | \r | |
2ef2b01e A |
235 | EFI_STATUS\r |
236 | CpuDxeInitialize (\r | |
237 | IN EFI_HANDLE ImageHandle,\r | |
238 | IN EFI_SYSTEM_TABLE *SystemTable\r | |
239 | )\r | |
f659880b A |
240 | {\r |
241 | EFI_STATUS Status;\r | |
8513037f | 242 | EFI_EVENT IdleLoopEvent;\r |
f659880b | 243 | \r |
3402aac7 RC |
244 | InitializeExceptions (&mCpu);\r |
245 | \r | |
756a514a AB |
246 | InitializeDma (&mCpu);\r |
247 | \r | |
f659880b | 248 | Status = gBS->InstallMultipleProtocolInterfaces (\r |
3402aac7 RC |
249 | &mCpuHandle,\r |
250 | &gEfiCpuArchProtocolGuid, &mCpu,\r | |
f659880b A |
251 | NULL\r |
252 | );\r | |
3402aac7 | 253 | \r |
f659880b A |
254 | //\r |
255 | // Make sure GCD and MMU settings match. This API calls gDS->SetMemorySpaceAttributes ()\r | |
256 | // and that calls EFI_CPU_ARCH_PROTOCOL.SetMemoryAttributes, so this code needs to go\r | |
257 | // after the protocol is installed\r | |
258 | //\r | |
3b44bb55 | 259 | mIsFlushingGCD = TRUE;\r |
f659880b | 260 | SyncCacheConfig (&mCpu);\r |
3b44bb55 | 261 | mIsFlushingGCD = FALSE;\r |
3402aac7 | 262 | \r |
44788bae | 263 | // If the platform is a MPCore system then install the Configuration Table describing the\r |
264 | // secondary core states\r | |
886f97c8 | 265 | if (ArmIsMpCore()) {\r |
44788bae | 266 | PublishArmProcessorTable();\r |
267 | }\r | |
268 | \r | |
8513037f | 269 | //\r |
270 | // Setup a callback for idle events\r | |
271 | //\r | |
272 | Status = gBS->CreateEventEx (\r | |
273 | EVT_NOTIFY_SIGNAL,\r | |
274 | TPL_NOTIFY,\r | |
275 | IdleLoopEventCallback,\r | |
276 | NULL,\r | |
277 | &gIdleLoopEventGuid,\r | |
278 | &IdleLoopEvent\r | |
279 | );\r | |
280 | ASSERT_EFI_ERROR (Status);\r | |
281 | \r | |
f659880b | 282 | return Status;\r |
2ef2b01e | 283 | }\r |