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1 | /*++\r |
2 | \r | |
3 | Copyright (c) 2009, Hewlett-Packard Company \r | |
4 | Portions copyright (c) 2010, Apple Inc. All rights reserved.\r | |
5 | \r | |
6 | All rights reserved. This program and the accompanying materials \r | |
7 | are licensed and made available under the terms and conditions of the BSD License \r | |
8 | which accompanies this distribution. The full text of the license may be found at \r | |
9 | http://opensource.org/licenses/bsd-license.php \r | |
10 | \r | |
11 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r | |
12 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r | |
13 | \r | |
14 | \r | |
15 | --*/\r | |
16 | \r | |
17 | #include "CpuDxe.h"\r | |
18 | \r | |
19 | //\r | |
20 | // Translation/page table definitions\r | |
21 | //\r | |
22 | \r | |
23 | // First Level Descriptors\r | |
24 | typedef UINT32 ARM_FIRST_LEVEL_DESCRIPTOR;\r | |
25 | \r | |
26 | // memory space covered by a first level descriptor\r | |
27 | #define ARM_PAGE_DESC_ENTRY_MVA_SIZE 0x00100000 // 1MB\r | |
28 | \r | |
29 | // number of first level descriptors to cover entire 32-bit memory space\r | |
30 | #define FIRST_LEVEL_ENTRY_COUNT (0xFFFFFFFF / ARM_PAGE_DESC_ENTRY_MVA_SIZE + 1)\r | |
31 | \r | |
32 | \r | |
33 | // page table 1st level descriptor entries\r | |
34 | #define ARM_PAGE_DESC_BASE_MASK 0xFFFFFC00\r | |
35 | #define ARM_PAGE_DESC_BASE_SHFIT 10\r | |
36 | #define ARM_PAGE_DESC_DOMAIN_MASK 0x000001E0\r | |
37 | #define ARM_PAGE_DESC_DOMAIN_SHIFT 5\r | |
38 | #define ARM_PAGE_DESC_NS 0x00000008\r | |
39 | \r | |
40 | #define ARM_FIRST_LEVEL_DESC_ALIGN 0x00004000 // 16KB\r | |
41 | \r | |
42 | // section 1st level desriptor entries\r | |
43 | #define ARM_SECTION_BASE_MASK 0xFFF00000\r | |
44 | #define ARM_SECTION_BASE_SHIFT 20\r | |
45 | #define ARM_SECTION_NS 0x00080000\r | |
46 | #define ARM_SECTION_nG 0x00020000\r | |
47 | #define ARM_SECTION_S 0x00010000\r | |
48 | #define ARM_SECTION_AP2 0x00008000\r | |
49 | #define ARM_SECTION_TEX_MASK 0x00007000\r | |
50 | #define ARM_SECTION_TEX_SHIFT 12\r | |
51 | #define ARM_SECTION_AP10_MASK 0x00000C00\r | |
52 | #define ARM_SECTION_AP10_SHIFT 10\r | |
53 | #define ARM_SECTION_DOMAIN_MASK 0x000001E0\r | |
54 | #define ARM_SECTION_DOMAIN_SHIFT 5\r | |
55 | #define ARM_SECTION_XN 0x00000010\r | |
56 | #define ARM_SECTION_C 0x00000008\r | |
57 | #define ARM_SECTION_B 0x00000004\r | |
58 | \r | |
59 | // section level AP[2:0] definitions\r | |
60 | #define ARM_SECTION_AP_NO_ACCESS 0 // AP[2:0] = 0\r | |
61 | #define ARM_SECTION_AP_READ_WRITE ARM_SECTION_AP10_MASK // AP[2:0] = 011\r | |
62 | #define ARM_SECTION_AP_READ_ONLY (ARM_SECTION_AP2 | ARM_SECTION_AP10_MASK) // AP[2:0] = 111\r | |
63 | \r | |
64 | // common 1st level descriptor fields\r | |
65 | #define ARM_DESC_TYPE_MASK 0x00000003\r | |
66 | \r | |
67 | // descriptor type values\r | |
68 | #define ARM_DESC_TYPE_FAULT 0x0\r | |
69 | #define ARM_DESC_TYPE_PAGE_TABLE 0x1\r | |
70 | #define ARM_DESC_TYPE_SECTION 0x2\r | |
71 | \r | |
72 | \r | |
73 | // Second Level Descriptors\r | |
74 | typedef UINT32 ARM_PAGE_TABLE_ENTRY;\r | |
75 | \r | |
76 | // small page 2nd level descriptor entries\r | |
77 | #define ARM_SMALL_PAGE_BASE_MASK 0xFFFFF000\r | |
78 | #define ARM_SMALL_PAGE_INDEX_MASK 0x000FF000\r | |
79 | #define ARM_SMALL_PAGE_BASE_SHIFT 12\r | |
80 | #define ARM_SMALL_PAGE_TEX_MASK 0x000001C0\r | |
81 | #define ARM_SMALL_PAGE_TEX_SHIFT 6\r | |
82 | #define ARM_SMALL_PAGE_XN 0x00000001\r | |
83 | \r | |
84 | // large page 2nd level descriptor entries\r | |
85 | #define ARM_LARGE_PAGE_BASE_MASK 0xFFFF0000\r | |
86 | #define ARM_LARGE_PAGE_BASE_SHIFT 16\r | |
87 | #define ARM_LARGE_PAGE_TEX_MASK 0x00007000\r | |
88 | #define ARM_LARGE_PAGE_TEX_SHIFT 12\r | |
89 | #define ARM_LARGE_PAGE_XN 0x00008000\r | |
90 | \r | |
91 | // common 2nd level desriptor fields\r | |
92 | #define ARM_PAGE_nG 0x00000800\r | |
93 | #define ARM_PAGE_S 0x00000400\r | |
94 | #define ARM_PAGE_AP2 0x00000200\r | |
95 | #define ARM_PAGE_AP10_MASK 0x00000030\r | |
96 | #define ARM_PAGE_AP10_SHIFT 4\r | |
97 | #define ARM_PAGE_C 0x00000008\r | |
98 | #define ARM_PAGE_B 0x00000004\r | |
99 | #define ARM_PAGE_DESC_TYPE_MASK 0x00000003\r | |
100 | \r | |
101 | // descriptor type values\r | |
102 | #define ARM_PAGE_TYPE_FAULT 0x0\r | |
103 | #define ARM_PAGE_TYPE_LARGE 0x1\r | |
104 | #define ARM_PAGE_TYPE_SMALL 0x2\r | |
105 | #define ARM_PAGE_TYPE_SMALL_XN 0x3\r | |
106 | \r | |
107 | #define SMALL_PAGE_TABLE_ENTRY_COUNT (ARM_PAGE_DESC_ENTRY_MVA_SIZE / EFI_PAGE_SIZE)\r | |
108 | \r | |
109 | \r | |
110 | // Translation Table Base 0 fields\r | |
111 | #define ARM_TTBR0_BASE_MASK 0xFFFFC000\r | |
112 | #define ARM_TTBR0_BASE_SHIFT 14\r | |
113 | #define ARM_TTRB0_NOS 0x00000020\r | |
114 | \r | |
115 | // define the combination of interesting attributes: cacheability and access permissions\r | |
116 | #define ARM_SECTION_CACHEABILITY_MASK ( ARM_SECTION_TEX_MASK | ARM_SECTION_C | ARM_SECTION_B )\r | |
117 | #define ARM_SECTION_RW_PERMISSIONS_MASK ( ARM_SECTION_AP2 | ARM_SECTION_AP10_MASK )\r | |
118 | #define ARM_DESCRIPTOR_ATTRIBUTES ( ARM_SECTION_CACHEABILITY_MASK | ARM_SECTION_RW_PERMISSIONS_MASK | ARM_SECTION_XN )\r | |
119 | \r | |
120 | // cacheability values for section entries\r | |
121 | #define ARM_SECTION_STRONGLY_ORDERED 0\r | |
122 | #define ARM_SECTION_SHAREABLE_DEVICE ARM_SECTION_B\r | |
123 | #define ARM_SECTION_WRITE_THROUGH ARM_SECTION_C\r | |
124 | #define ARM_SECTION_WRITE_BACK_NWA ( ARM_SECTION_C| ARM_SECTION_B )\r | |
125 | #define ARM_SECTION_NORMAL_UNCACHEABLE ( 0x1 << ARM_SECTION_TEX_SHIFT )\r | |
126 | #define ARM_SECTION_WRITE_BACK ( ( 0x1 << ARM_SECTION_TEX_SHIFT ) | ARM_SECTION_C | ARM_SECTION_B )\r | |
127 | #define ARM_SECTION_NONSHAREABLE_DEVICE ( 0x2 << ARM_SECTION_TEX_SHIFT )\r | |
128 | \r | |
129 | // permissions values for section entries\r | |
130 | #define ARM_SECTION_NO_ACCESS 0\r | |
131 | #define ARM_SECTION_PRIV_ACCESS_ONLY ( 0x1 << ARM_SECTION_AP10_SHIFT)\r | |
132 | #define ARM_SECTION_USER_READ_ONLY ( 0x2 << ARM_SECTION_AP10_SHIFT)\r | |
133 | #define ARM_SECTION_FULL_ACCESS ( 0x3 << ARM_SECTION_AP10_SHIFT)\r | |
134 | #define ARM_SECTION_PRIV_READ_ONLY ( ARM_SECTION_AP2 | (0x1 << ARM_SECTION_AP10_SHIFT) )\r | |
135 | #define ARM_SECTION_READ_ONLY_DEP ( ARM_SECTION_AP2 | (0x2 << ARM_SECTION_AP10_SHIFT) )\r | |
136 | #define ARM_SECTION_READ_ONLY ( ARM_SECTION_AP2 | (0x3 << ARM_SECTION_AP10_SHIFT) )\r | |
137 | \r | |
138 | \r | |
139 | \r | |
140 | EFI_STATUS \r | |
141 | SectionToGcdAttributes (\r | |
142 | IN UINT32 SectionAttributes,\r | |
143 | OUT UINT64 *GcdAttributes\r | |
144 | )\r | |
145 | {\r | |
146 | *GcdAttributes = 0;\r | |
147 | \r | |
148 | // determine cacheability attributes\r | |
149 | switch(SectionAttributes & ARM_SECTION_CACHEABILITY_MASK) {\r | |
150 | case ARM_SECTION_STRONGLY_ORDERED:\r | |
151 | *GcdAttributes |= EFI_MEMORY_UC;\r | |
152 | break;\r | |
153 | case ARM_SECTION_SHAREABLE_DEVICE:\r | |
154 | *GcdAttributes |= EFI_MEMORY_UC;\r | |
155 | break;\r | |
156 | case ARM_SECTION_WRITE_THROUGH:\r | |
157 | *GcdAttributes |= EFI_MEMORY_WT;\r | |
158 | break;\r | |
159 | case ARM_SECTION_WRITE_BACK_NWA:\r | |
160 | *GcdAttributes |= EFI_MEMORY_WB;\r | |
161 | break;\r | |
162 | case ARM_SECTION_NORMAL_UNCACHEABLE:\r | |
163 | *GcdAttributes |= EFI_MEMORY_WC;\r | |
164 | break;\r | |
165 | case ARM_SECTION_WRITE_BACK:\r | |
166 | *GcdAttributes |= EFI_MEMORY_WB;\r | |
167 | break;\r | |
168 | case ARM_SECTION_NONSHAREABLE_DEVICE:\r | |
169 | *GcdAttributes |= EFI_MEMORY_UC;\r | |
170 | break;\r | |
171 | default:\r | |
172 | return EFI_UNSUPPORTED;\r | |
173 | break;\r | |
174 | }\r | |
175 | \r | |
176 | // determine protection attributes\r | |
177 | switch(SectionAttributes & ARM_SECTION_RW_PERMISSIONS_MASK) {\r | |
178 | case ARM_SECTION_NO_ACCESS: // no read, no write\r | |
179 | *GcdAttributes |= EFI_MEMORY_WP | EFI_MEMORY_RP;\r | |
180 | break;\r | |
181 | \r | |
182 | case ARM_SECTION_PRIV_ACCESS_ONLY:\r | |
183 | case ARM_SECTION_FULL_ACCESS:\r | |
184 | // normal read/write access, do not add additional attributes\r | |
185 | break;\r | |
186 | \r | |
187 | // read only cases map to write-protect\r | |
188 | case ARM_SECTION_PRIV_READ_ONLY:\r | |
189 | case ARM_SECTION_READ_ONLY_DEP:\r | |
190 | case ARM_SECTION_READ_ONLY:\r | |
191 | *GcdAttributes |= EFI_MEMORY_WP;\r | |
192 | break;\r | |
193 | \r | |
194 | default:\r | |
195 | return EFI_UNSUPPORTED;\r | |
196 | break;\r | |
197 | }\r | |
198 | \r | |
199 | // now process eXectue Never attribute\r | |
200 | if ((SectionAttributes & ARM_SECTION_XN) != 0 ) {\r | |
201 | *GcdAttributes |= EFI_MEMORY_XP;\r | |
202 | }\r | |
203 | \r | |
204 | return EFI_SUCCESS;\r | |
205 | }\r | |
206 | \r | |
207 | \r | |
208 | \r | |
209 | EFI_STATUS\r | |
210 | SyncCacheConfig (\r | |
211 | IN EFI_CPU_ARCH_PROTOCOL *CpuProtocol\r | |
212 | )\r | |
213 | {\r | |
214 | EFI_STATUS Status;\r | |
215 | UINT32 i;\r | |
216 | UINT32 Descriptor;\r | |
217 | UINT32 SectionAttributes;\r | |
218 | EFI_PHYSICAL_ADDRESS NextRegionBase;\r | |
219 | UINT64 NextRegionLength;\r | |
220 | UINT64 GcdAttributes;\r | |
221 | UINT32 NextRegionAttributes = 0;\r | |
222 | volatile ARM_FIRST_LEVEL_DESCRIPTOR *FirstLevelTable;\r | |
223 | \r | |
224 | \r | |
225 | // This code assumes MMU is enabled and filed with section translations\r | |
226 | ASSERT (ArmMmuEnabled ());\r | |
227 | \r | |
228 | \r | |
229 | // The GCD implementation maintains its own copy of the state of memory space attributes. GCD needs\r | |
230 | // to know what the initial memory space attributes are. The CPU Arch. Protocol does not provide a\r | |
231 | // GetMemoryAttributes function for GCD to get this so we must resort to calling GCD (as if we were\r | |
232 | // a client) to update its copy of the attributes. This is bad architecture and should be replaced\r | |
233 | // with a way for GCD to query the CPU Arch. driver of the existing memory space attributes instead.\r | |
234 | \r | |
235 | // obtain page table base\r | |
236 | FirstLevelTable = (ARM_FIRST_LEVEL_DESCRIPTOR *)(ArmGetTranslationTableBaseAddress ());\r | |
237 | \r | |
238 | \r | |
239 | // iterate through each 1MB descriptor\r | |
240 | NextRegionBase = NextRegionLength = 0;\r | |
241 | for (i=0; i< FIRST_LEVEL_ENTRY_COUNT; i++) {\r | |
242 | \r | |
243 | // obtain existing descriptor\r | |
244 | Descriptor = FirstLevelTable[i];\r | |
245 | \r | |
246 | // extract attributes (cacheability and permissions)\r | |
247 | SectionAttributes = Descriptor & 0xDEC;\r | |
248 | \r | |
249 | // do we already have an existing region (or are we about to finish)?\r | |
250 | // Skip the first entry, and make sure we close on the last entry\r | |
251 | if ( (NextRegionLength > 0) || (i == (FIRST_LEVEL_ENTRY_COUNT-1)) ) {\r | |
252 | // attributes are changing, update attributes in GCD\r | |
253 | if (SectionAttributes != NextRegionAttributes) {\r | |
254 | \r | |
255 | // convert section entry attributes to GCD bitmask\r | |
256 | Status = SectionToGcdAttributes (NextRegionAttributes, &GcdAttributes);\r | |
257 | ASSERT_EFI_ERROR(Status);\r | |
258 | \r | |
259 | // update GCD with these changes (this will recurse into our own CpuSetMemoryAttributes below which is OK)\r | |
260 | Status = gDS->SetMemorySpaceAttributes (NextRegionBase, NextRegionLength, GcdAttributes);\r | |
261 | ASSERT_EFI_ERROR(Status);\r | |
262 | \r | |
263 | // start on a new region\r | |
264 | NextRegionLength = 0;\r | |
265 | NextRegionBase = Descriptor & ARM_SECTION_BASE_MASK;\r | |
266 | }\r | |
267 | }\r | |
268 | \r | |
269 | // starting a new region?\r | |
270 | if (NextRegionLength == 0) {\r | |
271 | NextRegionAttributes = SectionAttributes;\r | |
272 | }\r | |
273 | \r | |
274 | NextRegionLength += ARM_PAGE_DESC_ENTRY_MVA_SIZE;\r | |
275 | \r | |
276 | } // section entry loop\r | |
277 | \r | |
278 | return EFI_SUCCESS;\r | |
279 | }\r | |
280 | \r | |
281 | \r | |
282 | \r | |
283 | EFI_STATUS\r | |
284 | UpdatePageEntries (\r | |
285 | IN EFI_PHYSICAL_ADDRESS BaseAddress,\r | |
286 | IN UINT64 Length,\r | |
287 | IN UINT64 Attributes,\r | |
288 | IN EFI_PHYSICAL_ADDRESS VirtualMask\r | |
289 | )\r | |
290 | {\r | |
291 | EFI_STATUS Status;\r | |
292 | UINT32 EntryValue;\r | |
293 | UINT32 EntryMask;\r | |
294 | UINT32 FirstLevelIdx;\r | |
295 | UINT32 Offset;\r | |
296 | UINT32 NumPageEntries;\r | |
297 | UINT32 Descriptor;\r | |
298 | UINT32 p;\r | |
299 | UINT32 PageTableIndex;\r | |
300 | UINT32 PageTableEntry;\r | |
301 | \r | |
302 | volatile ARM_FIRST_LEVEL_DESCRIPTOR *FirstLevelTable;\r | |
303 | volatile ARM_PAGE_TABLE_ENTRY *PageTable;\r | |
304 | \r | |
305 | // EntryMask: bitmask of values to change (1 = change this value, 0 = leave alone)\r | |
306 | // EntryValue: values at bit positions specified by EntryMask\r | |
307 | \r | |
308 | // Although the PI spec is unclear on this the GCD guarantees that only\r | |
309 | // one Attribute bit is set at a time, so we can safely use a switch statement\r | |
310 | switch (Attributes) {\r | |
311 | case EFI_MEMORY_UC:\r | |
312 | // modify cacheability attributes\r | |
313 | EntryMask = ARM_SMALL_PAGE_TEX_MASK | ARM_PAGE_C | ARM_PAGE_B;\r | |
314 | // map to strongly ordered\r | |
315 | EntryValue = 0; // TEX[2:0] = 0, C=0, B=0\r | |
316 | break;\r | |
317 | \r | |
318 | case EFI_MEMORY_WC:\r | |
319 | // modify cacheability attributes\r | |
320 | EntryMask = ARM_SMALL_PAGE_TEX_MASK | ARM_PAGE_C | ARM_PAGE_B;\r | |
321 | // map to normal non-cachable\r | |
322 | EntryValue = (0x1 << ARM_SMALL_PAGE_TEX_SHIFT); // TEX [2:0]= 001 = 0x2, B=0, C=0\r | |
323 | break;\r | |
324 | \r | |
325 | case EFI_MEMORY_WT:\r | |
326 | // modify cacheability attributes\r | |
327 | EntryMask = ARM_SMALL_PAGE_TEX_MASK | ARM_PAGE_C | ARM_PAGE_B;\r | |
328 | // write through with no-allocate\r | |
329 | EntryValue = ARM_PAGE_C; // TEX [2:0] = 0, C=1, B=0\r | |
330 | break;\r | |
331 | \r | |
332 | case EFI_MEMORY_WB:\r | |
333 | // modify cacheability attributes\r | |
334 | EntryMask = ARM_SMALL_PAGE_TEX_MASK | ARM_PAGE_C | ARM_PAGE_B;\r | |
335 | // write back (with allocate)\r | |
336 | EntryValue = (0x1 << ARM_SMALL_PAGE_TEX_SHIFT) | ARM_PAGE_C | ARM_PAGE_B; // TEX [2:0] = 001, C=1, B=1\r | |
337 | break;\r | |
338 | \r | |
339 | case EFI_MEMORY_WP:\r | |
340 | case EFI_MEMORY_XP:\r | |
341 | case EFI_MEMORY_UCE:\r | |
342 | // cannot be implemented UEFI definition unclear for ARM\r | |
343 | // Cause a page fault if these ranges are accessed.\r | |
344 | EntryMask = 0x3;\r | |
345 | EntryValue = 0;\r | |
346 | DEBUG ((EFI_D_PAGE, "SetMemoryAttributes(): setting page %lx with unsupported attribute %x will page fault on access\n", BaseAddress, Attributes));\r | |
347 | break;\r | |
348 | \r | |
349 | default:\r | |
350 | return EFI_UNSUPPORTED;\r | |
351 | break;\r | |
352 | }\r | |
353 | \r | |
354 | // obtain page table base\r | |
355 | FirstLevelTable = (ARM_FIRST_LEVEL_DESCRIPTOR *)ArmGetTranslationTableBaseAddress ();\r | |
356 | \r | |
357 | // calculate number of 4KB page table entries to change\r | |
358 | NumPageEntries = Length/EFI_PAGE_SIZE;\r | |
359 | \r | |
360 | // iterate for the number of 4KB pages to change\r | |
361 | Offset = 0;\r | |
362 | for(p=0; p<NumPageEntries; p++) {\r | |
363 | // calculate index into first level translation table for page table value\r | |
364 | \r | |
365 | FirstLevelIdx = ((BaseAddress + Offset) & ARM_SECTION_BASE_MASK) >> ARM_SECTION_BASE_SHIFT;\r | |
366 | ASSERT (FirstLevelIdx < FIRST_LEVEL_ENTRY_COUNT);\r | |
367 | \r | |
368 | // read the descriptor from the first level page table\r | |
369 | Descriptor = FirstLevelTable[FirstLevelIdx];\r | |
370 | \r | |
371 | // does this descriptor need to be converted from section entry to 4K pages?\r | |
372 | if ((Descriptor & ARM_DESC_TYPE_MASK) == ARM_DESC_TYPE_SECTION ) {\r | |
373 | Status = ConvertSectionToPages (FirstLevelIdx << ARM_SECTION_BASE_SHIFT);\r | |
374 | if (EFI_ERROR(Status)) {\r | |
375 | // exit for loop\r | |
376 | break; \r | |
377 | } \r | |
378 | \r | |
379 | // re-read descriptor\r | |
380 | Descriptor = FirstLevelTable[FirstLevelIdx];\r | |
381 | }\r | |
382 | \r | |
383 | // obtain page table base address\r | |
384 | PageTable = (ARM_PAGE_TABLE_ENTRY *)(Descriptor & ARM_SMALL_PAGE_BASE_MASK);\r | |
385 | \r | |
386 | // calculate index into the page table\r | |
387 | PageTableIndex = ((BaseAddress + Offset) & ARM_SMALL_PAGE_INDEX_MASK) >> ARM_SMALL_PAGE_BASE_SHIFT;\r | |
388 | ASSERT(PageTableIndex < SMALL_PAGE_TABLE_ENTRY_COUNT);\r | |
389 | \r | |
390 | // get the entry\r | |
391 | PageTableEntry = PageTable[PageTableIndex];\r | |
392 | \r | |
393 | // mask off appropriate fields\r | |
394 | PageTableEntry &= ~EntryMask;\r | |
395 | \r | |
396 | // mask in new attributes and/or permissions\r | |
397 | PageTableEntry |= EntryValue;\r | |
398 | \r | |
399 | if (VirtualMask != 0) {\r | |
400 | // Make this virtual address point at a physical page\r | |
401 | PageTableEntry &= ~VirtualMask;\r | |
402 | }\r | |
403 | \r | |
404 | // update the entry\r | |
405 | PageTable[PageTableIndex] = PageTableEntry; \r | |
406 | \r | |
407 | \r | |
408 | Status = EFI_SUCCESS;\r | |
409 | Offset += EFI_PAGE_SIZE;\r | |
410 | \r | |
411 | } // end first level translation table loop\r | |
412 | \r | |
413 | return Status;\r | |
414 | }\r | |
415 | \r | |
416 | \r | |
417 | \r | |
418 | EFI_STATUS\r | |
419 | UpdateSectionEntries (\r | |
420 | IN EFI_PHYSICAL_ADDRESS BaseAddress,\r | |
421 | IN UINT64 Length,\r | |
422 | IN UINT64 Attributes,\r | |
423 | IN EFI_PHYSICAL_ADDRESS VirtualMask\r | |
424 | )\r | |
425 | {\r | |
426 | EFI_STATUS Status = EFI_SUCCESS;\r | |
427 | UINT32 EntryMask;\r | |
428 | UINT32 EntryValue;\r | |
429 | UINT32 FirstLevelIdx;\r | |
430 | UINT32 NumSections;\r | |
431 | UINT32 i;\r | |
432 | UINT32 Descriptor;\r | |
433 | \r | |
434 | volatile ARM_FIRST_LEVEL_DESCRIPTOR *FirstLevelTable;\r | |
435 | \r | |
436 | // EntryMask: bitmask of values to change (1 = change this value, 0 = leave alone)\r | |
437 | // EntryValue: values at bit positions specified by EntryMask\r | |
438 | \r | |
439 | // Although the PI spec is unclear on this the GCD guarantees that only\r | |
440 | // one Attribute bit is set at a time, so we can safely use a switch statement\r | |
441 | switch(Attributes) {\r | |
442 | case EFI_MEMORY_UC:\r | |
443 | // modify cacheability attributes\r | |
444 | EntryMask = ARM_SECTION_TEX_MASK | ARM_SECTION_C | ARM_SECTION_B;\r | |
445 | // map to strongly ordered\r | |
446 | EntryValue = 0; // TEX[2:0] = 0, C=0, B=0\r | |
447 | break;\r | |
448 | \r | |
449 | case EFI_MEMORY_WC:\r | |
450 | // modify cacheability attributes\r | |
451 | EntryMask = ARM_SECTION_TEX_MASK | ARM_SECTION_C | ARM_SECTION_B;\r | |
452 | // map to normal non-cachable\r | |
453 | EntryValue = (0x1 << ARM_SECTION_TEX_SHIFT); // TEX [2:0]= 001 = 0x2, B=0, C=0\r | |
454 | break;\r | |
455 | \r | |
456 | case EFI_MEMORY_WT:\r | |
457 | // modify cacheability attributes\r | |
458 | EntryMask = ARM_SECTION_TEX_MASK | ARM_SECTION_C | ARM_SECTION_B;\r | |
459 | // write through with no-allocate\r | |
460 | EntryValue = ARM_SECTION_C; // TEX [2:0] = 0, C=1, B=0\r | |
461 | break;\r | |
462 | \r | |
463 | case EFI_MEMORY_WB:\r | |
464 | // modify cacheability attributes\r | |
465 | EntryMask = ARM_SECTION_TEX_MASK | ARM_SECTION_C | ARM_SECTION_B;\r | |
466 | // write back (with allocate)\r | |
467 | EntryValue = (0x1 << ARM_SECTION_TEX_SHIFT) | ARM_SECTION_C | ARM_SECTION_B; // TEX [2:0] = 001, C=1, B=1\r | |
468 | break;\r | |
469 | \r | |
470 | case EFI_MEMORY_WP:\r | |
471 | case EFI_MEMORY_XP:\r | |
472 | case EFI_MEMORY_RP:\r | |
473 | case EFI_MEMORY_UCE:\r | |
474 | // cannot be implemented UEFI definition unclear for ARM\r | |
475 | // Cause a page fault if these ranges are accessed.\r | |
476 | EntryMask = 0x3;\r | |
477 | EntryValue = 0;\r | |
478 | DEBUG ((EFI_D_PAGE, "SetMemoryAttributes(): setting section %lx with unsupported attribute %x will page fault on access\n", BaseAddress, Attributes));\r | |
479 | break;\r | |
480 | \r | |
481 | \r | |
482 | default:\r | |
483 | return EFI_UNSUPPORTED;\r | |
484 | break;\r | |
485 | }\r | |
486 | \r | |
487 | // obtain page table base\r | |
488 | FirstLevelTable = (ARM_FIRST_LEVEL_DESCRIPTOR *)ArmGetTranslationTableBaseAddress ();\r | |
489 | \r | |
490 | // calculate index into first level translation table for start of modification\r | |
491 | FirstLevelIdx = (BaseAddress & ARM_SECTION_BASE_MASK) >> ARM_SECTION_BASE_SHIFT;\r | |
492 | ASSERT (FirstLevelIdx < FIRST_LEVEL_ENTRY_COUNT);\r | |
493 | \r | |
494 | // calculate number of 1MB first level entries this applies to\r | |
495 | NumSections = Length / ARM_PAGE_DESC_ENTRY_MVA_SIZE;\r | |
496 | \r | |
497 | // iterate through each descriptor\r | |
498 | for(i=0; i<NumSections; i++) {\r | |
499 | Descriptor = FirstLevelTable[FirstLevelIdx + i];\r | |
500 | \r | |
501 | // has this descriptor already been coverted to pages?\r | |
502 | if ((Descriptor & ARM_DESC_TYPE_MASK) == ARM_DESC_TYPE_PAGE_TABLE ) {\r | |
503 | // forward this 1MB range to page table function instead\r | |
504 | Status = UpdatePageEntries ((FirstLevelIdx + i) << ARM_SECTION_BASE_SHIFT, ARM_PAGE_DESC_ENTRY_MVA_SIZE, Attributes, VirtualMask);\r | |
505 | } else {\r | |
506 | // still a section entry\r | |
507 | \r | |
508 | // mask off appropriate fields\r | |
509 | Descriptor &= ~EntryMask;\r | |
510 | \r | |
511 | // mask in new attributes and/or permissions\r | |
512 | Descriptor |= EntryValue;\r | |
513 | if (VirtualMask != 0) {\r | |
514 | Descriptor &= ~VirtualMask;\r | |
515 | }\r | |
516 | \r | |
517 | FirstLevelTable[FirstLevelIdx + i] = Descriptor;\r | |
518 | \r | |
519 | Status = EFI_SUCCESS;\r | |
520 | }\r | |
521 | }\r | |
522 | \r | |
523 | return Status;\r | |
524 | }\r | |
525 | \r | |
526 | EFI_STATUS \r | |
527 | ConvertSectionToPages (\r | |
528 | IN EFI_PHYSICAL_ADDRESS BaseAddress\r | |
529 | )\r | |
530 | {\r | |
531 | EFI_STATUS Status;\r | |
532 | EFI_PHYSICAL_ADDRESS PageTableAddr;\r | |
533 | UINT32 FirstLevelIdx;\r | |
534 | UINT32 SectionDescriptor;\r | |
535 | UINT32 PageTableDescriptor;\r | |
536 | UINT32 PageDescriptor;\r | |
537 | UINT32 i;\r | |
538 | \r | |
539 | volatile ARM_FIRST_LEVEL_DESCRIPTOR *FirstLevelTable;\r | |
540 | volatile ARM_PAGE_TABLE_ENTRY *PageTable;\r | |
541 | \r | |
542 | DEBUG ((EFI_D_PAGE, "Converting section at 0x%x to pages\n", (UINTN)BaseAddress));\r | |
543 | \r | |
544 | // obtain page table base\r | |
545 | FirstLevelTable = (ARM_FIRST_LEVEL_DESCRIPTOR *)ArmGetTranslationTableBaseAddress ();\r | |
546 | \r | |
547 | // calculate index into first level translation table for start of modification\r | |
548 | FirstLevelIdx = (BaseAddress & ARM_SECTION_BASE_MASK) >> ARM_SECTION_BASE_SHIFT;\r | |
549 | ASSERT(FirstLevelIdx < FIRST_LEVEL_ENTRY_COUNT);\r | |
550 | \r | |
551 | // get section attributes and convert to page attributes\r | |
552 | SectionDescriptor = FirstLevelTable[FirstLevelIdx];\r | |
553 | PageDescriptor = ARM_PAGE_TYPE_SMALL;\r | |
554 | PageDescriptor |= ((SectionDescriptor & ARM_SECTION_TEX_MASK) >> ARM_SECTION_TEX_SHIFT) << ARM_SMALL_PAGE_TEX_SHIFT;\r | |
555 | if ((SectionDescriptor & ARM_SECTION_B) != 0) {\r | |
556 | PageDescriptor |= ARM_PAGE_B;\r | |
557 | }\r | |
558 | if ((SectionDescriptor & ARM_SECTION_C) != 0) {\r | |
559 | PageDescriptor |= ARM_PAGE_C;\r | |
560 | }\r | |
561 | PageDescriptor |= ((SectionDescriptor & ARM_SECTION_AP10_MASK) >> ARM_SECTION_AP10_SHIFT) << ARM_PAGE_AP10_SHIFT;\r | |
562 | if ((SectionDescriptor & ARM_SECTION_AP2) != 0) {\r | |
563 | PageDescriptor |= ARM_PAGE_AP2;\r | |
564 | }\r | |
565 | if ((SectionDescriptor & ARM_SECTION_XN) != 0) {\r | |
566 | PageDescriptor |= ARM_PAGE_TYPE_SMALL_XN;\r | |
567 | }\r | |
568 | if ((SectionDescriptor & ARM_SECTION_nG) != 0) {\r | |
569 | PageDescriptor |= ARM_PAGE_nG;\r | |
570 | }\r | |
571 | if ((SectionDescriptor & ARM_SECTION_S) != 0) {\r | |
572 | PageDescriptor |= ARM_PAGE_S;\r | |
573 | }\r | |
574 | \r | |
575 | // allocate a page table for the 4KB entries (we use up a full page even though we only need 1KB)\r | |
576 | Status = gBS->AllocatePages (AllocateAnyPages, EfiBootServicesData, 1, &PageTableAddr);\r | |
577 | if (EFI_ERROR(Status)) {\r | |
578 | return Status;\r | |
579 | }\r | |
580 | \r | |
581 | PageTable = (volatile ARM_PAGE_TABLE_ENTRY *)(UINTN)PageTableAddr;\r | |
582 | \r | |
583 | // write the page table entries out\r | |
584 | for (i=0; i<(ARM_PAGE_DESC_ENTRY_MVA_SIZE/EFI_PAGE_SIZE); i++) {\r | |
585 | PageTable[i] = ((BaseAddress + (i << 12)) & ARM_SMALL_PAGE_BASE_MASK) | PageDescriptor;\r | |
586 | }\r | |
587 | \r | |
588 | // flush d-cache so descriptors make it back to uncached memory for subsequent table walks\r | |
589 | // TODO: change to use only PageTable base and length\r | |
590 | // ArmInvalidateDataCache ();\r | |
591 | InvalidateDataCacheRange ((VOID *)&PageTableAddr, EFI_PAGE_SIZE);\r | |
592 | \r | |
593 | // formulate page table entry, Domain=0, NS=0\r | |
594 | PageTableDescriptor = (((UINTN)PageTableAddr) & ARM_PAGE_DESC_BASE_MASK) | ARM_DESC_TYPE_PAGE_TABLE;\r | |
595 | \r | |
596 | // write the page table entry out, repalcing section entry\r | |
597 | FirstLevelTable[FirstLevelIdx] = PageTableDescriptor;\r | |
598 | \r | |
599 | return EFI_SUCCESS;\r | |
600 | }\r | |
601 | \r | |
602 | \r | |
603 | \r | |
604 | EFI_STATUS\r | |
605 | SetMemoryAttributes (\r | |
606 | IN EFI_PHYSICAL_ADDRESS BaseAddress,\r | |
607 | IN UINT64 Length,\r | |
608 | IN UINT64 Attributes,\r | |
609 | IN EFI_PHYSICAL_ADDRESS VirtualMask\r | |
610 | )\r | |
611 | {\r | |
612 | EFI_STATUS Status;\r | |
613 | \r | |
614 | if(((BaseAddress & 0xFFFFF) == 0) && ((Length & 0xFFFFF) == 0)) {\r | |
615 | // is the base and length a multiple of 1 MB?\r | |
616 | DEBUG ((EFI_D_PAGE, "SetMemoryAttributes(): MMU section 0x%x length 0x%x to %lx\n", (UINTN)BaseAddress, (UINTN)Length, Attributes));\r | |
617 | Status = UpdateSectionEntries (BaseAddress, Length, Attributes, VirtualMask);\r | |
618 | } else {\r | |
619 | // base and/or length is not a multiple of 1 MB\r | |
620 | DEBUG ((EFI_D_PAGE, "SetMemoryAttributes(): MMU page 0x%x length 0x%x to %lx\n", (UINTN)BaseAddress, (UINTN)Length, Attributes));\r | |
621 | Status = UpdatePageEntries (BaseAddress, Length, Attributes, VirtualMask);\r | |
622 | }\r | |
623 | \r | |
624 | // flush d-cache so descriptors make it back to uncached memory for subsequent table walks\r | |
625 | // flush and invalidate pages\r | |
626 | ArmCleanInvalidateDataCache ();\r | |
627 | \r | |
628 | ArmInvalidateInstructionCache ();\r | |
629 | \r | |
630 | // invalidate all TLB entries so changes are synced\r | |
631 | ArmInvalidateTlb (); \r | |
632 | \r | |
633 | return Status;\r | |
634 | }\r | |
635 | \r | |
636 | \r | |
637 | /**\r | |
638 | This function modifies the attributes for the memory region specified by BaseAddress and\r | |
639 | Length from their current attributes to the attributes specified by Attributes.\r | |
640 | \r | |
641 | @param This The EFI_CPU_ARCH_PROTOCOL instance.\r | |
642 | @param BaseAddress The physical address that is the start address of a memory region.\r | |
643 | @param Length The size in bytes of the memory region.\r | |
644 | @param Attributes The bit mask of attributes to set for the memory region.\r | |
645 | \r | |
646 | @retval EFI_SUCCESS The attributes were set for the memory region.\r | |
647 | @retval EFI_ACCESS_DENIED The attributes for the memory resource range specified by\r | |
648 | BaseAddress and Length cannot be modified.\r | |
649 | @retval EFI_INVALID_PARAMETER Length is zero.\r | |
650 | @retval EFI_OUT_OF_RESOURCES There are not enough system resources to modify the attributes of\r | |
651 | the memory resource range.\r | |
652 | @retval EFI_UNSUPPORTED The processor does not support one or more bytes of the memory\r | |
653 | resource range specified by BaseAddress and Length.\r | |
654 | The bit mask of attributes is not support for the memory resource\r | |
655 | range specified by BaseAddress and Length.\r | |
656 | \r | |
657 | **/\r | |
658 | EFI_STATUS\r | |
659 | EFIAPI\r | |
660 | CpuSetMemoryAttributes (\r | |
661 | IN EFI_CPU_ARCH_PROTOCOL *This,\r | |
662 | IN EFI_PHYSICAL_ADDRESS BaseAddress,\r | |
663 | IN UINT64 Length,\r | |
664 | IN UINT64 Attributes\r | |
665 | )\r | |
666 | {\r | |
667 | if ( ((BaseAddress & (EFI_PAGE_SIZE-1)) != 0) || ((Length & (EFI_PAGE_SIZE-1)) != 0)){\r | |
668 | // minimum granularity is EFI_PAGE_SIZE (4KB on ARM)\r | |
669 | return EFI_UNSUPPORTED;\r | |
670 | }\r | |
671 | \r | |
672 | return SetMemoryAttributes (BaseAddress, Length, Attributes, 0);\r | |
673 | }\r | |
674 | \r | |
675 | \r | |
676 | \r | |
677 | //\r | |
678 | // Add a new protocol to support \r | |
679 | //\r | |
680 | \r | |
681 | EFI_STATUS\r | |
682 | EFIAPI\r | |
683 | CpuConvertPagesToUncachedVirtualAddress (\r | |
684 | IN VIRTUAL_UNCACHED_PAGES_PROTOCOL *This,\r | |
685 | IN EFI_PHYSICAL_ADDRESS Address,\r | |
686 | IN UINTN Length,\r | |
687 | IN EFI_PHYSICAL_ADDRESS VirtualMask,\r | |
688 | OUT UINT64 *Attributes OPTIONAL\r | |
689 | )\r | |
690 | {\r | |
691 | EFI_STATUS Status;\r | |
692 | EFI_GCD_MEMORY_SPACE_DESCRIPTOR GcdDescriptor;\r | |
693 | \r | |
694 | \r | |
695 | if (Attributes != NULL) {\r | |
696 | Status = gDS->GetMemorySpaceDescriptor (Address, &GcdDescriptor);\r | |
697 | if (!EFI_ERROR (Status)) {\r | |
698 | *Attributes = GcdDescriptor.Attributes;\r | |
699 | }\r | |
700 | }\r | |
701 | \r | |
702 | //\r | |
703 | // Make this address range page fault if accessed. If it is a DMA buffer than this would \r | |
704 | // be the PCI address. Code should always use the CPU address, and we will or in VirtualMask\r | |
705 | // to that address. \r | |
706 | //\r | |
707 | Status = SetMemoryAttributes (Address, Length, EFI_MEMORY_XP, 0);\r | |
708 | if (!EFI_ERROR (Status)) {\r | |
709 | Status = SetMemoryAttributes (Address | VirtualMask, Length, EFI_MEMORY_UC, VirtualMask);\r | |
710 | }\r | |
711 | \r | |
712 | return Status;\r | |
713 | }\r | |
714 | \r | |
715 | \r | |
716 | EFI_STATUS\r | |
717 | EFIAPI\r | |
718 | CpuFreeConvertedPages (\r | |
719 | IN VIRTUAL_UNCACHED_PAGES_PROTOCOL *This,\r | |
720 | IN EFI_PHYSICAL_ADDRESS Address,\r | |
721 | IN UINTN Length,\r | |
722 | IN EFI_PHYSICAL_ADDRESS VirtualMask,\r | |
723 | IN UINT64 Attributes\r | |
724 | )\r | |
725 | {\r | |
726 | EFI_STATUS Status;\r | |
727 | \r | |
728 | //\r | |
729 | // Unmap the alaised Address\r | |
730 | //\r | |
731 | Status = SetMemoryAttributes (Address | VirtualMask, Length, EFI_MEMORY_XP, 0);\r | |
732 | if (!EFI_ERROR (Status)) {\r | |
733 | //\r | |
734 | // Restore atttributes\r | |
735 | //\r | |
736 | Status = SetMemoryAttributes (Address, Length, Attributes, 0);\r | |
737 | }\r | |
738 | \r | |
739 | return Status;\r | |
740 | }\r | |
741 | \r | |
742 | \r | |
743 | VIRTUAL_UNCACHED_PAGES_PROTOCOL gVirtualUncachedPages = {\r | |
744 | CpuConvertPagesToUncachedVirtualAddress,\r | |
745 | CpuFreeConvertedPages\r | |
746 | };\r | |
747 | \r | |
748 | \r | |
749 | \r | |
750 | \r |