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aeb61534 A |
1 | /*++\r |
2 | \r | |
d6ebcab7 HT |
3 | Copyright (c) 2009, Hewlett-Packard Company. All rights reserved.<BR>\r |
4 | Portions copyright (c) 2010, Apple Inc. All rights reserved.<BR>\r | |
aeb61534 | 5 | \r |
d6ebcab7 | 6 | This program and the accompanying materials \r |
aeb61534 A |
7 | are licensed and made available under the terms and conditions of the BSD License \r |
8 | which accompanies this distribution. The full text of the license may be found at \r | |
9 | http://opensource.org/licenses/bsd-license.php \r | |
10 | \r | |
11 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r | |
12 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r | |
13 | \r | |
14 | \r | |
15 | --*/\r | |
16 | \r | |
17 | #include "CpuDxe.h"\r | |
aeb61534 A |
18 | \r |
19 | // First Level Descriptors\r | |
20 | typedef UINT32 ARM_FIRST_LEVEL_DESCRIPTOR;\r | |
21 | \r | |
aeb61534 A |
22 | // Second Level Descriptors\r |
23 | typedef UINT32 ARM_PAGE_TABLE_ENTRY;\r | |
24 | \r | |
aeb61534 A |
25 | EFI_STATUS \r |
26 | SectionToGcdAttributes (\r | |
27 | IN UINT32 SectionAttributes,\r | |
28 | OUT UINT64 *GcdAttributes\r | |
29 | )\r | |
30 | {\r | |
31 | *GcdAttributes = 0;\r | |
32 | \r | |
33 | // determine cacheability attributes\r | |
1bfda055 | 34 | switch(SectionAttributes & TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK) {\r |
35 | case TT_DESCRIPTOR_SECTION_CACHE_POLICY_STRONGLY_ORDERED:\r | |
aeb61534 A |
36 | *GcdAttributes |= EFI_MEMORY_UC;\r |
37 | break;\r | |
1bfda055 | 38 | case TT_DESCRIPTOR_SECTION_CACHE_POLICY_SHAREABLE_DEVICE:\r |
aeb61534 A |
39 | *GcdAttributes |= EFI_MEMORY_UC;\r |
40 | break;\r | |
1bfda055 | 41 | case TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_THROUGH_NO_ALLOC:\r |
aeb61534 A |
42 | *GcdAttributes |= EFI_MEMORY_WT;\r |
43 | break;\r | |
1bfda055 | 44 | case TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_BACK_NO_ALLOC:\r |
aeb61534 A |
45 | *GcdAttributes |= EFI_MEMORY_WB;\r |
46 | break;\r | |
1bfda055 | 47 | case TT_DESCRIPTOR_SECTION_CACHE_POLICY_NON_CACHEABLE:\r |
aeb61534 A |
48 | *GcdAttributes |= EFI_MEMORY_WC;\r |
49 | break;\r | |
1bfda055 | 50 | case TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_BACK_ALLOC:\r |
aeb61534 A |
51 | *GcdAttributes |= EFI_MEMORY_WB;\r |
52 | break;\r | |
1bfda055 | 53 | case TT_DESCRIPTOR_SECTION_CACHE_POLICY_NON_SHAREABLE_DEVICE:\r |
aeb61534 A |
54 | *GcdAttributes |= EFI_MEMORY_UC;\r |
55 | break;\r | |
56 | default:\r | |
57 | return EFI_UNSUPPORTED;\r | |
aeb61534 | 58 | }\r |
1bfda055 | 59 | \r |
aeb61534 | 60 | // determine protection attributes\r |
1bfda055 | 61 | switch(SectionAttributes & TT_DESCRIPTOR_SECTION_AP_MASK) {\r |
62 | case TT_DESCRIPTOR_SECTION_AP_NO_NO: // no read, no write\r | |
f659880b | 63 | //*GcdAttributes |= EFI_MEMORY_WP | EFI_MEMORY_RP;\r |
aeb61534 A |
64 | break;\r |
65 | \r | |
1bfda055 | 66 | case TT_DESCRIPTOR_SECTION_AP_RW_NO:\r |
67 | case TT_DESCRIPTOR_SECTION_AP_RW_RW:\r | |
aeb61534 A |
68 | // normal read/write access, do not add additional attributes\r |
69 | break;\r | |
70 | \r | |
71 | // read only cases map to write-protect\r | |
1bfda055 | 72 | case TT_DESCRIPTOR_SECTION_AP_RO_NO:\r |
73 | case TT_DESCRIPTOR_SECTION_AP_RO_RO:\r | |
aeb61534 A |
74 | *GcdAttributes |= EFI_MEMORY_WP;\r |
75 | break;\r | |
76 | \r | |
77 | default:\r | |
78 | return EFI_UNSUPPORTED;\r | |
aeb61534 A |
79 | }\r |
80 | \r | |
81 | // now process eXectue Never attribute\r | |
1bfda055 | 82 | if ((SectionAttributes & TT_DESCRIPTOR_SECTION_XN_MASK) != 0 ) {\r |
aeb61534 A |
83 | *GcdAttributes |= EFI_MEMORY_XP;\r |
84 | }\r | |
85 | \r | |
86 | return EFI_SUCCESS;\r | |
87 | }\r | |
88 | \r | |
2cf4b608 | 89 | EFI_STATUS\r |
90 | PageToGcdAttributes (\r | |
91 | IN UINT32 PageAttributes,\r | |
92 | OUT UINT64 *GcdAttributes\r | |
93 | )\r | |
94 | {\r | |
95 | *GcdAttributes = 0;\r | |
96 | \r | |
97 | // determine cacheability attributes\r | |
98 | switch(PageAttributes & TT_DESCRIPTOR_PAGE_CACHE_POLICY_MASK) {\r | |
99 | case TT_DESCRIPTOR_PAGE_CACHE_POLICY_STRONGLY_ORDERED:\r | |
100 | *GcdAttributes |= EFI_MEMORY_UC;\r | |
101 | break;\r | |
102 | case TT_DESCRIPTOR_PAGE_CACHE_POLICY_SHAREABLE_DEVICE:\r | |
103 | *GcdAttributes |= EFI_MEMORY_UC;\r | |
104 | break;\r | |
105 | case TT_DESCRIPTOR_PAGE_CACHE_POLICY_WRITE_THROUGH_NO_ALLOC:\r | |
106 | *GcdAttributes |= EFI_MEMORY_WT;\r | |
107 | break;\r | |
108 | case TT_DESCRIPTOR_PAGE_CACHE_POLICY_WRITE_BACK_NO_ALLOC:\r | |
109 | *GcdAttributes |= EFI_MEMORY_WB;\r | |
110 | break;\r | |
111 | case TT_DESCRIPTOR_PAGE_CACHE_POLICY_NON_CACHEABLE:\r | |
112 | *GcdAttributes |= EFI_MEMORY_WC;\r | |
113 | break;\r | |
114 | case TT_DESCRIPTOR_PAGE_CACHE_POLICY_WRITE_BACK_ALLOC:\r | |
115 | *GcdAttributes |= EFI_MEMORY_WB;\r | |
116 | break;\r | |
117 | case TT_DESCRIPTOR_PAGE_CACHE_POLICY_NON_SHAREABLE_DEVICE:\r | |
118 | *GcdAttributes |= EFI_MEMORY_UC;\r | |
119 | break;\r | |
120 | default:\r | |
121 | return EFI_UNSUPPORTED;\r | |
122 | }\r | |
123 | \r | |
124 | // determine protection attributes\r | |
125 | switch(PageAttributes & TT_DESCRIPTOR_PAGE_AP_MASK) {\r | |
126 | case TT_DESCRIPTOR_PAGE_AP_NO_NO: // no read, no write\r | |
127 | //*GcdAttributes |= EFI_MEMORY_WP | EFI_MEMORY_RP;\r | |
128 | break;\r | |
129 | \r | |
130 | case TT_DESCRIPTOR_PAGE_AP_RW_NO:\r | |
131 | case TT_DESCRIPTOR_PAGE_AP_RW_RW:\r | |
132 | // normal read/write access, do not add additional attributes\r | |
133 | break;\r | |
134 | \r | |
135 | // read only cases map to write-protect\r | |
136 | case TT_DESCRIPTOR_PAGE_AP_RO_NO:\r | |
137 | case TT_DESCRIPTOR_PAGE_AP_RO_RO:\r | |
138 | *GcdAttributes |= EFI_MEMORY_WP;\r | |
139 | break;\r | |
140 | \r | |
141 | default:\r | |
142 | return EFI_UNSUPPORTED;\r | |
143 | }\r | |
144 | \r | |
145 | // now process eXectue Never attribute\r | |
146 | if ((PageAttributes & TT_DESCRIPTOR_PAGE_XN_MASK) != 0 ) {\r | |
147 | *GcdAttributes |= EFI_MEMORY_XP;\r | |
148 | }\r | |
149 | \r | |
150 | return EFI_SUCCESS;\r | |
151 | }\r | |
152 | \r | |
f659880b A |
153 | /**\r |
154 | Searches memory descriptors covered by given memory range.\r | |
155 | \r | |
156 | This function searches into the Gcd Memory Space for descriptors\r | |
157 | (from StartIndex to EndIndex) that contains the memory range\r | |
158 | specified by BaseAddress and Length.\r | |
159 | \r | |
160 | @param MemorySpaceMap Gcd Memory Space Map as array.\r | |
161 | @param NumberOfDescriptors Number of descriptors in map.\r | |
162 | @param BaseAddress BaseAddress for the requested range.\r | |
163 | @param Length Length for the requested range.\r | |
164 | @param StartIndex Start index into the Gcd Memory Space Map.\r | |
165 | @param EndIndex End index into the Gcd Memory Space Map.\r | |
166 | \r | |
167 | @retval EFI_SUCCESS Search successfully.\r | |
168 | @retval EFI_NOT_FOUND The requested descriptors does not exist.\r | |
169 | \r | |
170 | **/\r | |
171 | EFI_STATUS\r | |
172 | SearchGcdMemorySpaces (\r | |
173 | IN EFI_GCD_MEMORY_SPACE_DESCRIPTOR *MemorySpaceMap,\r | |
174 | IN UINTN NumberOfDescriptors,\r | |
175 | IN EFI_PHYSICAL_ADDRESS BaseAddress,\r | |
176 | IN UINT64 Length,\r | |
177 | OUT UINTN *StartIndex,\r | |
178 | OUT UINTN *EndIndex\r | |
179 | )\r | |
180 | {\r | |
181 | UINTN Index;\r | |
182 | \r | |
183 | *StartIndex = 0;\r | |
184 | *EndIndex = 0;\r | |
185 | for (Index = 0; Index < NumberOfDescriptors; Index++) {\r | |
186 | if (BaseAddress >= MemorySpaceMap[Index].BaseAddress &&\r | |
187 | BaseAddress < MemorySpaceMap[Index].BaseAddress + MemorySpaceMap[Index].Length) {\r | |
188 | *StartIndex = Index;\r | |
189 | }\r | |
190 | if (BaseAddress + Length - 1 >= MemorySpaceMap[Index].BaseAddress &&\r | |
191 | BaseAddress + Length - 1 < MemorySpaceMap[Index].BaseAddress + MemorySpaceMap[Index].Length) {\r | |
192 | *EndIndex = Index;\r | |
193 | return EFI_SUCCESS;\r | |
194 | }\r | |
195 | }\r | |
196 | return EFI_NOT_FOUND;\r | |
197 | }\r | |
198 | \r | |
199 | \r | |
200 | /**\r | |
201 | Sets the attributes for a specified range in Gcd Memory Space Map.\r | |
202 | \r | |
203 | This function sets the attributes for a specified range in\r | |
204 | Gcd Memory Space Map.\r | |
205 | \r | |
206 | @param MemorySpaceMap Gcd Memory Space Map as array\r | |
207 | @param NumberOfDescriptors Number of descriptors in map\r | |
208 | @param BaseAddress BaseAddress for the range\r | |
209 | @param Length Length for the range\r | |
210 | @param Attributes Attributes to set\r | |
211 | \r | |
212 | @retval EFI_SUCCESS Memory attributes set successfully\r | |
213 | @retval EFI_NOT_FOUND The specified range does not exist in Gcd Memory Space\r | |
214 | \r | |
215 | **/\r | |
216 | EFI_STATUS\r | |
217 | SetGcdMemorySpaceAttributes (\r | |
218 | IN EFI_GCD_MEMORY_SPACE_DESCRIPTOR *MemorySpaceMap,\r | |
219 | IN UINTN NumberOfDescriptors,\r | |
220 | IN EFI_PHYSICAL_ADDRESS BaseAddress,\r | |
221 | IN UINT64 Length,\r | |
222 | IN UINT64 Attributes\r | |
223 | )\r | |
224 | {\r | |
225 | EFI_STATUS Status;\r | |
226 | UINTN Index;\r | |
227 | UINTN StartIndex;\r | |
228 | UINTN EndIndex;\r | |
229 | EFI_PHYSICAL_ADDRESS RegionStart;\r | |
230 | UINT64 RegionLength;\r | |
231 | \r | |
232 | //\r | |
233 | // Get all memory descriptors covered by the memory range\r | |
234 | //\r | |
235 | Status = SearchGcdMemorySpaces (\r | |
236 | MemorySpaceMap,\r | |
237 | NumberOfDescriptors,\r | |
238 | BaseAddress,\r | |
239 | Length,\r | |
240 | &StartIndex,\r | |
241 | &EndIndex\r | |
242 | );\r | |
243 | if (EFI_ERROR (Status)) {\r | |
244 | return Status;\r | |
245 | }\r | |
246 | \r | |
247 | //\r | |
248 | // Go through all related descriptors and set attributes accordingly\r | |
249 | //\r | |
250 | for (Index = StartIndex; Index <= EndIndex; Index++) {\r | |
251 | if (MemorySpaceMap[Index].GcdMemoryType == EfiGcdMemoryTypeNonExistent) {\r | |
252 | continue;\r | |
253 | }\r | |
254 | //\r | |
255 | // Calculate the start and end address of the overlapping range\r | |
256 | //\r | |
257 | if (BaseAddress >= MemorySpaceMap[Index].BaseAddress) {\r | |
258 | RegionStart = BaseAddress;\r | |
259 | } else {\r | |
260 | RegionStart = MemorySpaceMap[Index].BaseAddress;\r | |
261 | }\r | |
262 | if (BaseAddress + Length - 1 < MemorySpaceMap[Index].BaseAddress + MemorySpaceMap[Index].Length) {\r | |
263 | RegionLength = BaseAddress + Length - RegionStart;\r | |
264 | } else {\r | |
265 | RegionLength = MemorySpaceMap[Index].BaseAddress + MemorySpaceMap[Index].Length - RegionStart;\r | |
266 | }\r | |
267 | //\r | |
268 | // Set memory attributes according to MTRR attribute and the original attribute of descriptor\r | |
269 | //\r | |
270 | gDS->SetMemorySpaceAttributes (\r | |
271 | RegionStart,\r | |
272 | RegionLength,\r | |
273 | (MemorySpaceMap[Index].Attributes & ~EFI_MEMORY_CACHETYPE_MASK) | (MemorySpaceMap[Index].Capabilities & Attributes)\r | |
274 | );\r | |
275 | }\r | |
276 | \r | |
277 | return EFI_SUCCESS;\r | |
278 | }\r | |
aeb61534 | 279 | \r |
2cf4b608 | 280 | EFI_STATUS\r |
281 | SyncCacheConfigPage (\r | |
282 | IN UINT32 SectionIndex,\r | |
283 | IN UINT32 FirstLevelDescriptor,\r | |
284 | IN UINTN NumberOfDescriptors,\r | |
285 | IN EFI_GCD_MEMORY_SPACE_DESCRIPTOR *MemorySpaceMap,\r | |
286 | IN OUT EFI_PHYSICAL_ADDRESS *NextRegionBase,\r | |
287 | IN OUT UINT64 *NextRegionLength,\r | |
288 | IN OUT UINT32 *NextSectionAttributes\r | |
289 | )\r | |
290 | {\r | |
291 | EFI_STATUS Status;\r | |
292 | UINT32 i;\r | |
293 | volatile ARM_PAGE_TABLE_ENTRY *SecondLevelTable;\r | |
294 | UINT32 NextPageAttributes = 0;\r | |
295 | UINT32 PageAttributes = 0;\r | |
296 | UINT32 BaseAddress;\r | |
297 | UINT64 GcdAttributes;\r | |
298 | \r | |
299 | // Get the Base Address from FirstLevelDescriptor;\r | |
300 | BaseAddress = TT_DESCRIPTOR_PAGE_BASE_ADDRESS(SectionIndex << TT_DESCRIPTOR_SECTION_BASE_SHIFT);\r | |
301 | \r | |
302 | // Convert SectionAttributes into PageAttributes\r | |
303 | NextPageAttributes =\r | |
304 | TT_DESCRIPTOR_CONVERT_TO_PAGE_CACHE_POLICY(*NextSectionAttributes,0) |\r | |
305 | TT_DESCRIPTOR_CONVERT_TO_PAGE_AP(*NextSectionAttributes);\r | |
306 | \r | |
307 | // obtain page table base\r | |
308 | SecondLevelTable = (ARM_PAGE_TABLE_ENTRY *)(FirstLevelDescriptor & TT_DESCRIPTOR_SECTION_PAGETABLE_ADDRESS_MASK);\r | |
309 | \r | |
310 | for (i=0; i < TRANSLATION_TABLE_PAGE_COUNT; i++) {\r | |
311 | if ((SecondLevelTable[i] & TT_DESCRIPTOR_PAGE_TYPE_MASK) == TT_DESCRIPTOR_PAGE_TYPE_PAGE) {\r | |
312 | // extract attributes (cacheability and permissions)\r | |
313 | PageAttributes = SecondLevelTable[i] & (TT_DESCRIPTOR_PAGE_CACHE_POLICY_MASK | TT_DESCRIPTOR_PAGE_AP_MASK);\r | |
314 | \r | |
315 | if (NextPageAttributes == 0) {\r | |
316 | // start on a new region\r | |
317 | *NextRegionLength = 0;\r | |
318 | *NextRegionBase = BaseAddress | (i << TT_DESCRIPTOR_PAGE_BASE_SHIFT);\r | |
319 | NextPageAttributes = PageAttributes;\r | |
320 | } else if (PageAttributes != NextPageAttributes) {\r | |
321 | // Convert Section Attributes into GCD Attributes\r | |
322 | Status = PageToGcdAttributes (NextPageAttributes, &GcdAttributes);\r | |
323 | ASSERT_EFI_ERROR (Status);\r | |
324 | \r | |
325 | // update GCD with these changes (this will recurse into our own CpuSetMemoryAttributes below which is OK)\r | |
326 | SetGcdMemorySpaceAttributes (MemorySpaceMap, NumberOfDescriptors, *NextRegionBase, *NextRegionLength, GcdAttributes);\r | |
327 | \r | |
328 | // start on a new region\r | |
329 | *NextRegionLength = 0;\r | |
330 | *NextRegionBase = BaseAddress | (i << TT_DESCRIPTOR_PAGE_BASE_SHIFT);\r | |
331 | NextPageAttributes = PageAttributes;\r | |
332 | }\r | |
333 | } else if (NextPageAttributes != 0) {\r | |
334 | // Convert Page Attributes into GCD Attributes\r | |
335 | Status = PageToGcdAttributes (NextPageAttributes, &GcdAttributes);\r | |
336 | ASSERT_EFI_ERROR (Status);\r | |
337 | \r | |
338 | // update GCD with these changes (this will recurse into our own CpuSetMemoryAttributes below which is OK)\r | |
339 | SetGcdMemorySpaceAttributes (MemorySpaceMap, NumberOfDescriptors, *NextRegionBase, *NextRegionLength, GcdAttributes);\r | |
340 | \r | |
341 | *NextRegionLength = 0;\r | |
342 | *NextRegionBase = BaseAddress | (i << TT_DESCRIPTOR_PAGE_BASE_SHIFT);\r | |
343 | NextPageAttributes = 0;\r | |
344 | }\r | |
345 | *NextRegionLength += TT_DESCRIPTOR_PAGE_SIZE;\r | |
346 | }\r | |
347 | \r | |
348 | // Convert back PageAttributes into SectionAttributes\r | |
349 | *NextSectionAttributes =\r | |
350 | TT_DESCRIPTOR_CONVERT_TO_SECTION_CACHE_POLICY(NextPageAttributes,0) |\r | |
351 | TT_DESCRIPTOR_CONVERT_TO_SECTION_AP(NextPageAttributes);\r | |
352 | \r | |
353 | return EFI_SUCCESS;\r | |
354 | }\r | |
aeb61534 A |
355 | \r |
356 | EFI_STATUS\r | |
357 | SyncCacheConfig (\r | |
358 | IN EFI_CPU_ARCH_PROTOCOL *CpuProtocol\r | |
359 | )\r | |
360 | {\r | |
f659880b A |
361 | EFI_STATUS Status;\r |
362 | UINT32 i;\r | |
f659880b A |
363 | EFI_PHYSICAL_ADDRESS NextRegionBase;\r |
364 | UINT64 NextRegionLength;\r | |
2cf4b608 | 365 | UINT32 NextSectionAttributes = 0;\r |
366 | UINT32 SectionAttributes = 0;\r | |
f659880b | 367 | UINT64 GcdAttributes;\r |
aeb61534 | 368 | volatile ARM_FIRST_LEVEL_DESCRIPTOR *FirstLevelTable;\r |
f659880b A |
369 | UINTN NumberOfDescriptors;\r |
370 | EFI_GCD_MEMORY_SPACE_DESCRIPTOR *MemorySpaceMap;\r | |
aeb61534 A |
371 | \r |
372 | \r | |
225290eb | 373 | DEBUG ((EFI_D_PAGE, "SyncCacheConfig()\n"));\r |
f659880b | 374 | \r |
aeb61534 A |
375 | // This code assumes MMU is enabled and filed with section translations\r |
376 | ASSERT (ArmMmuEnabled ());\r | |
377 | \r | |
f659880b A |
378 | //\r |
379 | // Get the memory space map from GCD\r | |
380 | //\r | |
381 | MemorySpaceMap = NULL;\r | |
382 | Status = gDS->GetMemorySpaceMap (&NumberOfDescriptors, &MemorySpaceMap);\r | |
383 | ASSERT_EFI_ERROR (Status);\r | |
384 | \r | |
aeb61534 A |
385 | \r |
386 | // The GCD implementation maintains its own copy of the state of memory space attributes. GCD needs\r | |
387 | // to know what the initial memory space attributes are. The CPU Arch. Protocol does not provide a\r | |
388 | // GetMemoryAttributes function for GCD to get this so we must resort to calling GCD (as if we were\r | |
389 | // a client) to update its copy of the attributes. This is bad architecture and should be replaced\r | |
390 | // with a way for GCD to query the CPU Arch. driver of the existing memory space attributes instead.\r | |
391 | \r | |
392 | // obtain page table base\r | |
1bfda055 | 393 | FirstLevelTable = (ARM_FIRST_LEVEL_DESCRIPTOR *)(ArmGetTTBR0BaseAddress ());\r |
aeb61534 | 394 | \r |
2cf4b608 | 395 | // Get the first region\r |
396 | NextSectionAttributes = FirstLevelTable[0] & (TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK | TT_DESCRIPTOR_SECTION_AP_MASK);\r | |
aeb61534 A |
397 | \r |
398 | // iterate through each 1MB descriptor\r | |
399 | NextRegionBase = NextRegionLength = 0;\r | |
2cf4b608 | 400 | for (i=0; i < TRANSLATION_TABLE_SECTION_COUNT; i++) {\r |
401 | if ((FirstLevelTable[i] & TT_DESCRIPTOR_SECTION_TYPE_MASK) == TT_DESCRIPTOR_SECTION_TYPE_SECTION) {\r | |
402 | // extract attributes (cacheability and permissions)\r | |
403 | SectionAttributes = FirstLevelTable[i] & (TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK | TT_DESCRIPTOR_SECTION_AP_MASK);\r | |
404 | \r | |
405 | if (NextSectionAttributes == 0) {\r | |
406 | // start on a new region\r | |
407 | NextRegionLength = 0;\r | |
408 | NextRegionBase = TT_DESCRIPTOR_SECTION_BASE_ADDRESS(i << TT_DESCRIPTOR_SECTION_BASE_SHIFT);\r | |
409 | NextSectionAttributes = SectionAttributes;\r | |
410 | } else if (SectionAttributes != NextSectionAttributes) {\r | |
411 | // Convert Section Attributes into GCD Attributes\r | |
412 | Status = SectionToGcdAttributes (NextSectionAttributes, &GcdAttributes);\r | |
f659880b | 413 | ASSERT_EFI_ERROR (Status);\r |
aeb61534 A |
414 | \r |
415 | // update GCD with these changes (this will recurse into our own CpuSetMemoryAttributes below which is OK)\r | |
f659880b A |
416 | SetGcdMemorySpaceAttributes (MemorySpaceMap, NumberOfDescriptors, NextRegionBase, NextRegionLength, GcdAttributes);\r |
417 | \r | |
aeb61534 A |
418 | // start on a new region\r |
419 | NextRegionLength = 0;\r | |
2cf4b608 | 420 | NextRegionBase = TT_DESCRIPTOR_SECTION_BASE_ADDRESS(i << TT_DESCRIPTOR_SECTION_BASE_SHIFT);\r |
421 | NextSectionAttributes = SectionAttributes;\r | |
aeb61534 | 422 | }\r |
2cf4b608 | 423 | NextRegionLength += TT_DESCRIPTOR_SECTION_SIZE;\r |
424 | } else if (TT_DESCRIPTOR_SECTION_TYPE_IS_PAGE_TABLE(FirstLevelTable[i])) {\r | |
425 | Status = SyncCacheConfigPage (\r | |
426 | i,FirstLevelTable[i],\r | |
8ea50d2e | 427 | NumberOfDescriptors, MemorySpaceMap,\r |
2cf4b608 | 428 | &NextRegionBase,&NextRegionLength,&NextSectionAttributes);\r |
429 | ASSERT_EFI_ERROR (Status);\r | |
430 | } else {\r | |
431 | // We do not support yet 16MB sections\r | |
432 | ASSERT ((FirstLevelTable[i] & TT_DESCRIPTOR_SECTION_TYPE_MASK) != TT_DESCRIPTOR_SECTION_TYPE_SUPERSECTION);\r | |
aeb61534 | 433 | \r |
2cf4b608 | 434 | // start on a new region\r |
435 | if (NextSectionAttributes != 0) {\r | |
436 | // Convert Section Attributes into GCD Attributes\r | |
437 | Status = SectionToGcdAttributes (NextSectionAttributes, &GcdAttributes);\r | |
438 | ASSERT_EFI_ERROR (Status);\r | |
aeb61534 | 439 | \r |
2cf4b608 | 440 | // update GCD with these changes (this will recurse into our own CpuSetMemoryAttributes below which is OK)\r |
441 | SetGcdMemorySpaceAttributes (MemorySpaceMap, NumberOfDescriptors, NextRegionBase, NextRegionLength, GcdAttributes);\r | |
aeb61534 | 442 | \r |
2cf4b608 | 443 | NextRegionLength = 0;\r |
444 | NextRegionBase = TT_DESCRIPTOR_SECTION_BASE_ADDRESS(i << TT_DESCRIPTOR_SECTION_BASE_SHIFT);\r | |
445 | NextSectionAttributes = 0;\r | |
446 | }\r | |
447 | NextRegionLength += TT_DESCRIPTOR_SECTION_SIZE;\r | |
448 | }\r | |
aeb61534 A |
449 | } // section entry loop\r |
450 | \r | |
2cf4b608 | 451 | if (NextSectionAttributes != 0) {\r |
452 | // Convert Section Attributes into GCD Attributes\r | |
453 | Status = SectionToGcdAttributes (NextSectionAttributes, &GcdAttributes);\r | |
454 | ASSERT_EFI_ERROR (Status);\r | |
455 | \r | |
456 | // update GCD with these changes (this will recurse into our own CpuSetMemoryAttributes below which is OK)\r | |
457 | SetGcdMemorySpaceAttributes (MemorySpaceMap, NumberOfDescriptors, NextRegionBase, NextRegionLength, GcdAttributes);\r | |
458 | }\r | |
459 | \r | |
aeb61534 A |
460 | return EFI_SUCCESS;\r |
461 | }\r | |
462 | \r | |
463 | \r | |
464 | \r | |
465 | EFI_STATUS\r | |
466 | UpdatePageEntries (\r | |
467 | IN EFI_PHYSICAL_ADDRESS BaseAddress,\r | |
468 | IN UINT64 Length,\r | |
469 | IN UINT64 Attributes,\r | |
470 | IN EFI_PHYSICAL_ADDRESS VirtualMask\r | |
471 | )\r | |
472 | {\r | |
473 | EFI_STATUS Status;\r | |
474 | UINT32 EntryValue;\r | |
475 | UINT32 EntryMask;\r | |
476 | UINT32 FirstLevelIdx;\r | |
477 | UINT32 Offset;\r | |
478 | UINT32 NumPageEntries;\r | |
479 | UINT32 Descriptor;\r | |
480 | UINT32 p;\r | |
481 | UINT32 PageTableIndex;\r | |
482 | UINT32 PageTableEntry;\r | |
bb02cb80 | 483 | UINT32 CurrentPageTableEntry;\r |
484 | VOID *Mva;\r | |
aeb61534 A |
485 | \r |
486 | volatile ARM_FIRST_LEVEL_DESCRIPTOR *FirstLevelTable;\r | |
487 | volatile ARM_PAGE_TABLE_ENTRY *PageTable;\r | |
488 | \r | |
920cb926 A |
489 | Status = EFI_SUCCESS;\r |
490 | \r | |
aeb61534 A |
491 | // EntryMask: bitmask of values to change (1 = change this value, 0 = leave alone)\r |
492 | // EntryValue: values at bit positions specified by EntryMask\r | |
1bfda055 | 493 | EntryMask = TT_DESCRIPTOR_PAGE_TYPE_MASK;\r |
494 | EntryValue = TT_DESCRIPTOR_PAGE_TYPE_PAGE;\r | |
aeb61534 A |
495 | // Although the PI spec is unclear on this the GCD guarantees that only\r |
496 | // one Attribute bit is set at a time, so we can safely use a switch statement\r | |
497 | switch (Attributes) {\r | |
498 | case EFI_MEMORY_UC:\r | |
499 | // modify cacheability attributes\r | |
1bfda055 | 500 | EntryMask |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_MASK;\r |
501 | if (FeaturePcdGet(PcdEfiUncachedMemoryToStronglyOrdered)) {\r | |
2ac288f9 | 502 | // map to strongly ordered\r |
503 | EntryValue |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_STRONGLY_ORDERED; // TEX[2:0] = 0, C=0, B=0\r | |
1bfda055 | 504 | } else {\r |
2ac288f9 | 505 | // map to normal non-cachable\r |
506 | EntryValue |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_NON_CACHEABLE; // TEX [2:0]= 001 = 0x2, B=0, C=0\r | |
1bfda055 | 507 | }\r |
aeb61534 A |
508 | break;\r |
509 | \r | |
510 | case EFI_MEMORY_WC:\r | |
511 | // modify cacheability attributes\r | |
1bfda055 | 512 | EntryMask |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_MASK;\r |
aeb61534 | 513 | // map to normal non-cachable\r |
1bfda055 | 514 | EntryValue |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_NON_CACHEABLE; // TEX [2:0]= 001 = 0x2, B=0, C=0\r |
aeb61534 A |
515 | break;\r |
516 | \r | |
517 | case EFI_MEMORY_WT:\r | |
518 | // modify cacheability attributes\r | |
1bfda055 | 519 | EntryMask |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_MASK;\r |
aeb61534 | 520 | // write through with no-allocate\r |
1bfda055 | 521 | EntryValue |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_WRITE_THROUGH_NO_ALLOC; // TEX [2:0] = 0, C=1, B=0\r |
aeb61534 A |
522 | break;\r |
523 | \r | |
524 | case EFI_MEMORY_WB:\r | |
525 | // modify cacheability attributes\r | |
1bfda055 | 526 | EntryMask |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_MASK;\r |
aeb61534 | 527 | // write back (with allocate)\r |
1bfda055 | 528 | EntryValue |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_WRITE_BACK_ALLOC; // TEX [2:0] = 001, C=1, B=1\r |
aeb61534 A |
529 | break;\r |
530 | \r | |
531 | case EFI_MEMORY_WP:\r | |
532 | case EFI_MEMORY_XP:\r | |
533 | case EFI_MEMORY_UCE:\r | |
534 | // cannot be implemented UEFI definition unclear for ARM\r | |
535 | // Cause a page fault if these ranges are accessed.\r | |
1bfda055 | 536 | EntryValue = TT_DESCRIPTOR_PAGE_TYPE_FAULT;\r |
225290eb | 537 | DEBUG ((EFI_D_PAGE, "SetMemoryAttributes(): setting page %lx with unsupported attribute %x will page fault on access\n", BaseAddress, Attributes));\r |
aeb61534 A |
538 | break;\r |
539 | \r | |
540 | default:\r | |
541 | return EFI_UNSUPPORTED;\r | |
aeb61534 A |
542 | }\r |
543 | \r | |
11c20f4e | 544 | // Obtain page table base\r |
1bfda055 | 545 | FirstLevelTable = (ARM_FIRST_LEVEL_DESCRIPTOR *)ArmGetTTBR0BaseAddress ();\r |
aeb61534 | 546 | \r |
11c20f4e | 547 | // Calculate number of 4KB page table entries to change\r |
2297613a | 548 | NumPageEntries = Length / TT_DESCRIPTOR_PAGE_SIZE;\r |
aeb61534 | 549 | \r |
11c20f4e | 550 | // Iterate for the number of 4KB pages to change\r |
aeb61534 | 551 | Offset = 0;\r |
11c20f4e | 552 | for(p = 0; p < NumPageEntries; p++) {\r |
553 | // Calculate index into first level translation table for page table value\r | |
aeb61534 | 554 | \r |
1bfda055 | 555 | FirstLevelIdx = TT_DESCRIPTOR_SECTION_BASE_ADDRESS(BaseAddress + Offset) >> TT_DESCRIPTOR_SECTION_BASE_SHIFT;\r |
556 | ASSERT (FirstLevelIdx < TRANSLATION_TABLE_SECTION_COUNT);\r | |
aeb61534 | 557 | \r |
11c20f4e | 558 | // Read the descriptor from the first level page table\r |
aeb61534 A |
559 | Descriptor = FirstLevelTable[FirstLevelIdx];\r |
560 | \r | |
11c20f4e | 561 | // Does this descriptor need to be converted from section entry to 4K pages?\r |
1bfda055 | 562 | if (!TT_DESCRIPTOR_SECTION_TYPE_IS_PAGE_TABLE(Descriptor)) {\r |
563 | Status = ConvertSectionToPages (FirstLevelIdx << TT_DESCRIPTOR_SECTION_BASE_SHIFT);\r | |
aeb61534 | 564 | if (EFI_ERROR(Status)) {\r |
11c20f4e | 565 | // Exit for loop\r |
aeb61534 A |
566 | break; \r |
567 | } \r | |
568 | \r | |
11c20f4e | 569 | // Re-read descriptor\r |
aeb61534 A |
570 | Descriptor = FirstLevelTable[FirstLevelIdx];\r |
571 | }\r | |
572 | \r | |
11c20f4e | 573 | // Obtain page table base address\r |
1bfda055 | 574 | PageTable = (ARM_PAGE_TABLE_ENTRY *)TT_DESCRIPTOR_PAGE_BASE_ADDRESS(Descriptor);\r |
aeb61534 | 575 | \r |
11c20f4e | 576 | // Calculate index into the page table\r |
1bfda055 | 577 | PageTableIndex = ((BaseAddress + Offset) & TT_DESCRIPTOR_PAGE_INDEX_MASK) >> TT_DESCRIPTOR_PAGE_BASE_SHIFT;\r |
578 | ASSERT (PageTableIndex < TRANSLATION_TABLE_PAGE_COUNT);\r | |
aeb61534 | 579 | \r |
11c20f4e | 580 | // Get the entry\r |
bb02cb80 | 581 | CurrentPageTableEntry = PageTable[PageTableIndex];\r |
aeb61534 | 582 | \r |
11c20f4e | 583 | // Mask off appropriate fields\r |
bb02cb80 | 584 | PageTableEntry = CurrentPageTableEntry & ~EntryMask;\r |
aeb61534 | 585 | \r |
11c20f4e | 586 | // Mask in new attributes and/or permissions\r |
aeb61534 A |
587 | PageTableEntry |= EntryValue;\r |
588 | \r | |
589 | if (VirtualMask != 0) {\r | |
590 | // Make this virtual address point at a physical page\r | |
591 | PageTableEntry &= ~VirtualMask;\r | |
592 | }\r | |
aeb61534 | 593 | \r |
bb02cb80 | 594 | if (CurrentPageTableEntry != PageTableEntry) {\r |
1bfda055 | 595 | Mva = (VOID *)(UINTN)((((UINTN)FirstLevelIdx) << TT_DESCRIPTOR_SECTION_BASE_SHIFT) + (PageTableIndex << TT_DESCRIPTOR_PAGE_BASE_SHIFT));\r |
596 | if ((CurrentPageTableEntry & TT_DESCRIPTOR_PAGE_CACHEABLE_MASK) == TT_DESCRIPTOR_PAGE_CACHEABLE_MASK) {\r | |
bb02cb80 | 597 | // The current section mapping is cacheable so Clean/Invalidate the MVA of the page\r |
598 | // Note assumes switch(Attributes), not ARMv7 possibilities\r | |
2297613a | 599 | WriteBackInvalidateDataCacheRange (Mva, TT_DESCRIPTOR_PAGE_SIZE);\r |
bb02cb80 | 600 | }\r |
601 | \r | |
602 | // Only need to update if we are changing the entry \r | |
603 | PageTable[PageTableIndex] = PageTableEntry; \r | |
604 | ArmUpdateTranslationTableEntry ((VOID *)&PageTable[PageTableIndex], Mva);\r | |
605 | }\r | |
aeb61534 A |
606 | \r |
607 | Status = EFI_SUCCESS;\r | |
2297613a | 608 | Offset += TT_DESCRIPTOR_PAGE_SIZE;\r |
aeb61534 | 609 | \r |
11c20f4e | 610 | } // End first level translation table loop\r |
aeb61534 A |
611 | \r |
612 | return Status;\r | |
613 | }\r | |
614 | \r | |
615 | \r | |
616 | \r | |
617 | EFI_STATUS\r | |
618 | UpdateSectionEntries (\r | |
619 | IN EFI_PHYSICAL_ADDRESS BaseAddress,\r | |
620 | IN UINT64 Length,\r | |
621 | IN UINT64 Attributes,\r | |
622 | IN EFI_PHYSICAL_ADDRESS VirtualMask\r | |
623 | )\r | |
624 | {\r | |
625 | EFI_STATUS Status = EFI_SUCCESS;\r | |
626 | UINT32 EntryMask;\r | |
627 | UINT32 EntryValue;\r | |
628 | UINT32 FirstLevelIdx;\r | |
629 | UINT32 NumSections;\r | |
630 | UINT32 i;\r | |
bb02cb80 | 631 | UINT32 CurrentDescriptor;\r |
aeb61534 | 632 | UINT32 Descriptor;\r |
bb02cb80 | 633 | VOID *Mva;\r |
aeb61534 A |
634 | volatile ARM_FIRST_LEVEL_DESCRIPTOR *FirstLevelTable;\r |
635 | \r | |
636 | // EntryMask: bitmask of values to change (1 = change this value, 0 = leave alone)\r | |
637 | // EntryValue: values at bit positions specified by EntryMask\r | |
638 | \r | |
f659880b | 639 | // Make sure we handle a section range that is unmapped \r |
1bfda055 | 640 | EntryMask = TT_DESCRIPTOR_SECTION_TYPE_MASK;\r |
641 | EntryValue = TT_DESCRIPTOR_SECTION_TYPE_SECTION;\r | |
f659880b | 642 | \r |
aeb61534 A |
643 | // Although the PI spec is unclear on this the GCD guarantees that only\r |
644 | // one Attribute bit is set at a time, so we can safely use a switch statement\r | |
645 | switch(Attributes) {\r | |
646 | case EFI_MEMORY_UC:\r | |
647 | // modify cacheability attributes\r | |
1bfda055 | 648 | EntryMask |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK;\r |
649 | if (FeaturePcdGet(PcdEfiUncachedMemoryToStronglyOrdered)) {\r | |
2ac288f9 | 650 | // map to strongly ordered\r |
651 | EntryValue |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_STRONGLY_ORDERED; // TEX[2:0] = 0, C=0, B=0\r | |
1bfda055 | 652 | } else {\r |
2ac288f9 | 653 | // map to normal non-cachable\r |
654 | EntryValue |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_NON_CACHEABLE; // TEX [2:0]= 001 = 0x2, B=0, C=0\r | |
1bfda055 | 655 | }\r |
aeb61534 A |
656 | break;\r |
657 | \r | |
658 | case EFI_MEMORY_WC:\r | |
659 | // modify cacheability attributes\r | |
1bfda055 | 660 | EntryMask |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK;\r |
aeb61534 | 661 | // map to normal non-cachable\r |
1bfda055 | 662 | EntryValue |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_NON_CACHEABLE; // TEX [2:0]= 001 = 0x2, B=0, C=0\r |
aeb61534 A |
663 | break;\r |
664 | \r | |
665 | case EFI_MEMORY_WT:\r | |
666 | // modify cacheability attributes\r | |
1bfda055 | 667 | EntryMask |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK;\r |
aeb61534 | 668 | // write through with no-allocate\r |
1bfda055 | 669 | EntryValue |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_THROUGH_NO_ALLOC; // TEX [2:0] = 0, C=1, B=0\r |
aeb61534 A |
670 | break;\r |
671 | \r | |
672 | case EFI_MEMORY_WB:\r | |
673 | // modify cacheability attributes\r | |
1bfda055 | 674 | EntryMask |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK;\r |
aeb61534 | 675 | // write back (with allocate)\r |
1bfda055 | 676 | EntryValue |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_BACK_ALLOC; // TEX [2:0] = 001, C=1, B=1\r |
aeb61534 A |
677 | break;\r |
678 | \r | |
679 | case EFI_MEMORY_WP:\r | |
680 | case EFI_MEMORY_XP:\r | |
681 | case EFI_MEMORY_RP:\r | |
682 | case EFI_MEMORY_UCE:\r | |
683 | // cannot be implemented UEFI definition unclear for ARM\r | |
684 | // Cause a page fault if these ranges are accessed.\r | |
1bfda055 | 685 | EntryValue = TT_DESCRIPTOR_SECTION_TYPE_FAULT;\r |
225290eb | 686 | DEBUG ((EFI_D_PAGE, "SetMemoryAttributes(): setting section %lx with unsupported attribute %x will page fault on access\n", BaseAddress, Attributes));\r |
aeb61534 A |
687 | break;\r |
688 | \r | |
689 | \r | |
690 | default:\r | |
691 | return EFI_UNSUPPORTED;\r | |
aeb61534 A |
692 | }\r |
693 | \r | |
694 | // obtain page table base\r | |
1bfda055 | 695 | FirstLevelTable = (ARM_FIRST_LEVEL_DESCRIPTOR *)ArmGetTTBR0BaseAddress ();\r |
aeb61534 A |
696 | \r |
697 | // calculate index into first level translation table for start of modification\r | |
1bfda055 | 698 | FirstLevelIdx = TT_DESCRIPTOR_SECTION_BASE_ADDRESS(BaseAddress) >> TT_DESCRIPTOR_SECTION_BASE_SHIFT;\r |
699 | ASSERT (FirstLevelIdx < TRANSLATION_TABLE_SECTION_COUNT);\r | |
aeb61534 A |
700 | \r |
701 | // calculate number of 1MB first level entries this applies to\r | |
1bfda055 | 702 | NumSections = Length / TT_DESCRIPTOR_SECTION_SIZE;\r |
aeb61534 A |
703 | \r |
704 | // iterate through each descriptor\r | |
705 | for(i=0; i<NumSections; i++) {\r | |
bb02cb80 | 706 | CurrentDescriptor = FirstLevelTable[FirstLevelIdx + i];\r |
aeb61534 A |
707 | \r |
708 | // has this descriptor already been coverted to pages?\r | |
1bfda055 | 709 | if (TT_DESCRIPTOR_SECTION_TYPE_IS_PAGE_TABLE(CurrentDescriptor)) {\r |
aeb61534 | 710 | // forward this 1MB range to page table function instead\r |
1bfda055 | 711 | Status = UpdatePageEntries ((FirstLevelIdx + i) << TT_DESCRIPTOR_SECTION_BASE_SHIFT, TT_DESCRIPTOR_SECTION_SIZE, Attributes, VirtualMask);\r |
aeb61534 A |
712 | } else {\r |
713 | // still a section entry\r | |
714 | \r | |
715 | // mask off appropriate fields\r | |
bb02cb80 | 716 | Descriptor = CurrentDescriptor & ~EntryMask;\r |
aeb61534 A |
717 | \r |
718 | // mask in new attributes and/or permissions\r | |
719 | Descriptor |= EntryValue;\r | |
720 | if (VirtualMask != 0) {\r | |
721 | Descriptor &= ~VirtualMask;\r | |
722 | }\r | |
723 | \r | |
bb02cb80 | 724 | if (CurrentDescriptor != Descriptor) {\r |
1bfda055 | 725 | Mva = (VOID *)(UINTN)(((UINTN)FirstLevelTable) << TT_DESCRIPTOR_SECTION_BASE_SHIFT);\r |
726 | if ((CurrentDescriptor & TT_DESCRIPTOR_SECTION_CACHEABLE_MASK) == TT_DESCRIPTOR_SECTION_CACHEABLE_MASK) {\r | |
bb02cb80 | 727 | // The current section mapping is cacheable so Clean/Invalidate the MVA of the section\r |
728 | // Note assumes switch(Attributes), not ARMv7 possabilities\r | |
729 | WriteBackInvalidateDataCacheRange (Mva, SIZE_1MB);\r | |
730 | }\r | |
731 | \r | |
732 | // Only need to update if we are changing the descriptor \r | |
733 | FirstLevelTable[FirstLevelIdx + i] = Descriptor;\r | |
734 | ArmUpdateTranslationTableEntry ((VOID *)&FirstLevelTable[FirstLevelIdx + i], Mva);\r | |
735 | }\r | |
aeb61534 A |
736 | \r |
737 | Status = EFI_SUCCESS;\r | |
738 | }\r | |
739 | }\r | |
740 | \r | |
741 | return Status;\r | |
742 | }\r | |
743 | \r | |
744 | EFI_STATUS \r | |
745 | ConvertSectionToPages (\r | |
746 | IN EFI_PHYSICAL_ADDRESS BaseAddress\r | |
747 | )\r | |
748 | {\r | |
749 | EFI_STATUS Status;\r | |
750 | EFI_PHYSICAL_ADDRESS PageTableAddr;\r | |
751 | UINT32 FirstLevelIdx;\r | |
752 | UINT32 SectionDescriptor;\r | |
753 | UINT32 PageTableDescriptor;\r | |
754 | UINT32 PageDescriptor;\r | |
2cf4b608 | 755 | UINT32 Index;\r |
aeb61534 A |
756 | \r |
757 | volatile ARM_FIRST_LEVEL_DESCRIPTOR *FirstLevelTable;\r | |
758 | volatile ARM_PAGE_TABLE_ENTRY *PageTable;\r | |
759 | \r | |
225290eb | 760 | DEBUG ((EFI_D_PAGE, "Converting section at 0x%x to pages\n", (UINTN)BaseAddress));\r |
aeb61534 A |
761 | \r |
762 | // obtain page table base\r | |
1bfda055 | 763 | FirstLevelTable = (ARM_FIRST_LEVEL_DESCRIPTOR *)ArmGetTTBR0BaseAddress ();\r |
aeb61534 A |
764 | \r |
765 | // calculate index into first level translation table for start of modification\r | |
1bfda055 | 766 | FirstLevelIdx = TT_DESCRIPTOR_SECTION_BASE_ADDRESS(BaseAddress) >> TT_DESCRIPTOR_SECTION_BASE_SHIFT;\r |
767 | ASSERT (FirstLevelIdx < TRANSLATION_TABLE_SECTION_COUNT);\r | |
aeb61534 A |
768 | \r |
769 | // get section attributes and convert to page attributes\r | |
770 | SectionDescriptor = FirstLevelTable[FirstLevelIdx];\r | |
1bfda055 | 771 | PageDescriptor = TT_DESCRIPTOR_PAGE_TYPE_PAGE;\r |
772 | PageDescriptor |= TT_DESCRIPTOR_CONVERT_TO_PAGE_CACHE_POLICY(SectionDescriptor,0);\r | |
773 | PageDescriptor |= TT_DESCRIPTOR_CONVERT_TO_PAGE_AP(SectionDescriptor);\r | |
774 | PageDescriptor |= TT_DESCRIPTOR_CONVERT_TO_PAGE_XN(SectionDescriptor,0);\r | |
775 | PageDescriptor |= TT_DESCRIPTOR_CONVERT_TO_PAGE_NG(SectionDescriptor);\r | |
776 | PageDescriptor |= TT_DESCRIPTOR_CONVERT_TO_PAGE_S(SectionDescriptor);\r | |
aeb61534 A |
777 | \r |
778 | // allocate a page table for the 4KB entries (we use up a full page even though we only need 1KB)\r | |
779 | Status = gBS->AllocatePages (AllocateAnyPages, EfiBootServicesData, 1, &PageTableAddr);\r | |
780 | if (EFI_ERROR(Status)) {\r | |
781 | return Status;\r | |
782 | }\r | |
783 | \r | |
784 | PageTable = (volatile ARM_PAGE_TABLE_ENTRY *)(UINTN)PageTableAddr;\r | |
785 | \r | |
786 | // write the page table entries out\r | |
2cf4b608 | 787 | for (Index = 0; Index < TRANSLATION_TABLE_PAGE_COUNT; Index++) {\r |
788 | PageTable[Index] = TT_DESCRIPTOR_PAGE_BASE_ADDRESS(BaseAddress + (Index << 12)) | PageDescriptor;\r | |
aeb61534 A |
789 | }\r |
790 | \r | |
791 | // flush d-cache so descriptors make it back to uncached memory for subsequent table walks\r | |
2297613a | 792 | WriteBackInvalidateDataCacheRange ((VOID *)(UINTN)PageTableAddr, TT_DESCRIPTOR_PAGE_SIZE);\r |
aeb61534 A |
793 | \r |
794 | // formulate page table entry, Domain=0, NS=0\r | |
1bfda055 | 795 | PageTableDescriptor = (((UINTN)PageTableAddr) & TT_DESCRIPTOR_SECTION_PAGETABLE_ADDRESS_MASK) | TT_DESCRIPTOR_SECTION_TYPE_PAGE_TABLE;\r |
aeb61534 A |
796 | \r |
797 | // write the page table entry out, repalcing section entry\r | |
798 | FirstLevelTable[FirstLevelIdx] = PageTableDescriptor;\r | |
799 | \r | |
800 | return EFI_SUCCESS;\r | |
801 | }\r | |
802 | \r | |
803 | \r | |
804 | \r | |
805 | EFI_STATUS\r | |
806 | SetMemoryAttributes (\r | |
807 | IN EFI_PHYSICAL_ADDRESS BaseAddress,\r | |
808 | IN UINT64 Length,\r | |
809 | IN UINT64 Attributes,\r | |
810 | IN EFI_PHYSICAL_ADDRESS VirtualMask\r | |
811 | )\r | |
812 | {\r | |
813 | EFI_STATUS Status;\r | |
814 | \r | |
815 | if(((BaseAddress & 0xFFFFF) == 0) && ((Length & 0xFFFFF) == 0)) {\r | |
11c20f4e | 816 | // Is the base and length a multiple of 1 MB?\r |
225290eb | 817 | DEBUG ((EFI_D_PAGE, "SetMemoryAttributes(): MMU section 0x%x length 0x%x to %lx\n", (UINTN)BaseAddress, (UINTN)Length, Attributes));\r |
aeb61534 A |
818 | Status = UpdateSectionEntries (BaseAddress, Length, Attributes, VirtualMask);\r |
819 | } else {\r | |
11c20f4e | 820 | // Base and/or length is not a multiple of 1 MB\r |
225290eb | 821 | DEBUG ((EFI_D_PAGE, "SetMemoryAttributes(): MMU page 0x%x length 0x%x to %lx\n", (UINTN)BaseAddress, (UINTN)Length, Attributes));\r |
aeb61534 A |
822 | Status = UpdatePageEntries (BaseAddress, Length, Attributes, VirtualMask);\r |
823 | }\r | |
824 | \r | |
11c20f4e | 825 | // Flush d-cache so descriptors make it back to uncached memory for subsequent table walks\r |
aeb61534 | 826 | // flush and invalidate pages\r |
11c20f4e | 827 | //TODO: Do we really need to invalidate the caches everytime we change the memory attributes ?\r |
aeb61534 | 828 | ArmCleanInvalidateDataCache ();\r |
11c20f4e | 829 | \r |
aeb61534 A |
830 | ArmInvalidateInstructionCache ();\r |
831 | \r | |
11c20f4e | 832 | // Invalidate all TLB entries so changes are synced\r |
833 | ArmInvalidateTlb ();\r | |
aeb61534 A |
834 | \r |
835 | return Status;\r | |
836 | }\r | |
837 | \r | |
838 | \r | |
839 | /**\r | |
840 | This function modifies the attributes for the memory region specified by BaseAddress and\r | |
841 | Length from their current attributes to the attributes specified by Attributes.\r | |
842 | \r | |
843 | @param This The EFI_CPU_ARCH_PROTOCOL instance.\r | |
844 | @param BaseAddress The physical address that is the start address of a memory region.\r | |
845 | @param Length The size in bytes of the memory region.\r | |
846 | @param Attributes The bit mask of attributes to set for the memory region.\r | |
847 | \r | |
848 | @retval EFI_SUCCESS The attributes were set for the memory region.\r | |
849 | @retval EFI_ACCESS_DENIED The attributes for the memory resource range specified by\r | |
850 | BaseAddress and Length cannot be modified.\r | |
851 | @retval EFI_INVALID_PARAMETER Length is zero.\r | |
852 | @retval EFI_OUT_OF_RESOURCES There are not enough system resources to modify the attributes of\r | |
853 | the memory resource range.\r | |
854 | @retval EFI_UNSUPPORTED The processor does not support one or more bytes of the memory\r | |
855 | resource range specified by BaseAddress and Length.\r | |
856 | The bit mask of attributes is not support for the memory resource\r | |
857 | range specified by BaseAddress and Length.\r | |
858 | \r | |
859 | **/\r | |
860 | EFI_STATUS\r | |
861 | EFIAPI\r | |
862 | CpuSetMemoryAttributes (\r | |
863 | IN EFI_CPU_ARCH_PROTOCOL *This,\r | |
864 | IN EFI_PHYSICAL_ADDRESS BaseAddress,\r | |
865 | IN UINT64 Length,\r | |
866 | IN UINT64 Attributes\r | |
867 | )\r | |
868 | {\r | |
225290eb | 869 | DEBUG ((EFI_D_PAGE, "SetMemoryAttributes(%lx, %lx, %lx)\n", BaseAddress, Length, Attributes));\r |
2297613a | 870 | if ( ((BaseAddress & ~TT_DESCRIPTOR_PAGE_BASE_ADDRESS_MASK) != 0) || ((Length & ~TT_DESCRIPTOR_PAGE_BASE_ADDRESS_MASK) != 0)){\r |
bb02cb80 | 871 | // minimum granularity is SIZE_4KB (4KB on ARM)\r |
872 | DEBUG ((EFI_D_PAGE, "SetMemoryAttributes(%lx, %lx, %lx): minimum ganularity is SIZE_4KB\n", BaseAddress, Length, Attributes));\r | |
aeb61534 A |
873 | return EFI_UNSUPPORTED;\r |
874 | }\r | |
875 | \r | |
876 | return SetMemoryAttributes (BaseAddress, Length, Attributes, 0);\r | |
877 | }\r | |
878 | \r | |
879 | \r | |
880 | \r | |
881 | //\r | |
882 | // Add a new protocol to support \r | |
883 | //\r | |
884 | \r | |
885 | EFI_STATUS\r | |
886 | EFIAPI\r | |
887 | CpuConvertPagesToUncachedVirtualAddress (\r | |
888 | IN VIRTUAL_UNCACHED_PAGES_PROTOCOL *This,\r | |
889 | IN EFI_PHYSICAL_ADDRESS Address,\r | |
890 | IN UINTN Length,\r | |
891 | IN EFI_PHYSICAL_ADDRESS VirtualMask,\r | |
892 | OUT UINT64 *Attributes OPTIONAL\r | |
893 | )\r | |
894 | {\r | |
895 | EFI_STATUS Status;\r | |
896 | EFI_GCD_MEMORY_SPACE_DESCRIPTOR GcdDescriptor;\r | |
897 | \r | |
898 | \r | |
899 | if (Attributes != NULL) {\r | |
900 | Status = gDS->GetMemorySpaceDescriptor (Address, &GcdDescriptor);\r | |
901 | if (!EFI_ERROR (Status)) {\r | |
902 | *Attributes = GcdDescriptor.Attributes;\r | |
903 | }\r | |
904 | }\r | |
225290eb | 905 | \r |
aeb61534 A |
906 | //\r |
907 | // Make this address range page fault if accessed. If it is a DMA buffer than this would \r | |
908 | // be the PCI address. Code should always use the CPU address, and we will or in VirtualMask\r | |
909 | // to that address. \r | |
910 | //\r | |
f659880b | 911 | Status = SetMemoryAttributes (Address, Length, EFI_MEMORY_WP, 0);\r |
aeb61534 A |
912 | if (!EFI_ERROR (Status)) {\r |
913 | Status = SetMemoryAttributes (Address | VirtualMask, Length, EFI_MEMORY_UC, VirtualMask);\r | |
914 | }\r | |
915 | \r | |
6f72e28d | 916 | DEBUG ((DEBUG_INFO | DEBUG_LOAD, "ConvertPagesToUncachedVirtualAddress()\n Unmapped 0x%08lx Mapped 0x%08lx 0x%x bytes\n", Address, Address | VirtualMask, Length));\r |
917 | \r | |
aeb61534 A |
918 | return Status;\r |
919 | }\r | |
920 | \r | |
921 | \r | |
922 | EFI_STATUS\r | |
923 | EFIAPI\r | |
6f72e28d | 924 | CpuReconvertPages (\r |
aeb61534 A |
925 | IN VIRTUAL_UNCACHED_PAGES_PROTOCOL *This,\r |
926 | IN EFI_PHYSICAL_ADDRESS Address,\r | |
927 | IN UINTN Length,\r | |
928 | IN EFI_PHYSICAL_ADDRESS VirtualMask,\r | |
929 | IN UINT64 Attributes\r | |
930 | )\r | |
931 | {\r | |
932 | EFI_STATUS Status;\r | |
6f72e28d | 933 | \r |
934 | DEBUG ((DEBUG_INFO | DEBUG_LOAD, "CpuReconvertPages(%lx, %x, %lx, %lx)\n", Address, Length, VirtualMask, Attributes));\r | |
935 | \r | |
936 | //\r | |
aeb61534 A |
937 | // Unmap the alaised Address\r |
938 | //\r | |
f659880b | 939 | Status = SetMemoryAttributes (Address | VirtualMask, Length, EFI_MEMORY_WP, 0);\r |
aeb61534 A |
940 | if (!EFI_ERROR (Status)) {\r |
941 | //\r | |
942 | // Restore atttributes\r | |
943 | //\r | |
944 | Status = SetMemoryAttributes (Address, Length, Attributes, 0);\r | |
945 | }\r | |
946 | \r | |
947 | return Status;\r | |
948 | }\r | |
949 | \r | |
950 | \r | |
951 | VIRTUAL_UNCACHED_PAGES_PROTOCOL gVirtualUncachedPages = {\r | |
952 | CpuConvertPagesToUncachedVirtualAddress,\r | |
6f72e28d | 953 | CpuReconvertPages\r |
aeb61534 | 954 | };\r |