Update remaining ARM .S files with INTERWORK_FUNC macro. This is the 2nd half of...
[mirror_edk2.git] / ArmPkg / Drivers / CpuPei / CpuPei.c
CommitLineData
afdfe8f0 1/**@file\r
2\r
3Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>\r
4This program and the accompanying materials \r
5are licensed and made available under the terms and conditions of the BSD License \r
6which accompanies this distribution. The full text of the license may be found at \r
7http://opensource.org/licenses/bsd-license.php \r
8 \r
9THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
10WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
11\r
12Module Name:\r
13\r
14 MemoryInit.c\r
15 \r
16Abstract:\r
17\r
18 PEIM to provide fake memory init\r
19\r
20**/\r
21\r
22\r
23\r
24//\r
25// The package level header files this module uses\r
26//\r
27#include <PiPei.h>\r
28//\r
29// The protocols, PPI and GUID defintions for this module\r
30//\r
31\r
32//\r
33// The Library classes this module consumes\r
34//\r
35#include <Library/DebugLib.h>\r
36#include <Library/PeimEntryPoint.h>\r
37#include <Library/PcdLib.h>\r
38#include <Library/HobLib.h>\r
39#include <Library/ArmLib.h>\r
40\r
41//\r
42// Module globals\r
43//\r
44\r
45#define DDR_ATTRIBUTES_CACHED ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK\r
46#define DDR_ATTRIBUTES_UNCACHED ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED\r
47\r
48VOID\r
49JamArmMmuConfig ( VOID )\r
50{\r
51 UINT32 CacheAttributes;\r
52 ARM_MEMORY_REGION_DESCRIPTOR MemoryTable[3];\r
53 VOID *TranslationTableBase;\r
54 UINTN TranslationTableSize;\r
55\r
56 if (FeaturePcdGet(PcdCacheEnable) == TRUE) {\r
57 CacheAttributes = DDR_ATTRIBUTES_CACHED;\r
58 } else {\r
59 CacheAttributes = DDR_ATTRIBUTES_UNCACHED;\r
60 }\r
61\r
62 // DDR\r
63 MemoryTable[0].PhysicalBase = 0;\r
64 MemoryTable[0].VirtualBase = 0;\r
65 MemoryTable[0].Length = 0x10000000;\r
66 MemoryTable[0].Attributes = (ARM_MEMORY_REGION_ATTRIBUTES)CacheAttributes;\r
67\r
68 // SOC Registers. L3 interconnects\r
69 MemoryTable[1].PhysicalBase = 0x10000000;\r
70 MemoryTable[1].VirtualBase = 0x10000000;\r
71 MemoryTable[1].Length = 0xF0000000;\r
72 MemoryTable[1].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;\r
73\r
74 // End of Table\r
75 MemoryTable[2].PhysicalBase = 0;\r
76 MemoryTable[2].VirtualBase = 0;\r
77 MemoryTable[2].Length = 0;\r
78 MemoryTable[2].Attributes = (ARM_MEMORY_REGION_ATTRIBUTES)0;\r
79 \r
80 ArmConfigureMmu (MemoryTable, &TranslationTableBase, &TranslationTableSize);\r
81 \r
82 BuildMemoryAllocationHob((EFI_PHYSICAL_ADDRESS)(UINTN)TranslationTableBase, TranslationTableSize, EfiBootServicesData);\r
83}\r
84\r
85\r
86EFI_STATUS\r
87EFIAPI\r
88InitializeCpuPeim (\r
89 IN EFI_PEI_FILE_HANDLE FileHandle,\r
90 IN CONST EFI_PEI_SERVICES **PeiServices\r
91 )\r
92/*++\r
93\r
94Routine Description:\r
95\r
96 \r
97\r
98Arguments:\r
99\r
100 FileHandle - Handle of the file being invoked.\r
101 PeiServices - Describes the list of possible PEI Services.\r
102 \r
103Returns:\r
104\r
105 Status - EFI_SUCCESS if the boot mode could be set\r
106\r
107--*/\r
108{\r
109 // Enable program flow prediction, if supported.\r
110 ArmEnableBranchPrediction ();\r
111\r
112 JamArmMmuConfig();\r
113\r
114 return EFI_SUCCESS;\r
115}\r