Remove ArmEbPkg and replace with ArmRealViewEbPkg. Ported ArmRealViewEbPkg to have...

[mirror_edk2.git] / ArmPkg / Drivers / CpuPei / CpuPei.c

/**@file\r
\r
Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>\r
This program and the accompanying materials                          \r
are licensed and made available under the terms and conditions of the BSD License         \r
which accompanies this distribution.  The full text of the license may be found at        \r
http://opensource.org/licenses/bsd-license.php                                            \r
                                                                                          \r
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     \r
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             \r
\r
Module Name:\r
\r
  MemoryInit.c\r
   \r
Abstract:\r
\r
  PEIM to provide fake memory init\r
\r
**/\r
\r
\r
\r
//\r
// The package level header files this module uses\r
//\r
#include <PiPei.h>\r
//\r
// The protocols, PPI and GUID defintions for this module\r
//\r
\r
//\r
// The Library classes this module consumes\r
//\r
#include <Library/DebugLib.h>\r
#include <Library/PeimEntryPoint.h>\r
#include <Library/PcdLib.h>\r
#include <Library/HobLib.h>\r
#include <Library/ArmLib.h>\r
\r
//\r
// Module globals\r
//\r
\r
#define DDR_ATTRIBUTES_CACHED                ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK\r
#define DDR_ATTRIBUTES_UNCACHED              ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED\r
\r
VOID\r
JamArmMmuConfig ( VOID )\r
{\r
  UINT32                        CacheAttributes;\r
  ARM_MEMORY_REGION_DESCRIPTOR  MemoryTable[3];\r
  VOID                          *TranslationTableBase;\r
  UINTN                         TranslationTableSize;\r
\r
  if (FeaturePcdGet(PcdCacheEnable) == TRUE) {\r
    CacheAttributes = DDR_ATTRIBUTES_CACHED;\r
  } else {\r
    CacheAttributes = DDR_ATTRIBUTES_UNCACHED;\r
  }\r
\r
  // DDR\r
  MemoryTable[0].PhysicalBase = 0;\r
  MemoryTable[0].VirtualBase  = 0;\r
  MemoryTable[0].Length       = 0x10000000;\r
  MemoryTable[0].Attributes   = (ARM_MEMORY_REGION_ATTRIBUTES)CacheAttributes;\r
\r
  // SOC Registers. L3 interconnects\r
  MemoryTable[1].PhysicalBase = 0x10000000;\r
  MemoryTable[1].VirtualBase  = 0x10000000;\r
  MemoryTable[1].Length       = 0xF0000000;\r
  MemoryTable[1].Attributes   = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;\r
\r
  // End of Table\r
  MemoryTable[2].PhysicalBase = 0;\r
  MemoryTable[2].VirtualBase  = 0;\r
  MemoryTable[2].Length       = 0;\r
  MemoryTable[2].Attributes   = (ARM_MEMORY_REGION_ATTRIBUTES)0;\r
  \r
  ArmConfigureMmu (MemoryTable, &TranslationTableBase, &TranslationTableSize);\r
  \r
  BuildMemoryAllocationHob((EFI_PHYSICAL_ADDRESS)(UINTN)TranslationTableBase, TranslationTableSize, EfiBootServicesData);\r
}\r
\r
\r
EFI_STATUS\r
EFIAPI\r
InitializeCpuPeim (\r
  IN       EFI_PEI_FILE_HANDLE  FileHandle,\r
  IN CONST EFI_PEI_SERVICES     **PeiServices\r
  )\r
/*++\r
\r
Routine Description:\r
\r
  \r
\r
Arguments:\r
\r
  FileHandle  - Handle of the file being invoked.\r
  PeiServices - Describes the list of possible PEI Services.\r
    \r
Returns:\r
\r
  Status -  EFI_SUCCESS if the boot mode could be set\r
\r
--*/\r
{\r
  // Enable program flow prediction, if supported.\r
  ArmEnableBranchPrediction ();\r
\r
  JamArmMmuConfig();\r
\r
  return EFI_SUCCESS;\r
}\r