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1 | /** @file\r |
2 | Header for the MMC Host Protocol implementation for the ARM PrimeCell PL180.\r |
3 | \r |
4 | Copyright (c) 2011, ARM Limited. All rights reserved.\r |
5 | \r |
6 | This program and the accompanying materials \r |
7 | are licensed and made available under the terms and conditions of the BSD License \r |
8 | which accompanies this distribution. The full text of the license may be found at \r |
9 | http://opensource.org/licenses/bsd-license.php \r |
10 | \r |
11 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r |
12 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r |
13 | \r |
14 | **/\r |
15 | \r |
16 | #ifndef __PL180_MCI_H\r |
17 | #define __PL180_MCI_H\r |
18 | \r |
19 | #include <Uefi.h>\r |
20 | \r |
21 | #include <Protocol/MmcHost.h>\r |
22 | \r |
23 | #include <Library/UefiLib.h>\r |
24 | #include <Library/DebugLib.h>\r |
25 | #include <Library/UefiBootServicesTableLib.h>\r |
26 | #include <Library/IoLib.h>\r |
27 | #include <Library/TimerLib.h>\r |
28 | #include <Library/PcdLib.h>\r |
29 | \r |
30 | #define PL180_MCI_DXE_VERSION 0x10\r |
31 | \r |
32 | #define MCI_SYSCTL FixedPcdGet32(PcdPL180MciBaseAddress)\r |
33 | \r |
34 | #define MCI_POWER_CONTROL_REG (MCI_SYSCTL+0x000)\r |
35 | #define MCI_CLOCK_CONTROL_REG (MCI_SYSCTL+0x004)\r |
36 | #define MCI_ARGUMENT_REG (MCI_SYSCTL+0x008)\r |
37 | #define MCI_COMMAND_REG (MCI_SYSCTL+0x00C)\r |
38 | #define MCI_RESPCMD_REG (MCI_SYSCTL+0x010)\r |
39 | #define MCI_RESPONSE0_REG (MCI_SYSCTL+0x014)\r |
40 | #define MCI_RESPONSE1_REG (MCI_SYSCTL+0x018)\r |
41 | #define MCI_RESPONSE2_REG (MCI_SYSCTL+0x01C)\r |
42 | #define MCI_RESPONSE3_REG (MCI_SYSCTL+0x020)\r |
43 | #define MCI_DATA_TIMER_REG (MCI_SYSCTL+0x024)\r |
44 | #define MCI_DATA_LENGTH_REG (MCI_SYSCTL+0x028)\r |
45 | #define MCI_DATA_CTL_REG (MCI_SYSCTL+0x02C)\r |
46 | #define MCI_DATA_COUNTER (MCI_SYSCTL+0x030)\r |
47 | #define MCI_STATUS_REG (MCI_SYSCTL+0x034)\r |
48 | #define MCI_CLEAR_STATUS_REG (MCI_SYSCTL+0x038)\r |
49 | #define MCI_INT0_MASK_REG (MCI_SYSCTL+0x03C)\r |
50 | #define MCI_INT1_MASK_REG (MCI_SYSCTL+0x040)\r |
51 | #define MCI_FIFOCOUNT_REG (MCI_SYSCTL+0x048)\r |
52 | #define MCI_FIFO_REG (MCI_SYSCTL+0x080)\r |
53 | \r |
54 | #define MCI_POWER_UP 0x2\r |
55 | #define MCI_POWER_ON 0x3\r |
56 | #define MCI_POWER_OPENDRAIN (1 << 6)\r |
57 | #define MCI_POWER_ROD (1 << 7)\r |
58 | \r |
59 | #define MCI_CLOCK_ENABLE 0x100\r |
60 | #define MCI_CLOCK_POWERSAVE 0x200\r |
61 | #define MCI_CLOCK_BYPASS 0x400\r |
62 | \r |
63 | #define MCI_STATUS_CMD_CMDCRCFAIL 0x1\r |
64 | #define MCI_STATUS_CMD_DATACRCFAIL 0x2\r |
65 | #define MCI_STATUS_CMD_CMDTIMEOUT 0x4\r |
66 | #define MCI_STATUS_CMD_DATATIMEOUT 0x8\r |
2ed2ed29 |
67 | #define MCI_STATUS_CMD_TX_UNDERRUN 0x10\r |
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68 | #define MCI_STATUS_CMD_RXOVERRUN 0x20\r |
69 | #define MCI_STATUS_CMD_RESPEND 0x40\r |
70 | #define MCI_STATUS_CMD_SENT 0x80\r |
71 | #define MCI_STATUS_CMD_TXDONE (MCI_STATUS_CMD_DATAEND | MCI_STATUS_CMD_DATABLOCKEND)\r |
72 | #define MCI_STATUS_CMD_DATAEND 0x000100 // Command Status - Data end\r |
2ed2ed29 |
73 | #define MCI_STATUS_CMD_START_BIT_ERROR 0x000200\r |
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74 | #define MCI_STATUS_CMD_DATABLOCKEND 0x000400 // Command Status - Data end\r |
75 | #define MCI_STATUS_CMD_ACTIVE 0x800\r |
76 | #define MCI_STATUS_CMD_RXACTIVE (1 << 13)\r |
77 | #define MCI_STATUS_CMD_RXFIFOHALFFULL 0x008000\r |
78 | #define MCI_STATUS_CMD_RXFIFOEMPTY 0x080000\r |
79 | #define MCI_STATUS_CMD_RXDATAAVAILBL (1 << 21)\r |
80 | #define MCI_STATUS_CMD_TXACTIVE (1 << 12)\r |
81 | #define MCI_STATUS_CMD_TXFIFOFULL (1 << 16)\r |
82 | #define MCI_STATUS_CMD_TXFIFOHALFEMPTY (1 << 14)\r |
83 | #define MCI_STATUS_CMD_TXFIFOEMPTY (1 << 18)\r |
84 | #define MCI_STATUS_CMD_TXDATAAVAILBL (1 << 20)\r |
85 | \r |
86 | #define MCI_DATACTL_ENABLE 1\r |
87 | #define MCI_DATACTL_CONT_TO_CARD 0\r |
88 | #define MCI_DATACTL_CARD_TO_CONT 2\r |
89 | #define MCI_DATACTL_BLOCK_TRANS 0\r |
90 | #define MCI_DATACTL_STREAM_TRANS 4\r |
2ed2ed29 |
91 | #define MCI_DATACTL_DMA_ENABLE (1 << 3)\r |
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92 | \r |
93 | #define INDX(CMD_INDX) ((CMD_INDX & 0x3F) | MCI_CPSM_ENABLED)\r |
94 | \r |
95 | #define MCI_CPSM_ENABLED (1 << 10)\r |
96 | #define MCI_CPSM_WAIT_RESPONSE (1 << 6)\r |
97 | #define MCI_CPSM_LONG_RESPONSE (1 << 7)\r |
98 | \r |
99 | #define MCI_TRACE(txt) DEBUG((EFI_D_BLKIO, "ARM_MCI: " txt "\n"))\r |
100 | \r |
101 | EFI_STATUS\r |
102 | EFIAPI\r |
103 | MciGetDriverName (\r |
104 | IN EFI_COMPONENT_NAME_PROTOCOL *This,\r |
105 | IN CHAR8 *Language,\r |
106 | OUT CHAR16 **DriverName\r |
107 | );\r |
108 | \r |
109 | EFI_STATUS\r |
110 | EFIAPI\r |
111 | MciGetControllerName (\r |
112 | IN EFI_COMPONENT_NAME_PROTOCOL *This,\r |
113 | IN EFI_HANDLE ControllerHandle,\r |
114 | IN EFI_HANDLE ChildHandle OPTIONAL,\r |
115 | IN CHAR8 *Language,\r |
116 | OUT CHAR16 **ControllerName\r |
117 | );\r |
118 | \r |
119 | #endif\r |