[mirror_edk2.git] / ArmPkg / Drivers / PL34xDmc / PL341Dmc.c

/** @file\r
*\r
*  Copyright (c) 2011, ARM Limited. All rights reserved.\r
*  \r
*  This program and the accompanying materials                          \r
*  are licensed and made available under the terms and conditions of the BSD License         \r
*  which accompanies this distribution.  The full text of the license may be found at        \r
*  http://opensource.org/licenses/bsd-license.php                                            \r
*\r
*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     \r
*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             \r
*\r
**/\r
\r
#include <Library/IoLib.h>\r
#include <Library/DebugLib.h>\r
#include <Drivers/PL341Dmc.h>\r
\r
// Macros for writing to DDR2 controller.\r
#define DmcWriteReg(reg,val)                    MmioWrite32(DmcBase + reg, val)\r
#define DmcReadReg(reg)                         MmioRead32(DmcBase + reg)\r
\r
// Macros for writing/reading to DDR2 PHY controller\r
#define DmcPhyWriteReg(reg,val)                    MmioWrite32(DmcPhyBase + reg, val)\r
#define DmcPhyReadReg(reg)                         MmioRead32(DmcPhyBase + reg)\r
\r
// Initialise PL341 Dynamic Memory Controller\r
VOID\r
PL341DmcInit (\r
  IN  PL341_DMC_CONFIG *DmcConfig\r
  )\r
{\r
  UINTN DmcBase;\r
  UINTN Index;\r
  UINT32 Chip;\r
\r
  DmcBase = DmcConfig->base;\r
\r
  // Set config mode\r
  DmcWriteReg(DMC_COMMAND_REG, DMC_COMMAND_CONFIGURE);\r
\r
  //\r
  // Setup the QoS AXI ID bits\r
  //\r
  if (DmcConfig->HasQos) {\r
    // CLCD AXIID = 000\r
    DmcWriteReg(DMC_ID_0_CFG_REG, DMC_ID_CFG_QOS_ENABLE | DMC_ID_CFG_QOS_MIN);\r
\r
    // Default disable QoS\r
    DmcWriteReg(DMC_ID_1_CFG_REG, DMC_ID_CFG_QOS_DISABLE);\r
    DmcWriteReg(DMC_ID_2_CFG_REG, DMC_ID_CFG_QOS_DISABLE);\r
    DmcWriteReg(DMC_ID_3_CFG_REG, DMC_ID_CFG_QOS_DISABLE);\r
    DmcWriteReg(DMC_ID_4_CFG_REG, DMC_ID_CFG_QOS_DISABLE);\r
    DmcWriteReg(DMC_ID_5_CFG_REG, DMC_ID_CFG_QOS_DISABLE);\r
    DmcWriteReg(DMC_ID_6_CFG_REG, DMC_ID_CFG_QOS_DISABLE);\r
    DmcWriteReg(DMC_ID_7_CFG_REG, DMC_ID_CFG_QOS_DISABLE);\r
    DmcWriteReg(DMC_ID_8_CFG_REG, DMC_ID_CFG_QOS_DISABLE);\r
    DmcWriteReg(DMC_ID_9_CFG_REG, DMC_ID_CFG_QOS_DISABLE);\r
    DmcWriteReg(DMC_ID_10_CFG_REG, DMC_ID_CFG_QOS_DISABLE);\r
    DmcWriteReg(DMC_ID_11_CFG_REG, DMC_ID_CFG_QOS_DISABLE);\r
    DmcWriteReg(DMC_ID_12_CFG_REG, DMC_ID_CFG_QOS_DISABLE);\r
    DmcWriteReg(DMC_ID_13_CFG_REG, DMC_ID_CFG_QOS_DISABLE);\r
    DmcWriteReg(DMC_ID_14_CFG_REG, DMC_ID_CFG_QOS_DISABLE);\r
    DmcWriteReg(DMC_ID_15_CFG_REG, DMC_ID_CFG_QOS_DISABLE);\r
  }\r
\r
  //\r
  // Initialise memory controlller\r
  //\r
  DmcWriteReg(DMC_REFRESH_PRD_REG, DmcConfig->refresh_prd);\r
  DmcWriteReg(DMC_CAS_LATENCY_REG, DmcConfig->cas_latency);\r
  DmcWriteReg(DMC_WRITE_LATENCY_REG, DmcConfig->write_latency);\r
  DmcWriteReg(DMC_T_MRD_REG, DmcConfig->t_mrd);\r
  DmcWriteReg(DMC_T_RAS_REG, DmcConfig->t_ras);\r
  DmcWriteReg(DMC_T_RC_REG, DmcConfig->t_rc);\r
  DmcWriteReg(DMC_T_RCD_REG, DmcConfig->t_rcd);\r
  DmcWriteReg(DMC_T_RFC_REG, DmcConfig->t_rfc);\r
  DmcWriteReg(DMC_T_RP_REG, DmcConfig->t_rp);\r
  DmcWriteReg(DMC_T_RRD_REG, DmcConfig->t_rrd);\r
  DmcWriteReg(DMC_T_WR_REG, DmcConfig->t_wr);\r
  DmcWriteReg(DMC_T_WTR_REG, DmcConfig->t_wtr);\r
  DmcWriteReg(DMC_T_XP_REG, DmcConfig->t_xp);\r
  DmcWriteReg(DMC_T_XSR_REG, DmcConfig->t_xsr);\r
  DmcWriteReg(DMC_T_ESR_REG, DmcConfig->t_esr);\r
  DmcWriteReg(DMC_T_FAW_REG, DmcConfig->t_faw);\r
  DmcWriteReg(DMC_T_WRLAT_DIFF, DmcConfig->t_wdata_en);\r
  DmcWriteReg(DMC_T_RDATA_EN, DmcConfig->t_data_en);\r
\r
  //\r
  // Initialise PL341 Mem Config Registers\r
  //\r
\r
  // Set PL341 Memory Config\r
  DmcWriteReg(DMC_MEMORY_CONFIG_REG, DmcConfig->MemoryCfg);\r
\r
  // Set PL341 Memory Config 2\r
  DmcWriteReg(DMC_MEMORY_CFG2_REG, DmcConfig->MemoryCfg2);\r
\r
  // Set PL341 Chip Select <n>\r
  DmcWriteReg(DMC_CHIP_0_CFG_REG, DmcConfig->ChipCfg0);\r
  DmcWriteReg(DMC_CHIP_1_CFG_REG, DmcConfig->ChipCfg1);\r
  DmcWriteReg(DMC_CHIP_2_CFG_REG, DmcConfig->ChipCfg2);\r
  DmcWriteReg(DMC_CHIP_3_CFG_REG, DmcConfig->ChipCfg3);\r
\r
  // Delay\r
  for (Index = 0; Index < 10; Index++) {\r
    DmcReadReg(DMC_STATUS_REG);\r
  }\r
\r
  // Set PL341 Memory Config 3\r
  DmcWriteReg(DMC_MEMORY_CFG3_REG, DmcConfig->MemoryCfg3);\r
\r
  if (DmcConfig->IsUserCfg) {\r
    //\r
    // Set Test Chip PHY Registers via PL341 User Config Reg\r
    // Note that user_cfgX registers are Write Only\r
    //\r
    // DLL Freq set = 250MHz - 266MHz\r
    //\r
    DmcWriteReg(DMC_USER_0_CFG_REG, DmcConfig->User0Cfg);\r
\r
    // user_config2\r
    // ------------\r
    // Set defaults before calibrating the DDR2 buffer impendence\r
    // - Disable ODT\r
    // - Default drive strengths\r
    DmcWriteReg(DMC_USER_2_CFG_REG, 0x40000198);\r
\r
    //\r
    // Auto calibrate the DDR2 buffers impendence\r
    //\r
    while (!(DmcReadReg(DMC_USER_STATUS_REG) & 0x100));\r
\r
    // Set the output driven strength\r
    DmcWriteReg(DMC_USER_2_CFG_REG, 0x40800000 | DmcConfig->User2Cfg);\r
\r
    //\r
    // Set PL341 Feature Control Register\r
    //\r
    // Disable early BRESP - use to optimise CLCD performance\r
    DmcWriteReg(DMC_FEATURE_CRTL_REG, 0x00000001);\r
  }\r
\r
  //\r
  // Config memories\r
  //\r
  for (Chip = 0; Chip < DmcConfig->MaxChip; Chip++) {\r
    // Send nop\r
    DmcWriteReg(DMC_DIRECT_CMD_REG, DMC_DIRECT_CMD_CHIP_ADDR(Chip) | DMC_DIRECT_CMD_MEMCMD_NOP);\r
\r
    // Pre-charge all\r
    DmcWriteReg(DMC_DIRECT_CMD_REG, DMC_DIRECT_CMD_CHIP_ADDR(Chip) | DMC_DIRECT_CMD_MEMCMD_PRECHARGEALL);\r
\r
    // Delay\r
    for (Index = 0; Index < 10; Index++) {\r
      DmcReadReg(DMC_STATUS_REG);\r
    }\r
\r
    // Set (EMR2) extended mode register 2\r
    DmcWriteReg(DMC_DIRECT_CMD_REG,\r
      DMC_DIRECT_CMD_CHIP_ADDR(Chip) |\r
      DMC_DIRECT_CMD_BANKADDR(2) |\r
      DMC_DIRECT_CMD_MEMCMD_EXTMODEREG);\r
\r
    // Set (EMR3) extended mode register 3\r
    DmcWriteReg(DMC_DIRECT_CMD_REG,\r
      DMC_DIRECT_CMD_CHIP_ADDR(Chip) |\r
      DMC_DIRECT_CMD_BANKADDR(3) |\r
      DMC_DIRECT_CMD_MEMCMD_EXTMODEREG);\r
\r
    //\r
    // Set (EMR) Extended Mode Register\r
    //\r
    // Put into OCD default state\r
    DmcWriteReg(DMC_DIRECT_CMD_REG,DMC_DIRECT_CMD_CHIP_ADDR(Chip) | DMC_DIRECT_CMD_BANKADDR(1) | DMC_DIRECT_CMD_MEMCMD_EXTMODEREG);\r
\r
    //\r
    // Set (MR) mode register - With DLL reset\r
    //\r
    DmcWriteReg(DMC_DIRECT_CMD_REG, DMC_DIRECT_CMD_CHIP_ADDR(Chip) | DMC_DIRECT_CMD_MEMCMD_EXTMODEREG | DmcConfig->ModeReg | DDR2_MR_DLL_RESET);\r
\r
    // Pre-charge all\r
    DmcWriteReg(DMC_DIRECT_CMD_REG, DMC_DIRECT_CMD_CHIP_ADDR(Chip) | DMC_DIRECT_CMD_MEMCMD_PRECHARGEALL);\r
    // Auto-refresh\r
    DmcWriteReg(DMC_DIRECT_CMD_REG, DMC_DIRECT_CMD_CHIP_ADDR(Chip) | DMC_DIRECT_CMD_MEMCMD_AUTOREFRESH);\r
    // Auto-refresh\r
    DmcWriteReg(DMC_DIRECT_CMD_REG, DMC_DIRECT_CMD_CHIP_ADDR(Chip) | DMC_DIRECT_CMD_MEMCMD_AUTOREFRESH);\r
\r
    //\r
    // Set (MR) mode register - Without DLL reset\r
    //\r
    DmcWriteReg(DMC_DIRECT_CMD_REG, DMC_DIRECT_CMD_CHIP_ADDR(Chip) | DMC_DIRECT_CMD_MEMCMD_EXTMODEREG | DmcConfig->ModeReg);\r
\r
    // Delay\r
    for (Index = 0; Index < 10; Index++) {\r
      DmcReadReg(DMC_STATUS_REG);\r
    }\r
\r
    //\r
    // Set (EMR) extended mode register - Enable OCD defaults\r
    //\r
    DmcWriteReg(DMC_DIRECT_CMD_REG, DMC_DIRECT_CMD_CHIP_ADDR(Chip) | (0x00090000) |\r
        (1 << DDR_MODESET_SHFT) | (DDR_EMR_OCD_DEFAULT << DDR_EMR_OCD_SHIFT) | DmcConfig->ExtModeReg);\r
\r
    // Delay\r
    for (Index = 0; Index < 10; Index++) {\r
      DmcReadReg(DMC_STATUS_REG);\r
    }\r
\r
    // Set (EMR) extended mode register - OCD Exit\r
    DmcWriteReg(DMC_DIRECT_CMD_REG, DMC_DIRECT_CMD_CHIP_ADDR(Chip) | (0x00090000) |\r
        (1 << DDR_MODESET_SHFT) | (DDR_EMR_OCD_NS << DDR_EMR_OCD_SHIFT) | DmcConfig->ExtModeReg);\r
  }\r
\r
  // Move DDR2 Controller to Ready state by issueing GO command\r
  DmcWriteReg(DMC_COMMAND_REG, DMC_COMMAND_GO);\r
\r
  // wait for ready\r
  while (!(DmcReadReg(DMC_STATUS_REG) & DMC_STATUS_READY));\r
\r
}\r
Commit	Line	Data
1bfda055	1	/** @file\r
	2	*\r
	3	* Copyright (c) 2011, ARM Limited. All rights reserved.\r
	4	* \r
	5	* This program and the accompanying materials \r
	6	* are licensed and made available under the terms and conditions of the BSD License \r
	7	* which accompanies this distribution. The full text of the license may be found at \r
	8	* http://opensource.org/licenses/bsd-license.php \r
	9	*\r
	10	* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
	11	* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
	12	*\r
	13	**/\r
	14	\r
	15	#include <Library/IoLib.h>\r
	16	#include <Library/DebugLib.h>\r
	17	#include <Drivers/PL341Dmc.h>\r
	18	\r
8be5d4d6	19	// Macros for writing to DDR2 controller.\r
	20	#define DmcWriteReg(reg,val) MmioWrite32(DmcBase + reg, val)\r
	21	#define DmcReadReg(reg) MmioRead32(DmcBase + reg)\r
1bfda055	22	\r
8be5d4d6	23	// Macros for writing/reading to DDR2 PHY controller\r
	24	#define DmcPhyWriteReg(reg,val) MmioWrite32(DmcPhyBase + reg, val)\r
	25	#define DmcPhyReadReg(reg) MmioRead32(DmcPhyBase + reg)\r
	26	\r
	27	// Initialise PL341 Dynamic Memory Controller\r
	28	VOID\r
	29	PL341DmcInit (\r
	30	IN PL341_DMC_CONFIG *DmcConfig\r
	31	)\r
	32	{\r
	33	UINTN DmcBase;\r
	34	UINTN Index;\r
	35	UINT32 Chip;\r
	36	\r
	37	DmcBase = DmcConfig->base;\r
	38	\r
	39	// Set config mode\r
	40	DmcWriteReg(DMC_COMMAND_REG, DMC_COMMAND_CONFIGURE);\r
	41	\r
	42	//\r
	43	// Setup the QoS AXI ID bits\r
	44	//\r
	45	if (DmcConfig->HasQos) {\r
	46	// CLCD AXIID = 000\r
	47	DmcWriteReg(DMC_ID_0_CFG_REG, DMC_ID_CFG_QOS_ENABLE \| DMC_ID_CFG_QOS_MIN);\r
	48	\r
	49	// Default disable QoS\r
	50	DmcWriteReg(DMC_ID_1_CFG_REG, DMC_ID_CFG_QOS_DISABLE);\r
	51	DmcWriteReg(DMC_ID_2_CFG_REG, DMC_ID_CFG_QOS_DISABLE);\r
	52	DmcWriteReg(DMC_ID_3_CFG_REG, DMC_ID_CFG_QOS_DISABLE);\r
	53	DmcWriteReg(DMC_ID_4_CFG_REG, DMC_ID_CFG_QOS_DISABLE);\r
	54	DmcWriteReg(DMC_ID_5_CFG_REG, DMC_ID_CFG_QOS_DISABLE);\r
	55	DmcWriteReg(DMC_ID_6_CFG_REG, DMC_ID_CFG_QOS_DISABLE);\r
	56	DmcWriteReg(DMC_ID_7_CFG_REG, DMC_ID_CFG_QOS_DISABLE);\r
	57	DmcWriteReg(DMC_ID_8_CFG_REG, DMC_ID_CFG_QOS_DISABLE);\r
	58	DmcWriteReg(DMC_ID_9_CFG_REG, DMC_ID_CFG_QOS_DISABLE);\r
	59	DmcWriteReg(DMC_ID_10_CFG_REG, DMC_ID_CFG_QOS_DISABLE);\r
	60	DmcWriteReg(DMC_ID_11_CFG_REG, DMC_ID_CFG_QOS_DISABLE);\r
	61	DmcWriteReg(DMC_ID_12_CFG_REG, DMC_ID_CFG_QOS_DISABLE);\r
	62	DmcWriteReg(DMC_ID_13_CFG_REG, DMC_ID_CFG_QOS_DISABLE);\r
	63	DmcWriteReg(DMC_ID_14_CFG_REG, DMC_ID_CFG_QOS_DISABLE);\r
	64	DmcWriteReg(DMC_ID_15_CFG_REG, DMC_ID_CFG_QOS_DISABLE);\r
	65	}\r
1bfda055	66	\r
8be5d4d6	67	//\r
	68	// Initialise memory controlller\r
	69	//\r
	70	DmcWriteReg(DMC_REFRESH_PRD_REG, DmcConfig->refresh_prd);\r
	71	DmcWriteReg(DMC_CAS_LATENCY_REG, DmcConfig->cas_latency);\r
	72	DmcWriteReg(DMC_WRITE_LATENCY_REG, DmcConfig->write_latency);\r
	73	DmcWriteReg(DMC_T_MRD_REG, DmcConfig->t_mrd);\r
	74	DmcWriteReg(DMC_T_RAS_REG, DmcConfig->t_ras);\r
	75	DmcWriteReg(DMC_T_RC_REG, DmcConfig->t_rc);\r
	76	DmcWriteReg(DMC_T_RCD_REG, DmcConfig->t_rcd);\r
	77	DmcWriteReg(DMC_T_RFC_REG, DmcConfig->t_rfc);\r
	78	DmcWriteReg(DMC_T_RP_REG, DmcConfig->t_rp);\r
	79	DmcWriteReg(DMC_T_RRD_REG, DmcConfig->t_rrd);\r
	80	DmcWriteReg(DMC_T_WR_REG, DmcConfig->t_wr);\r
	81	DmcWriteReg(DMC_T_WTR_REG, DmcConfig->t_wtr);\r
	82	DmcWriteReg(DMC_T_XP_REG, DmcConfig->t_xp);\r
	83	DmcWriteReg(DMC_T_XSR_REG, DmcConfig->t_xsr);\r
	84	DmcWriteReg(DMC_T_ESR_REG, DmcConfig->t_esr);\r
	85	DmcWriteReg(DMC_T_FAW_REG, DmcConfig->t_faw);\r
	86	DmcWriteReg(DMC_T_WRLAT_DIFF, DmcConfig->t_wdata_en);\r
	87	DmcWriteReg(DMC_T_RDATA_EN, DmcConfig->t_data_en);\r
	88	\r
	89	//\r
	90	// Initialise PL341 Mem Config Registers\r
	91	//\r
	92	\r
	93	// Set PL341 Memory Config\r
	94	DmcWriteReg(DMC_MEMORY_CONFIG_REG, DmcConfig->MemoryCfg);\r
	95	\r
	96	// Set PL341 Memory Config 2\r
	97	DmcWriteReg(DMC_MEMORY_CFG2_REG, DmcConfig->MemoryCfg2);\r
	98	\r
	99	// Set PL341 Chip Select <n>\r
	100	DmcWriteReg(DMC_CHIP_0_CFG_REG, DmcConfig->ChipCfg0);\r
	101	DmcWriteReg(DMC_CHIP_1_CFG_REG, DmcConfig->ChipCfg1);\r
	102	DmcWriteReg(DMC_CHIP_2_CFG_REG, DmcConfig->ChipCfg2);\r
	103	DmcWriteReg(DMC_CHIP_3_CFG_REG, DmcConfig->ChipCfg3);\r
	104	\r
	105	// Delay\r
	106	for (Index = 0; Index < 10; Index++) {\r
	107	DmcReadReg(DMC_STATUS_REG);\r
	108	}\r
1bfda055	109	\r
8be5d4d6	110	// Set PL341 Memory Config 3\r
8be5d4d6	111	DmcWriteReg(DMC_MEMORY_CFG3_REG, DmcConfig->MemoryCfg3);\r
1bfda055	112	\r
8be5d4d6	113	if (DmcConfig->IsUserCfg) {\r
	114	//\r
	115	// Set Test Chip PHY Registers via PL341 User Config Reg\r
	116	// Note that user_cfgX registers are Write Only\r
	117	//\r
	118	// DLL Freq set = 250MHz - 266MHz\r
	119	//\r
	120	DmcWriteReg(DMC_USER_0_CFG_REG, DmcConfig->User0Cfg);\r
1bfda055	121	\r
8be5d4d6	122	// user_config2\r
	123	// ------------\r
	124	// Set defaults before calibrating the DDR2 buffer impendence\r
	125	// - Disable ODT\r
	126	// - Default drive strengths\r
	127	DmcWriteReg(DMC_USER_2_CFG_REG, 0x40000198);\r
1bfda055	128	\r
1bfda055	129	//\r
8be5d4d6	130	// Auto calibrate the DDR2 buffers impendence\r
1bfda055	131	//\r
8be5d4d6	132	while (!(DmcReadReg(DMC_USER_STATUS_REG) & 0x100));\r
1bfda055	133	\r
8be5d4d6	134	// Set the output driven strength\r
8be5d4d6	135	DmcWriteReg(DMC_USER_2_CFG_REG, 0x40800000 \| DmcConfig->User2Cfg);\r
1bfda055	136	\r
1bfda055	137	//\r
8be5d4d6	138	// Set PL341 Feature Control Register\r
1bfda055	139	//\r
8be5d4d6	140	// Disable early BRESP - use to optimise CLCD performance\r
8be5d4d6	141	DmcWriteReg(DMC_FEATURE_CRTL_REG, 0x00000001);\r
2ac288f9	142	}\r
2ac288f9	143	\r
8be5d4d6	144	//\r
	145	// Config memories\r
	146	//\r
	147	for (Chip = 0; Chip < DmcConfig->MaxChip; Chip++) {\r
	148	// Send nop\r
	149	DmcWriteReg(DMC_DIRECT_CMD_REG, DMC_DIRECT_CMD_CHIP_ADDR(Chip) \| DMC_DIRECT_CMD_MEMCMD_NOP);\r
2ac288f9	150	\r
8be5d4d6	151	// Pre-charge all\r
8be5d4d6	152	DmcWriteReg(DMC_DIRECT_CMD_REG, DMC_DIRECT_CMD_CHIP_ADDR(Chip) \| DMC_DIRECT_CMD_MEMCMD_PRECHARGEALL);\r
2ac288f9	153	\r
8be5d4d6	154	// Delay\r
	155	for (Index = 0; Index < 10; Index++) {\r
	156	DmcReadReg(DMC_STATUS_REG);\r
	157	}\r
1bfda055	158	\r
8be5d4d6	159	// Set (EMR2) extended mode register 2\r
	160	DmcWriteReg(DMC_DIRECT_CMD_REG,\r
	161	DMC_DIRECT_CMD_CHIP_ADDR(Chip) \|\r
	162	DMC_DIRECT_CMD_BANKADDR(2) \|\r
	163	DMC_DIRECT_CMD_MEMCMD_EXTMODEREG);\r
1bfda055	164	\r
8be5d4d6	165	// Set (EMR3) extended mode register 3\r
	166	DmcWriteReg(DMC_DIRECT_CMD_REG,\r
	167	DMC_DIRECT_CMD_CHIP_ADDR(Chip) \|\r
	168	DMC_DIRECT_CMD_BANKADDR(3) \|\r
	169	DMC_DIRECT_CMD_MEMCMD_EXTMODEREG);\r
2ac288f9	170	\r
8be5d4d6	171	//\r
	172	// Set (EMR) Extended Mode Register\r
	173	//\r
	174	// Put into OCD default state\r
	175	DmcWriteReg(DMC_DIRECT_CMD_REG,DMC_DIRECT_CMD_CHIP_ADDR(Chip) \| DMC_DIRECT_CMD_BANKADDR(1) \| DMC_DIRECT_CMD_MEMCMD_EXTMODEREG);\r
	176	\r
	177	//\r
	178	// Set (MR) mode register - With DLL reset\r
	179	//\r
	180	DmcWriteReg(DMC_DIRECT_CMD_REG, DMC_DIRECT_CMD_CHIP_ADDR(Chip) \| DMC_DIRECT_CMD_MEMCMD_EXTMODEREG \| DmcConfig->ModeReg \| DDR2_MR_DLL_RESET);\r
	181	\r
	182	// Pre-charge all\r
	183	DmcWriteReg(DMC_DIRECT_CMD_REG, DMC_DIRECT_CMD_CHIP_ADDR(Chip) \| DMC_DIRECT_CMD_MEMCMD_PRECHARGEALL);\r
	184	// Auto-refresh\r
	185	DmcWriteReg(DMC_DIRECT_CMD_REG, DMC_DIRECT_CMD_CHIP_ADDR(Chip) \| DMC_DIRECT_CMD_MEMCMD_AUTOREFRESH);\r
	186	// Auto-refresh\r
	187	DmcWriteReg(DMC_DIRECT_CMD_REG, DMC_DIRECT_CMD_CHIP_ADDR(Chip) \| DMC_DIRECT_CMD_MEMCMD_AUTOREFRESH);\r
	188	\r
	189	//\r
	190	// Set (MR) mode register - Without DLL reset\r
	191	//\r
	192	DmcWriteReg(DMC_DIRECT_CMD_REG, DMC_DIRECT_CMD_CHIP_ADDR(Chip) \| DMC_DIRECT_CMD_MEMCMD_EXTMODEREG \| DmcConfig->ModeReg);\r
1bfda055	193	\r
8be5d4d6	194	// Delay\r
	195	for (Index = 0; Index < 10; Index++) {\r
	196	DmcReadReg(DMC_STATUS_REG);\r
1bfda055	197	}\r
1bfda055	198	\r
8be5d4d6	199	//\r
	200	// Set (EMR) extended mode register - Enable OCD defaults\r
	201	//\r
	202	DmcWriteReg(DMC_DIRECT_CMD_REG, DMC_DIRECT_CMD_CHIP_ADDR(Chip) \| (0x00090000) \|\r
	203	(1 << DDR_MODESET_SHFT) \| (DDR_EMR_OCD_DEFAULT << DDR_EMR_OCD_SHIFT) \| DmcConfig->ExtModeReg);\r
1bfda055	204	\r
8be5d4d6	205	// Delay\r
	206	for (Index = 0; Index < 10; Index++) {\r
	207	DmcReadReg(DMC_STATUS_REG);\r
1bfda055	208	}\r
8be5d4d6	209	\r
	210	// Set (EMR) extended mode register - OCD Exit\r
	211	DmcWriteReg(DMC_DIRECT_CMD_REG, DMC_DIRECT_CMD_CHIP_ADDR(Chip) \| (0x00090000) \|\r
	212	(1 << DDR_MODESET_SHFT) \| (DDR_EMR_OCD_NS << DDR_EMR_OCD_SHIFT) \| DmcConfig->ExtModeReg);\r
	213	}\r
	214	\r
	215	// Move DDR2 Controller to Ready state by issueing GO command\r
	216	DmcWriteReg(DMC_COMMAND_REG, DMC_COMMAND_GO);\r
	217	\r
	218	// wait for ready\r
	219	while (!(DmcReadReg(DMC_STATUS_REG) & DMC_STATUS_READY));\r
	220	\r
1bfda055	221	}\r