[mirror_edk2.git] / ArmPkg / Drivers / PL35xSmc / InitializeSMC.S

#\r
#  Copyright (c) 2011, ARM Limited. All rights reserved.\r
#  \r
#  This program and the accompanying materials                          \r
#  are licensed and made available under the terms and conditions of the BSD License         \r
#  which accompanies this distribution.  The full text of the license may be found at        \r
#  http:#opensource.org/licenses/bsd-license.php                                            \r
#\r
#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     \r
#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             \r
#\r
#\r
\r
#include <AsmMacroIoLib.h>\r
#include <Library/PcdLib.h>\r
#include <AutoGen.h>\r
#include <Drivers/PL354Smc.h>\r
\r
#Start of the code section\r
.text\r
\r
#Maintain 8 byte alignment\r
.align 3\r
\r
\r
GCC_ASM_EXPORT(SMCInitializeNOR)\r
GCC_ASM_EXPORT(SMCInitializeSRAM)\r
GCC_ASM_EXPORT(SMCInitializePeripherals)\r
GCC_ASM_EXPORT(SMCInitializeVRAM)\r
\r
\r
# CS0  CS0-Interf0     NOR1 flash on the motherboard\r
# CS1  CS1-Interf0     Reserved for the motherboard\r
# CS2  CS2-Interf0     SRAM on the motherboard\r
# CS3  CS3-Interf0     memory-mapped Ethernet and USB controllers on the motherboard\r
# CS4  CS0-Interf1     NOR2 flash on the motherboard\r
# CS5  CS1-Interf1     memory-mapped peripherals\r
# CS6  CS2-Interf1     memory-mapped peripherals\r
# CS7  CS3-Interf1     system memory-mapped peripherals on the motherboard.\r
\r
// IN r1 SmcBase\r
// IN r2 ChipSelect\r
// NOTE: This code is been called before any stack has been setup. It means some registers\r
//       could be overwritten (case of 'r0')\r
ASM_PFX(SMCInitializeNOR):\r
#\r
# Setup NOR1 (CS0-Interface0)\r
#\r
\r
  # Write to set_cycle register(holding register for NOR 1 cycle register or NAND cycle register)\r
     #Read cycle timeout = 0xA (0:3)\r
     #Write cycle timeout = 0x3(7:4)\r
     #OE Assertion Delay = 0x9(11:8)\r
     #WE Assertion delay = 0x3(15:12)\r
     #Page cycle timeout = 0x2(19:16)  \r
  LoadConstantToReg (0x0002393A,r0)       @ldr     r0, = 0x0002393A\r
  str     r0, [r1, #PL354_SMC_SET_CYCLES_OFFSET]\r
  \r
  # Write to set_opmode register(holding register for NOR 1 opomode register or NAND opmode register)\r
     # 0x00000002 = MemoryWidth: 32bit\r
     # 0x00000028 = ReadMemoryBurstLength:continuous\r
     # 0x00000280 = WriteMemoryBurstLength:continuous\r
     # 0x00000800 = Set Address Valid\r
  LoadConstantToReg (0x00000AAA,r0)       @ldr     r0, = 0x00000AAA\r
  str     r0, [r1, #PL354_SMC_SET_OPMODE_OFFSET]\r
\r
 # Write to direct_cmd register so that the NOR 1 registers(set-cycles and opmode) are updated with holding registers\r
     # 0x00000000 = ChipSelect0-Interface 0\r
     # 0x00400000 = CmdTypes: UpdateRegs\r
  LoadConstantToReg (0x00400000,r0)       @ldr     r0, = 0x00400000\r
  str     r0, [r1, #PL354_SMC_DIRECT_CMD_OFFSET]\r
  \r
  bx lr\r
\r
ASM_PFX(SMCInitializeSRAM):\r
#\r
# Setup SRAM (CS2-Interface0)\r
#\r
  LoadConstantToReg (0x00027158,r0)       @ldr     r0, = 0x00027158\r
  str     r0, [r1, #PL354_SMC_SET_CYCLES_OFFSET]\r
\r
  # 0x00000002 = MemoryWidth: 32bit\r
  # 0x00000800 = Set Address Valid\r
  LoadConstantToReg (0x00000802,r0)       @ldr     r0, = 0x00000802\r
  str     r0, [r1, #PL354_SMC_SET_OPMODE_OFFSET]\r
  \r
  # 0x01000000 = ChipSelect2-Interface 0\r
  # 0x00400000 = CmdTypes: UpdateRegs\r
  LoadConstantToReg (0x01400000,r0)       @ldr     r0, = 0x01400000\r
  str     r0, [r1, #PL354_SMC_DIRECT_CMD_OFFSET]\r
\r
  bx    lr\r
\r
ASM_PFX(SMCInitializePeripherals):\r
#\r
# USB/Eth/VRAM (CS3-Interface0)\r
#\r
  LoadConstantToReg (0x000CD2AA,r0)      @ldr     r0, = 0x000CD2AA\r
  str     r0, [r1, #PL354_SMC_SET_CYCLES_OFFSET]\r
 \r
  # 0x00000002 = MemoryWidth: 32bit\r
  # 0x00000004 = Memory reads are synchronous\r
  # 0x00000040 = Memory writes are synchronous\r
  LoadConstantToReg (0x00000046,r0)      @ldr     r0, = 0x00000046\r
  str     r0, [r1, #PL354_SMC_SET_OPMODE_OFFSET]\r
        \r
  # 0x01800000 = ChipSelect3-Interface 0\r
  # 0x00400000 = CmdTypes: UpdateRegs\r
  LoadConstantToReg (0x01C00000,r0)      @ldr     r0, = 0x01C00000\r
  str     r0, [r1, #PL354_SMC_DIRECT_CMD_OFFSET]\r
\r
#\r
# Setup NOR3 (CS0-Interface1)\r
#\r
  LoadConstantToReg (0x0002393A,r0)      @ldr     r0, = 0x0002393A\r
  str     r0, [r1, #PL354_SMC_SET_CYCLES_OFFSET]\r
 \r
  # 0x00000002 = MemoryWidth: 32bit\r
  # 0x00000028 = ReadMemoryBurstLength:continuous\r
  # 0x00000280 = WriteMemoryBurstLength:continuous\r
  # 0x00000800 = Set Address Valid\r
  LoadConstantToReg (0x00000AAA,r0)      @ldr     r0, = 0x00000AAA\r
  str     r0, [r1, #PL354_SMC_SET_OPMODE_OFFSET]\r
        \r
  # 0x02000000 = ChipSelect0-Interface 1\r
  # 0x00400000 = CmdTypes: UpdateRegs\r
  LoadConstantToReg (0x02400000,r0)      @ldr     r0, = 0x02400000\r
  str     r0, [r1, #PL354_SMC_DIRECT_CMD_OFFSET]\r
 \r
#\r
# Setup Peripherals (CS3-Interface1)\r
#\r
  LoadConstantToReg (0x00025156,r0)      @ldr     r0, = 0x00025156\r
  str     r0, [r1, #PL354_SMC_SET_CYCLES_OFFSET]\r
 \r
  # 0x00000002 = MemoryWidth: 32bit\r
  # 0x00000004 = Memory reads are synchronous\r
  # 0x00000040 = Memory writes are synchronous\r
  LoadConstantToReg (0x00000046,r0)      @ldr     r0, = 0x00000046\r
  str     r0, [r1, #PL354_SMC_SET_OPMODE_OFFSET]\r
        \r
  # 0x03800000 = ChipSelect3-Interface 1\r
  # 0x00400000 = CmdTypes: UpdateRegs\r
  LoadConstantToReg (0x03C00000,r0)      @ldr     r0, = 0x03C00000\r
  str     r0, [r1, #PL354_SMC_DIRECT_CMD_OFFSET]\r
  bx    lr\r
\r
// IN r1 SmcBase\r
// IN r2 VideoSRamBase\r
// NOTE: This code is been called before any stack has been setup. It means some registers\r
//       could be overwritten (case of 'r0')\r
ASM_PFX(SMCInitializeVRAM):\r
#\r
# Setup VRAM (CS1-Interface0)\r
#\r
  LoadConstantToReg (0x00049249,r0)      @ldr     r0, =  0x00049249\r
  str     r0, [r1, #PL354_SMC_SET_CYCLES_OFFSET]\r
 \r
  # 0x00000002 = MemoryWidth: 32bit\r
  # 0x00000004 = Memory reads are synchronous\r
  # 0x00000040 = Memory writes are synchronous\r
  LoadConstantToReg (0x00000046,r0)      @ldr     r0, = 0x00000046\r
  str     r0, [r1, #PL354_SMC_SET_OPMODE_OFFSET]\r
        \r
  # 0x00800000 = ChipSelect1-Interface 0\r
  # 0x00400000 = CmdTypes: UpdateRegs\r
  LoadConstantToReg (0x00C00000,r0)      @ldr     r0, = 0x00C00000\r
  str     r0, [r1, #PL354_SMC_DIRECT_CMD_OFFSET]\r
  \r
#\r
# Page mode setup for VRAM\r
#\r
  #read current state \r
  ldr     r0, [r2, #0]  \r
  ldr     r0, [r2, #0]  \r
  LoadConstantToReg (0x00000000,r0)      @ldr     r0, = 0x00000000\r
  str     r0, [r2, #0] \r
  ldr     r0, [r2, #0]  \r
\r
  #enable page mode \r
  ldr     r0, [r2, #0]  \r
  ldr     r0, [r2, #0]  \r
  LoadConstantToReg (0x00000000,r0)      @ldr     r0, = 0x00000000\r
  str     r0, [r2, #0] \r
  LoadConstantToReg (0x00900090,r0)      @ldr     r0, = 0x00900090\r
  str     r0, [r2, #0] \r
\r
  #confirm page mode enabled\r
  ldr     r0, [r2, #0]  \r
  ldr     r0, [r2, #0]  \r
  LoadConstantToReg (0x00000000,r0)      @ldr     r0, = 0x00000000\r
  str     r0, [r2, #0] \r
  ldr     r0, [r2, #0]  \r
  \r
  bx    lr\r
  \r
ASM_FUNCTION_REMOVE_IF_UNREFERENCED
Commit	Line	Data
1bfda055	1	#\r
	2	# Copyright (c) 2011, ARM Limited. All rights reserved.\r
	3	# \r
	4	# This program and the accompanying materials \r
	5	# are licensed and made available under the terms and conditions of the BSD License \r
	6	# which accompanies this distribution. The full text of the license may be found at \r
	7	# http:#opensource.org/licenses/bsd-license.php \r
	8	#\r
	9	# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
	10	# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
	11	#\r
	12	#\r
	13	\r
	14	#include <AsmMacroIoLib.h>\r
	15	#include <Library/PcdLib.h>\r
	16	#include <AutoGen.h>\r
f501f5d1	17	#include <Drivers/PL354Smc.h>\r
1bfda055	18	\r
	19	#Start of the code section\r
	20	.text\r
	21	\r
	22	#Maintain 8 byte alignment\r
	23	.align 3\r
	24	\r
1bfda055	25	\r
f501f5d1	26	GCC_ASM_EXPORT(SMCInitializeNOR)\r
	27	GCC_ASM_EXPORT(SMCInitializeSRAM)\r
	28	GCC_ASM_EXPORT(SMCInitializePeripherals)\r
	29	GCC_ASM_EXPORT(SMCInitializeVRAM)\r
	30	\r
1bfda055	31	\r
	32	# CS0 CS0-Interf0 NOR1 flash on the motherboard\r
	33	# CS1 CS1-Interf0 Reserved for the motherboard\r
	34	# CS2 CS2-Interf0 SRAM on the motherboard\r
	35	# CS3 CS3-Interf0 memory-mapped Ethernet and USB controllers on the motherboard\r
	36	# CS4 CS0-Interf1 NOR2 flash on the motherboard\r
	37	# CS5 CS1-Interf1 memory-mapped peripherals\r
	38	# CS6 CS2-Interf1 memory-mapped peripherals\r
	39	# CS7 CS3-Interf1 system memory-mapped peripherals on the motherboard.\r
	40	\r
f501f5d1	41	// IN r1 SmcBase\r
	42	// IN r2 ChipSelect\r
	43	// NOTE: This code is been called before any stack has been setup. It means some registers\r
	44	// could be overwritten (case of 'r0')\r
	45	ASM_PFX(SMCInitializeNOR):\r
1bfda055	46	#\r
	47	# Setup NOR1 (CS0-Interface0)\r
	48	#\r
	49	\r
f501f5d1	50	# Write to set_cycle register(holding register for NOR 1 cycle register or NAND cycle register)\r
1bfda055	51	#Read cycle timeout = 0xA (0:3)\r
	52	#Write cycle timeout = 0x3(7:4)\r
	53	#OE Assertion Delay = 0x9(11:8)\r
	54	#WE Assertion delay = 0x3(15:12)\r
	55	#Page cycle timeout = 0x2(19:16) \r
	56	LoadConstantToReg (0x0002393A,r0) @ldr r0, = 0x0002393A\r
f501f5d1	57	str r0, [r1, #PL354_SMC_SET_CYCLES_OFFSET]\r
1bfda055	58	\r
f501f5d1	59	# Write to set_opmode register(holding register for NOR 1 opomode register or NAND opmode register)\r
1bfda055	60	# 0x00000002 = MemoryWidth: 32bit\r
	61	# 0x00000028 = ReadMemoryBurstLength:continuous\r
	62	# 0x00000280 = WriteMemoryBurstLength:continuous\r
	63	# 0x00000800 = Set Address Valid\r
	64	LoadConstantToReg (0x00000AAA,r0) @ldr r0, = 0x00000AAA\r
f501f5d1	65	str r0, [r1, #PL354_SMC_SET_OPMODE_OFFSET]\r
1bfda055	66	\r
f501f5d1	67	# Write to direct_cmd register so that the NOR 1 registers(set-cycles and opmode) are updated with holding registers\r
1bfda055	68	# 0x00000000 = ChipSelect0-Interface 0\r
	69	# 0x00400000 = CmdTypes: UpdateRegs\r
	70	LoadConstantToReg (0x00400000,r0) @ldr r0, = 0x00400000\r
f501f5d1	71	str r0, [r1, #PL354_SMC_DIRECT_CMD_OFFSET]\r
1bfda055	72	\r
f501f5d1	73	bx lr\r
	74	\r
	75	ASM_PFX(SMCInitializeSRAM):\r
1bfda055	76	#\r
	77	# Setup SRAM (CS2-Interface0)\r
	78	#\r
	79	LoadConstantToReg (0x00027158,r0) @ldr r0, = 0x00027158\r
f501f5d1	80	str r0, [r1, #PL354_SMC_SET_CYCLES_OFFSET]\r
1bfda055	81	\r
	82	# 0x00000002 = MemoryWidth: 32bit\r
	83	# 0x00000800 = Set Address Valid\r
	84	LoadConstantToReg (0x00000802,r0) @ldr r0, = 0x00000802\r
f501f5d1	85	str r0, [r1, #PL354_SMC_SET_OPMODE_OFFSET]\r
1bfda055	86	\r
	87	# 0x01000000 = ChipSelect2-Interface 0\r
	88	# 0x00400000 = CmdTypes: UpdateRegs\r
	89	LoadConstantToReg (0x01400000,r0) @ldr r0, = 0x01400000\r
f501f5d1	90	str r0, [r1, #PL354_SMC_DIRECT_CMD_OFFSET]\r
	91	\r
	92	bx lr\r
1bfda055	93	\r
f501f5d1	94	ASM_PFX(SMCInitializePeripherals):\r
1bfda055	95	#\r
	96	# USB/Eth/VRAM (CS3-Interface0)\r
	97	#\r
	98	LoadConstantToReg (0x000CD2AA,r0) @ldr r0, = 0x000CD2AA\r
f501f5d1	99	str r0, [r1, #PL354_SMC_SET_CYCLES_OFFSET]\r
1bfda055	100	\r
	101	# 0x00000002 = MemoryWidth: 32bit\r
	102	# 0x00000004 = Memory reads are synchronous\r
	103	# 0x00000040 = Memory writes are synchronous\r
	104	LoadConstantToReg (0x00000046,r0) @ldr r0, = 0x00000046\r
f501f5d1	105	str r0, [r1, #PL354_SMC_SET_OPMODE_OFFSET]\r
1bfda055	106	\r
	107	# 0x01800000 = ChipSelect3-Interface 0\r
	108	# 0x00400000 = CmdTypes: UpdateRegs\r
	109	LoadConstantToReg (0x01C00000,r0) @ldr r0, = 0x01C00000\r
f501f5d1	110	str r0, [r1, #PL354_SMC_DIRECT_CMD_OFFSET]\r
1bfda055	111	\r
	112	#\r
	113	# Setup NOR3 (CS0-Interface1)\r
	114	#\r
	115	LoadConstantToReg (0x0002393A,r0) @ldr r0, = 0x0002393A\r
f501f5d1	116	str r0, [r1, #PL354_SMC_SET_CYCLES_OFFSET]\r
1bfda055	117	\r
	118	# 0x00000002 = MemoryWidth: 32bit\r
	119	# 0x00000028 = ReadMemoryBurstLength:continuous\r
	120	# 0x00000280 = WriteMemoryBurstLength:continuous\r
	121	# 0x00000800 = Set Address Valid\r
	122	LoadConstantToReg (0x00000AAA,r0) @ldr r0, = 0x00000AAA\r
f501f5d1	123	str r0, [r1, #PL354_SMC_SET_OPMODE_OFFSET]\r
1bfda055	124	\r
	125	# 0x02000000 = ChipSelect0-Interface 1\r
	126	# 0x00400000 = CmdTypes: UpdateRegs\r
	127	LoadConstantToReg (0x02400000,r0) @ldr r0, = 0x02400000\r
f501f5d1	128	str r0, [r1, #PL354_SMC_DIRECT_CMD_OFFSET]\r
1bfda055	129	\r
	130	#\r
	131	# Setup Peripherals (CS3-Interface1)\r
	132	#\r
	133	LoadConstantToReg (0x00025156,r0) @ldr r0, = 0x00025156\r
f501f5d1	134	str r0, [r1, #PL354_SMC_SET_CYCLES_OFFSET]\r
1bfda055	135	\r
	136	# 0x00000002 = MemoryWidth: 32bit\r
	137	# 0x00000004 = Memory reads are synchronous\r
	138	# 0x00000040 = Memory writes are synchronous\r
	139	LoadConstantToReg (0x00000046,r0) @ldr r0, = 0x00000046\r
f501f5d1	140	str r0, [r1, #PL354_SMC_SET_OPMODE_OFFSET]\r
1bfda055	141	\r
	142	# 0x03800000 = ChipSelect3-Interface 1\r
	143	# 0x00400000 = CmdTypes: UpdateRegs\r
	144	LoadConstantToReg (0x03C00000,r0) @ldr r0, = 0x03C00000\r
f501f5d1	145	str r0, [r1, #PL354_SMC_DIRECT_CMD_OFFSET]\r
f501f5d1	146	bx lr\r
1bfda055	147	\r
f501f5d1	148	// IN r1 SmcBase\r
	149	// IN r2 VideoSRamBase\r
	150	// NOTE: This code is been called before any stack has been setup. It means some registers\r
	151	// could be overwritten (case of 'r0')\r
	152	ASM_PFX(SMCInitializeVRAM):\r
1bfda055	153	#\r
	154	# Setup VRAM (CS1-Interface0)\r
	155	#\r
	156	LoadConstantToReg (0x00049249,r0) @ldr r0, = 0x00049249\r
f501f5d1	157	str r0, [r1, #PL354_SMC_SET_CYCLES_OFFSET]\r
1bfda055	158	\r
	159	# 0x00000002 = MemoryWidth: 32bit\r
	160	# 0x00000004 = Memory reads are synchronous\r
	161	# 0x00000040 = Memory writes are synchronous\r
	162	LoadConstantToReg (0x00000046,r0) @ldr r0, = 0x00000046\r
f501f5d1	163	str r0, [r1, #PL354_SMC_SET_OPMODE_OFFSET]\r
1bfda055	164	\r
	165	# 0x00800000 = ChipSelect1-Interface 0\r
	166	# 0x00400000 = CmdTypes: UpdateRegs\r
	167	LoadConstantToReg (0x00C00000,r0) @ldr r0, = 0x00C00000\r
f501f5d1	168	str r0, [r1, #PL354_SMC_DIRECT_CMD_OFFSET]\r
1bfda055	169	\r
	170	#\r
	171	# Page mode setup for VRAM\r
	172	#\r
	173	#read current state \r
	174	ldr r0, [r2, #0] \r
	175	ldr r0, [r2, #0] \r
	176	LoadConstantToReg (0x00000000,r0) @ldr r0, = 0x00000000\r
	177	str r0, [r2, #0] \r
	178	ldr r0, [r2, #0] \r
	179	\r
	180	#enable page mode \r
	181	ldr r0, [r2, #0] \r
	182	ldr r0, [r2, #0] \r
	183	LoadConstantToReg (0x00000000,r0) @ldr r0, = 0x00000000\r
	184	str r0, [r2, #0] \r
	185	LoadConstantToReg (0x00900090,r0) @ldr r0, = 0x00900090\r
	186	str r0, [r2, #0] \r
	187	\r
	188	#confirm page mode enabled\r
	189	ldr r0, [r2, #0] \r
	190	ldr r0, [r2, #0] \r
	191	LoadConstantToReg (0x00000000,r0) @ldr r0, = 0x00000000\r
	192	str r0, [r2, #0] \r
	193	ldr r0, [r2, #0] \r
	194	\r
	195	bx lr\r
	196	\r
	197	ASM_FUNCTION_REMOVE_IF_UNREFERENCED