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1 | /** @file\r |
2 | *\r |
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3 | * Copyright (c) 2011-2012, ARM Limited. All rights reserved.\r |
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4 | * \r |
5 | * This program and the accompanying materials \r |
6 | * are licensed and made available under the terms and conditions of the BSD License \r |
7 | * which accompanies this distribution. The full text of the license may be found at \r |
8 | * http://opensource.org/licenses/bsd-license.php \r |
9 | *\r |
10 | * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r |
11 | * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r |
12 | *\r |
13 | **/\r |
14 | \r |
15 | #include <Uefi.h>\r |
16 | #include <Library/IoLib.h>\r |
17 | #include <Library/ArmGicLib.h>\r |
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18 | #include <Library/PcdLib.h>\r |
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19 | \r |
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20 | UINTN\r |
21 | EFIAPI\r |
22 | ArmGicGetMaxNumInterrupts (\r |
23 | IN INTN GicDistributorBase\r |
24 | )\r |
25 | {\r |
26 | return 32 * ((MmioRead32 (GicDistributorBase + ARM_GIC_ICDICTR) & 0x1F) + 1);\r |
27 | }\r |
28 | \r |
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29 | VOID\r |
30 | EFIAPI\r |
31 | ArmGicSendSgiTo (\r |
32 | IN INTN GicDistributorBase,\r |
33 | IN INTN TargetListFilter,\r |
34 | IN INTN CPUTargetList\r |
35 | )\r |
36 | {\r |
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37 | MmioWrite32 (GicDistributorBase + ARM_GIC_ICDSGIR, ((TargetListFilter & 0x3) << 24) | ((CPUTargetList & 0xFF) << 16) | PcdGet32(PcdGicSgiIntId));\r |
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38 | }\r |
39 | \r |
40 | UINT32\r |
41 | EFIAPI\r |
42 | ArmGicAcknowledgeSgiFrom (\r |
43 | IN INTN GicInterruptInterfaceBase,\r |
44 | IN INTN CoreId\r |
45 | )\r |
46 | {\r |
47 | INTN InterruptId;\r |
48 | \r |
49 | InterruptId = MmioRead32 (GicInterruptInterfaceBase + ARM_GIC_ICCIAR);\r |
50 | \r |
51 | // Check if the Interrupt ID is valid, The read from Interrupt Ack register returns CPU ID and Interrupt ID\r |
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52 | if ((((CoreId & 0x7) << 10) | PcdGet32(PcdGicSgiIntId)) == InterruptId) {\r |
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53 | // Got SGI number 0 hence signal End of Interrupt by writing to ICCEOIR\r |
54 | MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCEIOR, InterruptId);\r |
55 | return 1;\r |
56 | } else {\r |
57 | return 0;\r |
58 | }\r |
59 | }\r |
60 | \r |
61 | UINT32\r |
62 | EFIAPI\r |
63 | ArmGicAcknowledgeSgi2From (\r |
64 | IN INTN GicInterruptInterfaceBase,\r |
65 | IN INTN CoreId,\r |
66 | IN INTN SgiId\r |
67 | )\r |
68 | {\r |
69 | INTN InterruptId;\r |
70 | \r |
71 | InterruptId = MmioRead32(GicInterruptInterfaceBase + ARM_GIC_ICCIAR);\r |
72 | \r |
73 | // Check if the Interrupt ID is valid, The read from Interrupt Ack register returns CPU ID and Interrupt ID\r |
74 | if((((CoreId & 0x7) << 10) | (SgiId & 0x3FF)) == (InterruptId & 0x1FFF)) {\r |
75 | // Got SGI number 0 hence signal End of Interrupt by writing to ICCEOIR\r |
76 | MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCEIOR, InterruptId);\r |
77 | return 1;\r |
78 | } else {\r |
79 | return 0;\r |
80 | }\r |
81 | }\r |