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1 | /*++\r |
2 | \r |
3 | Copyright (c) 2009, Hewlett-Packard Company. All rights reserved.<BR>\r |
4 | Portions copyright (c) 2010, Apple Inc. All rights reserved.<BR>\r |
111339d2 |
5 | Portions copyright (c) 2011-2013, ARM Ltd. All rights reserved.<BR> \r |
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6 | \r |
7 | This program and the accompanying materials \r |
8 | are licensed and made available under the terms and conditions of the BSD License \r |
9 | which accompanies this distribution. The full text of the license may be found at \r |
10 | http://opensource.org/licenses/bsd-license.php \r |
11 | \r |
12 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r |
13 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r |
14 | \r |
15 | Module Name:\r |
16 | \r |
17 | Gic.c\r |
18 | \r |
19 | Abstract:\r |
20 | \r |
21 | Driver implementing the GIC interrupt controller protocol\r |
22 | \r |
23 | --*/\r |
24 | \r |
25 | #include <PiDxe.h>\r |
26 | \r |
111339d2 |
27 | #include <Library/ArmLib.h>\r |
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28 | #include <Library/BaseLib.h>\r |
29 | #include <Library/DebugLib.h>\r |
30 | #include <Library/BaseMemoryLib.h>\r |
31 | #include <Library/MemoryAllocationLib.h>\r |
32 | #include <Library/UefiBootServicesTableLib.h>\r |
33 | #include <Library/UefiLib.h>\r |
34 | #include <Library/PcdLib.h>\r |
35 | #include <Library/IoLib.h>\r |
36 | #include <Library/ArmGicLib.h>\r |
37 | \r |
38 | #include <Protocol/Cpu.h>\r |
39 | #include <Protocol/HardwareInterrupt.h>\r |
40 | \r |
41 | #define ARM_GIC_DEFAULT_PRIORITY 0x80\r |
42 | \r |
43 | extern EFI_HARDWARE_INTERRUPT_PROTOCOL gHardwareInterruptProtocol;\r |
44 | \r |
45 | //\r |
46 | // Notifications\r |
47 | //\r |
48 | EFI_EVENT EfiExitBootServicesEvent = (EFI_EVENT)NULL;\r |
49 | \r |
50 | // Maximum Number of Interrupts\r |
51 | UINTN mGicNumInterrupts = 0;\r |
52 | \r |
53 | HARDWARE_INTERRUPT_HANDLER *gRegisteredInterruptHandlers = NULL;\r |
54 | \r |
55 | /**\r |
56 | Register Handler for the specified interrupt source.\r |
57 | \r |
58 | @param This Instance pointer for this protocol\r |
59 | @param Source Hardware source of the interrupt\r |
60 | @param Handler Callback for interrupt. NULL to unregister\r |
61 | \r |
62 | @retval EFI_SUCCESS Source was updated to support Handler.\r |
63 | @retval EFI_DEVICE_ERROR Hardware could not be programmed.\r |
64 | \r |
65 | **/\r |
66 | EFI_STATUS\r |
67 | EFIAPI\r |
68 | RegisterInterruptSource (\r |
69 | IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,\r |
70 | IN HARDWARE_INTERRUPT_SOURCE Source,\r |
71 | IN HARDWARE_INTERRUPT_HANDLER Handler\r |
72 | )\r |
73 | {\r |
74 | if (Source > mGicNumInterrupts) {\r |
75 | ASSERT(FALSE);\r |
76 | return EFI_UNSUPPORTED;\r |
77 | }\r |
78 | \r |
79 | if ((Handler == NULL) && (gRegisteredInterruptHandlers[Source] == NULL)) {\r |
80 | return EFI_INVALID_PARAMETER;\r |
81 | }\r |
82 | \r |
83 | if ((Handler != NULL) && (gRegisteredInterruptHandlers[Source] != NULL)) {\r |
84 | return EFI_ALREADY_STARTED;\r |
85 | }\r |
86 | \r |
87 | gRegisteredInterruptHandlers[Source] = Handler;\r |
88 | \r |
89 | // If the interrupt handler is unregistered then disable the interrupt\r |
90 | if (NULL == Handler){\r |
91 | return This->DisableInterruptSource (This, Source);\r |
92 | } else {\r |
93 | return This->EnableInterruptSource (This, Source);\r |
94 | }\r |
95 | }\r |
96 | \r |
97 | /**\r |
98 | Enable interrupt source Source.\r |
99 | \r |
100 | @param This Instance pointer for this protocol\r |
101 | @param Source Hardware source of the interrupt\r |
102 | \r |
103 | @retval EFI_SUCCESS Source interrupt enabled.\r |
104 | @retval EFI_DEVICE_ERROR Hardware could not be programmed.\r |
105 | \r |
106 | **/\r |
107 | EFI_STATUS\r |
108 | EFIAPI\r |
109 | EnableInterruptSource (\r |
110 | IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,\r |
111 | IN HARDWARE_INTERRUPT_SOURCE Source\r |
112 | )\r |
113 | {\r |
114 | UINT32 RegOffset;\r |
115 | UINTN RegShift;\r |
116 | \r |
117 | if (Source > mGicNumInterrupts) {\r |
118 | ASSERT(FALSE);\r |
119 | return EFI_UNSUPPORTED;\r |
120 | }\r |
121 | \r |
122 | // Calculate enable register offset and bit position\r |
123 | RegOffset = Source / 32;\r |
124 | RegShift = Source % 32;\r |
125 | \r |
126 | // Write set-enable register\r |
127 | MmioWrite32 (PcdGet32(PcdGicDistributorBase) + ARM_GIC_ICDISER + (4*RegOffset), 1 << RegShift);\r |
128 | \r |
129 | return EFI_SUCCESS;\r |
130 | }\r |
131 | \r |
132 | /**\r |
133 | Disable interrupt source Source.\r |
134 | \r |
135 | @param This Instance pointer for this protocol\r |
136 | @param Source Hardware source of the interrupt\r |
137 | \r |
138 | @retval EFI_SUCCESS Source interrupt disabled.\r |
139 | @retval EFI_DEVICE_ERROR Hardware could not be programmed.\r |
140 | \r |
141 | **/\r |
142 | EFI_STATUS\r |
143 | EFIAPI\r |
144 | DisableInterruptSource (\r |
145 | IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,\r |
146 | IN HARDWARE_INTERRUPT_SOURCE Source\r |
147 | )\r |
148 | {\r |
149 | UINT32 RegOffset;\r |
150 | UINTN RegShift;\r |
151 | \r |
152 | if (Source > mGicNumInterrupts) {\r |
153 | ASSERT(FALSE);\r |
154 | return EFI_UNSUPPORTED;\r |
155 | }\r |
156 | \r |
157 | // Calculate enable register offset and bit position\r |
158 | RegOffset = Source / 32;\r |
159 | RegShift = Source % 32;\r |
160 | \r |
161 | // Write set-enable register\r |
162 | MmioWrite32 (PcdGet32(PcdGicDistributorBase) + ARM_GIC_ICDICER + (4*RegOffset), 1 << RegShift);\r |
163 | \r |
164 | return EFI_SUCCESS;\r |
165 | }\r |
166 | \r |
167 | /**\r |
168 | Return current state of interrupt source Source.\r |
169 | \r |
170 | @param This Instance pointer for this protocol\r |
171 | @param Source Hardware source of the interrupt\r |
172 | @param InterruptState TRUE: source enabled, FALSE: source disabled.\r |
173 | \r |
174 | @retval EFI_SUCCESS InterruptState is valid\r |
175 | @retval EFI_DEVICE_ERROR InterruptState is not valid\r |
176 | \r |
177 | **/\r |
178 | EFI_STATUS\r |
179 | EFIAPI\r |
180 | GetInterruptSourceState (\r |
181 | IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,\r |
182 | IN HARDWARE_INTERRUPT_SOURCE Source,\r |
183 | IN BOOLEAN *InterruptState\r |
184 | )\r |
185 | {\r |
186 | UINT32 RegOffset;\r |
187 | UINTN RegShift;\r |
188 | \r |
189 | if (Source > mGicNumInterrupts) {\r |
190 | ASSERT(FALSE);\r |
191 | return EFI_UNSUPPORTED;\r |
192 | }\r |
193 | \r |
194 | // calculate enable register offset and bit position\r |
195 | RegOffset = Source / 32;\r |
196 | RegShift = Source % 32;\r |
197 | \r |
198 | if ((MmioRead32 (PcdGet32(PcdGicDistributorBase) + ARM_GIC_ICDISER + (4*RegOffset)) & (1<<RegShift)) == 0) {\r |
199 | *InterruptState = FALSE;\r |
200 | } else {\r |
201 | *InterruptState = TRUE;\r |
202 | }\r |
203 | \r |
204 | return EFI_SUCCESS;\r |
205 | }\r |
206 | \r |
207 | /**\r |
208 | Signal to the hardware that the End Of Intrrupt state \r |
209 | has been reached.\r |
210 | \r |
211 | @param This Instance pointer for this protocol\r |
212 | @param Source Hardware source of the interrupt\r |
213 | \r |
214 | @retval EFI_SUCCESS Source interrupt EOI'ed.\r |
215 | @retval EFI_DEVICE_ERROR Hardware could not be programmed.\r |
216 | \r |
217 | **/\r |
218 | EFI_STATUS\r |
219 | EFIAPI\r |
220 | EndOfInterrupt (\r |
221 | IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,\r |
222 | IN HARDWARE_INTERRUPT_SOURCE Source\r |
223 | )\r |
224 | {\r |
225 | if (Source > mGicNumInterrupts) {\r |
226 | ASSERT(FALSE);\r |
227 | return EFI_UNSUPPORTED;\r |
228 | }\r |
229 | \r |
230 | MmioWrite32 (PcdGet32(PcdGicInterruptInterfaceBase) + ARM_GIC_ICCEIOR, Source);\r |
231 | return EFI_SUCCESS;\r |
232 | }\r |
233 | \r |
234 | /**\r |
235 | EFI_CPU_INTERRUPT_HANDLER that is called when a processor interrupt occurs.\r |
236 | \r |
237 | @param InterruptType Defines the type of interrupt or exception that\r |
238 | occurred on the processor.This parameter is processor architecture specific.\r |
239 | @param SystemContext A pointer to the processor context when\r |
240 | the interrupt occurred on the processor.\r |
241 | \r |
242 | @return None\r |
243 | \r |
244 | **/\r |
245 | VOID\r |
246 | EFIAPI\r |
247 | IrqInterruptHandler (\r |
248 | IN EFI_EXCEPTION_TYPE InterruptType,\r |
249 | IN EFI_SYSTEM_CONTEXT SystemContext\r |
250 | )\r |
251 | {\r |
252 | UINT32 GicInterrupt;\r |
253 | HARDWARE_INTERRUPT_HANDLER InterruptHandler;\r |
254 | \r |
255 | GicInterrupt = MmioRead32 (PcdGet32(PcdGicInterruptInterfaceBase) + ARM_GIC_ICCIAR);\r |
256 | \r |
257 | // Special Interrupts (ID1020-ID1023) have an Interrupt ID greater than the number of interrupt (ie: Spurious interrupt).\r |
258 | if (GicInterrupt >= mGicNumInterrupts) {\r |
259 | // The special interrupt do not need to be acknowledge\r |
260 | return;\r |
261 | }\r |
262 | \r |
263 | InterruptHandler = gRegisteredInterruptHandlers[GicInterrupt];\r |
264 | if (InterruptHandler != NULL) {\r |
265 | // Call the registered interrupt handler.\r |
266 | InterruptHandler (GicInterrupt, SystemContext);\r |
267 | } else {\r |
268 | DEBUG ((EFI_D_ERROR, "Spurious GIC interrupt: 0x%x\n", GicInterrupt));\r |
269 | }\r |
270 | \r |
271 | EndOfInterrupt (&gHardwareInterruptProtocol, GicInterrupt);\r |
272 | }\r |
273 | \r |
274 | //\r |
275 | // Making this global saves a few bytes in image size\r |
276 | //\r |
277 | EFI_HANDLE gHardwareInterruptHandle = NULL;\r |
278 | \r |
279 | //\r |
280 | // The protocol instance produced by this driver\r |
281 | //\r |
282 | EFI_HARDWARE_INTERRUPT_PROTOCOL gHardwareInterruptProtocol = {\r |
283 | RegisterInterruptSource,\r |
284 | EnableInterruptSource,\r |
285 | DisableInterruptSource,\r |
286 | GetInterruptSourceState,\r |
287 | EndOfInterrupt\r |
288 | };\r |
289 | \r |
290 | /**\r |
291 | Shutdown our hardware\r |
292 | \r |
293 | DXE Core will disable interrupts and turn off the timer and disable interrupts\r |
294 | after all the event handlers have run.\r |
295 | \r |
296 | @param[in] Event The Event that is being processed\r |
297 | @param[in] Context Event Context\r |
298 | **/\r |
299 | VOID\r |
300 | EFIAPI\r |
301 | ExitBootServicesEvent (\r |
302 | IN EFI_EVENT Event,\r |
303 | IN VOID *Context\r |
304 | )\r |
305 | {\r |
306 | UINTN Index;\r |
307 | \r |
308 | // Acknowledge all pending interrupts\r |
309 | for (Index = 0; Index < mGicNumInterrupts; Index++) {\r |
310 | DisableInterruptSource (&gHardwareInterruptProtocol, Index);\r |
311 | }\r |
312 | \r |
313 | for (Index = 0; Index < mGicNumInterrupts; Index++) {\r |
314 | EndOfInterrupt (&gHardwareInterruptProtocol, Index);\r |
315 | }\r |
316 | \r |
317 | // Disable Gic Interface\r |
318 | MmioWrite32 (PcdGet32(PcdGicInterruptInterfaceBase) + ARM_GIC_ICCICR, 0x0);\r |
319 | MmioWrite32 (PcdGet32(PcdGicInterruptInterfaceBase) + ARM_GIC_ICCPMR, 0x0);\r |
320 | \r |
321 | // Disable Gic Distributor\r |
322 | MmioWrite32 (PcdGet32(PcdGicDistributorBase) + ARM_GIC_ICDDCR, 0x0);\r |
323 | }\r |
324 | \r |
325 | /**\r |
326 | Initialize the state information for the CPU Architectural Protocol\r |
327 | \r |
328 | @param ImageHandle of the loaded driver\r |
329 | @param SystemTable Pointer to the System Table\r |
330 | \r |
331 | @retval EFI_SUCCESS Protocol registered\r |
332 | @retval EFI_OUT_OF_RESOURCES Cannot allocate protocol data structure\r |
333 | @retval EFI_DEVICE_ERROR Hardware problems\r |
334 | \r |
335 | **/\r |
336 | EFI_STATUS\r |
337 | InterruptDxeInitialize (\r |
338 | IN EFI_HANDLE ImageHandle,\r |
339 | IN EFI_SYSTEM_TABLE *SystemTable\r |
340 | )\r |
341 | {\r |
342 | EFI_STATUS Status;\r |
343 | UINTN Index;\r |
344 | UINT32 RegOffset;\r |
345 | UINTN RegShift;\r |
346 | EFI_CPU_ARCH_PROTOCOL *Cpu;\r |
347 | UINT32 CpuTarget;\r |
348 | \r |
349 | // Check PcdGicPrimaryCoreId has been set in case the Primary Core is not the core 0 of Cluster 0\r |
350 | DEBUG_CODE_BEGIN();\r |
351 | if ((PcdGet32(PcdArmPrimaryCore) != 0) && (PcdGet32 (PcdGicPrimaryCoreId) == 0)) {\r |
352 | DEBUG((EFI_D_WARN,"Warning: the PCD PcdGicPrimaryCoreId does not seem to be set up for the configuration.\n"));\r |
353 | }\r |
354 | DEBUG_CODE_END();\r |
355 | \r |
356 | // Make sure the Interrupt Controller Protocol is not already installed in the system.\r |
357 | ASSERT_PROTOCOL_ALREADY_INSTALLED (NULL, &gHardwareInterruptProtocolGuid);\r |
358 | \r |
359 | mGicNumInterrupts = ArmGicGetMaxNumInterrupts (PcdGet32(PcdGicDistributorBase));\r |
360 | \r |
361 | for (Index = 0; Index < mGicNumInterrupts; Index++) {\r |
362 | DisableInterruptSource (&gHardwareInterruptProtocol, Index);\r |
363 | \r |
364 | // Set Priority \r |
365 | RegOffset = Index / 4;\r |
366 | RegShift = (Index % 4) * 8;\r |
367 | MmioAndThenOr32 (\r |
368 | PcdGet32(PcdGicDistributorBase) + ARM_GIC_ICDIPR + (4*RegOffset),\r |
369 | ~(0xff << RegShift), \r |
370 | ARM_GIC_DEFAULT_PRIORITY << RegShift\r |
371 | );\r |
372 | }\r |
373 | \r |
374 | // Configure interrupts for Primary Cpu\r |
375 | CpuTarget = (1 << PcdGet32 (PcdGicPrimaryCoreId));\r |
376 | CpuTarget |= (CpuTarget << 24) | (CpuTarget << 16) | (CpuTarget << 8);\r |
377 | for (Index = 0; Index < (mGicNumInterrupts / 4); Index++) {\r |
378 | MmioWrite32 (PcdGet32(PcdGicDistributorBase) + ARM_GIC_ICDIPTR + (Index*4), CpuTarget);\r |
379 | }\r |
380 | \r |
381 | // Set binary point reg to 0x7 (no preemption)\r |
382 | MmioWrite32 (PcdGet32(PcdGicInterruptInterfaceBase) + ARM_GIC_ICCBPR, 0x7);\r |
383 | \r |
384 | // Set priority mask reg to 0xff to allow all priorities through\r |
385 | MmioWrite32 (PcdGet32(PcdGicInterruptInterfaceBase) + ARM_GIC_ICCPMR, 0xff);\r |
386 | \r |
387 | // Enable gic cpu interface\r |
388 | MmioWrite32 (PcdGet32(PcdGicInterruptInterfaceBase) + ARM_GIC_ICCICR, 0x1);\r |
389 | \r |
390 | // Enable gic distributor\r |
391 | MmioWrite32 (PcdGet32(PcdGicDistributorBase) + ARM_GIC_ICDDCR, 0x1);\r |
392 | \r |
393 | // Initialize the array for the Interrupt Handlers\r |
394 | gRegisteredInterruptHandlers = (HARDWARE_INTERRUPT_HANDLER*)AllocateZeroPool (sizeof(HARDWARE_INTERRUPT_HANDLER) * mGicNumInterrupts);\r |
395 | \r |
396 | Status = gBS->InstallMultipleProtocolInterfaces (\r |
397 | &gHardwareInterruptHandle,\r |
398 | &gHardwareInterruptProtocolGuid, &gHardwareInterruptProtocol,\r |
399 | NULL\r |
400 | );\r |
401 | ASSERT_EFI_ERROR (Status);\r |
402 | \r |
403 | //\r |
404 | // Get the CPU protocol that this driver requires.\r |
405 | //\r |
406 | Status = gBS->LocateProtocol(&gEfiCpuArchProtocolGuid, NULL, (VOID **)&Cpu);\r |
407 | ASSERT_EFI_ERROR(Status);\r |
408 | \r |
409 | //\r |
410 | // Unregister the default exception handler.\r |
411 | //\r |
111339d2 |
412 | Status = Cpu->RegisterInterruptHandler(Cpu, ARM_ARCH_EXCEPTION_IRQ, NULL);\r |
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413 | ASSERT_EFI_ERROR(Status);\r |
414 | \r |
415 | //\r |
416 | // Register to receive interrupts\r |
417 | //\r |
111339d2 |
418 | Status = Cpu->RegisterInterruptHandler(Cpu, ARM_ARCH_EXCEPTION_IRQ, IrqInterruptHandler);\r |
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419 | ASSERT_EFI_ERROR(Status);\r |
420 | \r |
421 | // Register for an ExitBootServicesEvent\r |
422 | Status = gBS->CreateEvent (EVT_SIGNAL_EXIT_BOOT_SERVICES, TPL_NOTIFY, ExitBootServicesEvent, NULL, &EfiExitBootServicesEvent);\r |
423 | ASSERT_EFI_ERROR (Status);\r |
424 | \r |
425 | return Status;\r |
426 | }\r |