Sync up ArmPkg with patch from mailing list. Changed name of BdsLib.h to BdsUnixLib...
[mirror_edk2.git] / ArmPkg / Drivers / PL390Gic / PL390GicNonSec.c
CommitLineData
1bfda055 1/** @file\r
2*\r
3* Copyright (c) 2011, ARM Limited. All rights reserved.\r
4* \r
5* This program and the accompanying materials \r
6* are licensed and made available under the terms and conditions of the BSD License \r
7* which accompanies this distribution. The full text of the license may be found at \r
8* http://opensource.org/licenses/bsd-license.php \r
9*\r
10* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
11* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
12*\r
13**/\r
14\r
15#include <Library/IoLib.h>\r
16#include <Drivers/PL390Gic.h>\r
17\r
18\r
19VOID\r
20EFIAPI\r
21PL390GicEnableInterruptInterface (\r
22 IN INTN GicInterruptInterfaceBase\r
23 )\r
24{ \r
25 /*\r
26 * Enable the CPU interface in Non-Secure world\r
27 * Note: The ICCICR register is banked when Security extensions are implemented \r
28 */\r
29 MmioWrite32(GicInterruptInterfaceBase + GIC_ICCICR,0x00000001);\r
30}\r
31\r
32VOID\r
33EFIAPI\r
34PL390GicEnableDistributor (\r
35 IN INTN GicDistributorBase\r
36 )\r
37{\r
38 /*\r
39 * Enable GIC distributor in Non-Secure world.\r
40 * Note: The ICDDCR register is banked when Security extensions are implemented\r
41 */\r
42 MmioWrite32(GicDistributorBase + GIC_ICDDCR, 0x00000001);\r
43}\r
44\r
45VOID\r
46EFIAPI\r
47PL390GicSendSgiTo (\r
48 IN INTN GicDistributorBase,\r
49 IN INTN TargetListFilter,\r
50 IN INTN CPUTargetList\r
51 )\r
52{\r
53 MmioWrite32(GicDistributorBase + GIC_ICDSGIR, ((TargetListFilter & 0x3) << 24) | ((CPUTargetList & 0xFF) << 16));\r
54}\r
55\r
56UINT32\r
57EFIAPI\r
58PL390GicAcknowledgeSgiFrom (\r
59 IN INTN GicInterruptInterfaceBase,\r
60 IN INTN CoreId\r
61 )\r
62{\r
63 INTN InterruptId;\r
64\r
65 InterruptId = MmioRead32(GicInterruptInterfaceBase + GIC_ICCIAR);\r
66\r
67 //Check if the Interrupt ID is valid, The read from Interrupt Ack register returns CPU ID and Interrupt ID\r
68 if (((CoreId & 0x7) << 10) == (InterruptId & 0x1C00)) {\r
69 //Got SGI number 0 hence signal End of Interrupt by writing to ICCEOIR\r
70 MmioWrite32(GicInterruptInterfaceBase + GIC_ICCEIOR, InterruptId);\r
71 return 1;\r
72 } else {\r
73 return 0;\r
74 }\r
75}\r
76\r
77UINT32\r
78EFIAPI\r
79PL390GicAcknowledgeSgi2From (\r
80 IN INTN GicInterruptInterfaceBase,\r
81 IN INTN CoreId,\r
82 IN INTN SgiId\r
83 )\r
84{\r
85 INTN InterruptId;\r
86\r
87 InterruptId = MmioRead32(GicInterruptInterfaceBase + GIC_ICCIAR);\r
88\r
89 //Check if the Interrupt ID is valid, The read from Interrupt Ack register returns CPU ID and Interrupt ID\r
90 if((((CoreId & 0x7) << 10) | (SgiId & 0x3FF)) == (InterruptId & 0x1FFF)) {\r
91 //Got SGI number 0 hence signal End of Interrupt by writing to ICCEOIR\r
92 MmioWrite32(GicInterruptInterfaceBase + GIC_ICCEIOR, InterruptId);\r
93 return 1;\r
94 } else {\r
95 return 0;\r
96 }\r
97}\r