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1 | /** @file\r |
2 | *\r |
3 | * Copyright (c) 2011, ARM Limited. All rights reserved.\r |
4 | * \r |
5 | * This program and the accompanying materials \r |
6 | * are licensed and made available under the terms and conditions of the BSD License \r |
7 | * which accompanies this distribution. The full text of the license may be found at \r |
8 | * http://opensource.org/licenses/bsd-license.php \r |
9 | *\r |
10 | * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r |
11 | * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r |
12 | *\r |
13 | **/\r |
14 | \r |
15 | #include <Library/IoLib.h>\r |
16 | #include <Drivers/PL390Gic.h>\r |
17 | \r |
18 | /*\r |
19 | * This function configures the all interrupts to be Non-secure.\r |
20 | *\r |
21 | */\r |
22 | VOID\r |
23 | EFIAPI\r |
24 | PL390GicSetupNonSecure (\r |
25 | IN INTN GicDistributorBase,\r |
26 | IN INTN GicInterruptInterfaceBase\r |
27 | )\r |
28 | {\r |
29 | UINTN CachedPriorityMask = MmioRead32(GicInterruptInterfaceBase + GIC_ICCPMR);\r |
30 | \r |
31 | //Set priority Mask so that no interrupts get through to CPU\r |
32 | MmioWrite32(GicInterruptInterfaceBase + GIC_ICCPMR, 0);\r |
33 | \r |
34 | //Check if there are any pending interrupts\r |
35 | while(0 != (MmioRead32(GicDistributorBase + GIC_ICDICPR) & 0xF))\r |
36 | {\r |
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37 | //Some of the SGI's are still pending, read Ack register and send End of Interrupt Signal\r |
38 | UINTN InterruptId = MmioRead32(GicInterruptInterfaceBase + GIC_ICCIAR);\r |
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39 | \r |
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40 | //Write to End of interrupt signal\r |
41 | MmioWrite32(GicInterruptInterfaceBase + GIC_ICCEIOR, InterruptId);\r |
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42 | }\r |
43 | \r |
44 | // Ensure all GIC interrupts are Non-Secure\r |
45 | MmioWrite32(GicDistributorBase + GIC_ICDISR, 0xffffffff); // IRQs 0-31 are Non-Secure : Private Peripheral Interrupt[31:16] & Software Generated Interrupt[15:0]\r |
46 | MmioWrite32(GicDistributorBase + GIC_ICDISR + 4, 0xffffffff); // IRQs 32-63 are Non-Secure : Shared Peripheral Interrupt\r |
47 | MmioWrite32(GicDistributorBase + GIC_ICDISR + 8, 0xffffffff); // And another 32 in case we're on the testchip : Shared Peripheral Interrupt (2)\r |
48 | \r |
49 | // Ensure all interrupts can get through the priority mask\r |
50 | MmioWrite32(GicInterruptInterfaceBase + GIC_ICCPMR, CachedPriorityMask);\r |
51 | }\r |
52 | \r |
53 | VOID\r |
54 | EFIAPI\r |
55 | PL390GicEnableInterruptInterface (\r |
56 | IN INTN GicInterruptInterfaceBase\r |
57 | )\r |
58 | {\r |
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59 | MmioWrite32(GicInterruptInterfaceBase + GIC_ICCPMR, 0x000000FF); /* Set Priority Mask to allow interrupts */\r |
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60 | \r |
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61 | /*\r |
62 | * Enable CPU interface in Secure world\r |
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63 | * Enable CPU inteface in Non-secure World\r |
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64 | * Signal Secure Interrupts to CPU using FIQ line *\r |
65 | */\r |
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66 | MmioWrite32(GicInterruptInterfaceBase + GIC_ICCICR,\r |
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67 | GIC_ICCICR_ENABLE_SECURE(1) |\r |
68 | GIC_ICCICR_ENABLE_NS(1) |\r |
69 | GIC_ICCICR_ACK_CTL(0) |\r |
70 | GIC_ICCICR_SIGNAL_SECURE_TO_FIQ(1) |\r |
71 | GIC_ICCICR_USE_SBPR(0));\r |
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72 | }\r |
73 | \r |
74 | VOID\r |
75 | EFIAPI\r |
76 | PL390GicEnableDistributor (\r |
77 | IN INTN GicDistributorBase\r |
78 | )\r |
79 | {\r |
80 | MmioWrite32(GicDistributorBase + GIC_ICDDCR, 1); // turn on the GIC distributor\r |
81 | }\r |
82 | \r |
83 | VOID\r |
84 | EFIAPI\r |
85 | PL390GicSendSgiTo (\r |
86 | IN INTN GicDistributorBase,\r |
87 | IN INTN TargetListFilter,\r |
88 | IN INTN CPUTargetList\r |
89 | )\r |
90 | {\r |
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91 | MmioWrite32(GicDistributorBase + GIC_ICDSGIR, ((TargetListFilter & 0x3) << 24) | ((CPUTargetList & 0xFF) << 16));\r |
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92 | }\r |
93 | \r |
94 | UINT32\r |
95 | EFIAPI\r |
96 | PL390GicAcknowledgeSgiFrom (\r |
97 | IN INTN GicInterruptInterfaceBase,\r |
98 | IN INTN CoreId\r |
99 | )\r |
100 | {\r |
101 | INTN InterruptId;\r |
102 | \r |
103 | InterruptId = MmioRead32(GicInterruptInterfaceBase + GIC_ICCIAR);\r |
104 | \r |
105 | //Check if the Interrupt ID is valid, The read from Interrupt Ack register returns CPU ID and Interrupt ID\r |
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106 | if (((CoreId & 0x7) << 10) == (InterruptId & 0x1C00)) {\r |
107 | //Got SGI number 0 hence signal End of Interrupt by writing to ICCEOIR\r |
108 | MmioWrite32(GicInterruptInterfaceBase + GIC_ICCEIOR, InterruptId);\r |
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109 | return 1;\r |
110 | } else {\r |
111 | return 0;\r |
112 | }\r |
113 | }\r |
114 | \r |
115 | UINT32\r |
116 | EFIAPI\r |
117 | PL390GicAcknowledgeSgi2From (\r |
118 | IN INTN GicInterruptInterfaceBase,\r |
119 | IN INTN CoreId,\r |
120 | IN INTN SgiId\r |
121 | )\r |
122 | {\r |
123 | INTN InterruptId;\r |
124 | \r |
125 | InterruptId = MmioRead32(GicInterruptInterfaceBase + GIC_ICCIAR);\r |
126 | \r |
127 | //Check if the Interrupt ID is valid, The read from Interrupt Ack register returns CPU ID and Interrupt ID\r |
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128 | if((((CoreId & 0x7) << 10) | (SgiId & 0x3FF)) == (InterruptId & 0x1FFF)) {\r |
129 | //Got SGI number 0 hence signal End of Interrupt by writing to ICCEOIR\r |
130 | MmioWrite32(GicInterruptInterfaceBase + GIC_ICCEIOR, InterruptId);\r |
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131 | return 1;\r |
132 | } else {\r |
133 | return 0;\r |
134 | }\r |
135 | }\r |