ArmPkg: Renamed library 'PL390GicLib' into 'ArmGicLib'

[mirror_edk2.git] / ArmPkg / Drivers / PL390Gic / PL390GicSec.c

/** @file\r
*\r
*  Copyright (c) 2011, ARM Limited. All rights reserved.\r
*  \r
*  This program and the accompanying materials                          \r
*  are licensed and made available under the terms and conditions of the BSD License         \r
*  which accompanies this distribution.  The full text of the license may be found at        \r
*  http://opensource.org/licenses/bsd-license.php                                            \r
*\r
*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     \r
*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             \r
*\r
**/\r
\r
#include <Uefi.h>\r
#include <Library/IoLib.h>\r
#include <Library/ArmGicLib.h>\r
\r
/*\r
 * This function configures the all interrupts to be Non-secure.\r
 *\r
 */\r
VOID\r
EFIAPI\r
ArmGicSetupNonSecure (\r
  IN  INTN          GicDistributorBase,\r
  IN  INTN          GicInterruptInterfaceBase\r
  )\r
{\r
  UINTN CachedPriorityMask = MmioRead32(GicInterruptInterfaceBase + ARM_GIC_ICCPMR);\r
\r
  // Set priority Mask so that no interrupts get through to CPU\r
  MmioWrite32(GicInterruptInterfaceBase + ARM_GIC_ICCPMR, 0);\r
\r
  // Check if there are any pending interrupts\r
  //TODO: could be extended to take Peripheral interrupts into consideration, but at the moment only SGI's are taken into consideration.\r
  while(0 != (MmioRead32(GicDistributorBase + ARM_GIC_ICDICPR) & 0xF)) {\r
    // Some of the SGI's are still pending, read Ack register and send End of Interrupt Signal\r
    UINTN InterruptId = MmioRead32(GicInterruptInterfaceBase + ARM_GIC_ICCIAR);\r
\r
    // Write to End of interrupt signal\r
    MmioWrite32(GicInterruptInterfaceBase + ARM_GIC_ICCEIOR, InterruptId);\r
  }\r
\r
  // Ensure all GIC interrupts are Non-Secure\r
  MmioWrite32(GicDistributorBase + ARM_GIC_ICDISR, 0xffffffff);     // IRQs  0-31 are Non-Secure : Private Peripheral Interrupt[31:16] & Software Generated Interrupt[15:0]\r
  MmioWrite32(GicDistributorBase + ARM_GIC_ICDISR + 4, 0xffffffff); // IRQs 32-63 are Non-Secure : Shared Peripheral Interrupt\r
  MmioWrite32(GicDistributorBase + ARM_GIC_ICDISR + 8, 0xffffffff); // And another 32 in case we're on the testchip : Shared Peripheral Interrupt (2)\r
\r
  // Ensure all interrupts can get through the priority mask\r
  MmioWrite32(GicInterruptInterfaceBase + ARM_GIC_ICCPMR, CachedPriorityMask);\r
}\r
\r
VOID\r
EFIAPI\r
ArmGicEnableInterruptInterface (\r
  IN  INTN          GicInterruptInterfaceBase\r
  )\r
{\r
  MmioWrite32(GicInterruptInterfaceBase + ARM_GIC_ICCPMR, 0x000000FF);  /* Set Priority Mask to allow interrupts */\r
\r
  /*\r
   * Enable CPU interface in Secure world\r
     * Enable CPU inteface in Non-secure World\r
   * Signal Secure Interrupts to CPU using FIQ line *\r
   */\r
  MmioWrite32(GicInterruptInterfaceBase + ARM_GIC_ICCICR,\r
      ARM_GIC_ICCICR_ENABLE_SECURE |\r
      ARM_GIC_ICCICR_ENABLE_NS |\r
      ARM_GIC_ICCICR_SIGNAL_SECURE_TO_FIQ);\r
}\r
\r
VOID\r
EFIAPI\r
ArmGicEnableDistributor (\r
  IN  INTN          GicDistributorBase\r
  )\r
{\r
  MmioWrite32(GicDistributorBase + ARM_GIC_ICDDCR, 1);               // turn on the GIC distributor\r
}\r