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[mirror_edk2.git] / ArmPkg / Drivers / PL390Gic / PL390GicSec.c

/** @file\r
*\r
*  Copyright (c) 2011, ARM Limited. All rights reserved.\r
*  \r
*  This program and the accompanying materials                          \r
*  are licensed and made available under the terms and conditions of the BSD License         \r
*  which accompanies this distribution.  The full text of the license may be found at        \r
*  http://opensource.org/licenses/bsd-license.php                                            \r
*\r
*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     \r
*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             \r
*\r
**/\r
\r
#include <Library/IoLib.h>\r
#include <Drivers/PL390Gic.h>\r
\r
/*\r
 * This function configures the all interrupts to be Non-secure.\r
 *\r
 */\r
VOID\r
EFIAPI\r
PL390GicSetupNonSecure (\r
  IN  INTN          GicDistributorBase,\r
  IN  INTN          GicInterruptInterfaceBase\r
  )\r
{\r
   UINTN CachedPriorityMask = MmioRead32(GicInterruptInterfaceBase + GIC_ICCPMR);\r
\r
   //Set priority Mask so that no interrupts get through to CPU\r
   MmioWrite32(GicInterruptInterfaceBase + GIC_ICCPMR, 0);\r
\r
   //Check if there are any pending interrupts\r
   while(0 != (MmioRead32(GicDistributorBase + GIC_ICDICPR) & 0xF))\r
   {\r
\s\s   //Some of the SGI's are still pending, read Ack register and send End of Interrupt Signal\r
\s\s   UINTN InterruptId = MmioRead32(GicInterruptInterfaceBase + GIC_ICCIAR);\r
\r
\s\s   //Write to End of interrupt signal\r
\s\s   MmioWrite32(GicInterruptInterfaceBase + GIC_ICCEIOR, InterruptId);\r
   }\r
\r
  // Ensure all GIC interrupts are Non-Secure\r
   MmioWrite32(GicDistributorBase + GIC_ICDISR, 0xffffffff);     // IRQs  0-31 are Non-Secure : Private Peripheral Interrupt[31:16] & Software Generated Interrupt[15:0]\r
   MmioWrite32(GicDistributorBase + GIC_ICDISR + 4, 0xffffffff); // IRQs 32-63 are Non-Secure : Shared Peripheral Interrupt\r
   MmioWrite32(GicDistributorBase + GIC_ICDISR + 8, 0xffffffff); // And another 32 in case we're on the testchip : Shared Peripheral Interrupt (2)\r
\r
  // Ensure all interrupts can get through the priority mask\r
   MmioWrite32(GicInterruptInterfaceBase + GIC_ICCPMR, CachedPriorityMask);\r
}\r
\r
VOID\r
EFIAPI\r
PL390GicEnableInterruptInterface (\r
  IN  INTN          GicInterruptInterfaceBase\r
  )\r
{\r
\s\sMmioWrite32(GicInterruptInterfaceBase + GIC_ICCPMR, 0x000000FF);  /* Set Priority Mask to allow interrupts */\r
\r
\s\s/*\r
\s\s * Enable CPU interface in Secure world\r
     * Enable CPU inteface in Non-secure World\r
\s\s * Signal Secure Interrupts to CPU using FIQ line *\r
\s\s */\r
    MmioWrite32(GicInterruptInterfaceBase + GIC_ICCICR,\r
    \s\s\s\sGIC_ICCICR_ENABLE_SECURE(1) |\r
    \s\s\s\sGIC_ICCICR_ENABLE_NS(1) |\r
    \s\s\s\sGIC_ICCICR_ACK_CTL(0) |\r
    \s\s\s\sGIC_ICCICR_SIGNAL_SECURE_TO_FIQ(1) |\r
    \s\s\s\sGIC_ICCICR_USE_SBPR(0));\r
}\r
\r
VOID\r
EFIAPI\r
PL390GicEnableDistributor (\r
  IN  INTN          GicDistributorBase\r
  )\r
{\r
    MmioWrite32(GicDistributorBase + GIC_ICDDCR, 1);               // turn on the GIC distributor\r
}\r
\r
VOID\r
EFIAPI\r
PL390GicSendSgiTo (\r
  IN  INTN          GicDistributorBase,\r
  IN  INTN          TargetListFilter,\r
  IN  INTN          CPUTargetList\r
  )\r
{\r
\s\sMmioWrite32(GicDistributorBase + GIC_ICDSGIR, ((TargetListFilter & 0x3) << 24) | ((CPUTargetList & 0xFF) << 16));\r
}\r
\r
UINT32\r
EFIAPI\r
PL390GicAcknowledgeSgiFrom (\r
  IN  INTN          GicInterruptInterfaceBase,\r
  IN  INTN          CoreId\r
  )\r
{\r
    INTN            InterruptId;\r
\r
    InterruptId = MmioRead32(GicInterruptInterfaceBase + GIC_ICCIAR);\r
\r
    //Check if the Interrupt ID is valid, The read from Interrupt Ack register returns CPU ID and Interrupt ID\r
\s\sif (((CoreId & 0x7) << 10) == (InterruptId & 0x1C00)) {\r
\s\s    //Got SGI number 0 hence signal End of Interrupt by writing to ICCEOIR\r
\s\s\s\sMmioWrite32(GicInterruptInterfaceBase + GIC_ICCEIOR, InterruptId);\r
        return 1;\r
    } else {\r
        return 0;\r
    }\r
}\r
\r
UINT32\r
EFIAPI\r
PL390GicAcknowledgeSgi2From (\r
  IN  INTN          GicInterruptInterfaceBase,\r
  IN  INTN          CoreId,\r
  IN  INTN          SgiId\r
  )\r
{\r
    INTN            InterruptId;\r
\r
    InterruptId = MmioRead32(GicInterruptInterfaceBase + GIC_ICCIAR);\r
\r
    //Check if the Interrupt ID is valid, The read from Interrupt Ack register returns CPU ID and Interrupt ID\r
\s\sif((((CoreId & 0x7) << 10) | (SgiId & 0x3FF)) == (InterruptId & 0x1FFF)) {\r
\s\s    //Got SGI number 0 hence signal End of Interrupt by writing to ICCEOIR\r
\s\s\s\sMmioWrite32(GicInterruptInterfaceBase + GIC_ICCEIOR, InterruptId);\r
        return 1;\r
    } else {\r
        return 0;\r
    }\r
}\r