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1 | /** @file\r |
2 | *\r |
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3 | * Copyright (c) 2011-2012, ARM Limited. All rights reserved.\r |
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4 | * \r |
5 | * This program and the accompanying materials \r |
6 | * are licensed and made available under the terms and conditions of the BSD License \r |
7 | * which accompanies this distribution. The full text of the license may be found at \r |
8 | * http://opensource.org/licenses/bsd-license.php \r |
9 | *\r |
10 | * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r |
11 | * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r |
12 | *\r |
13 | **/\r |
14 | \r |
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15 | #include <Base.h>\r |
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16 | #include <Library/ArmLib.h>\r |
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17 | #include <Library/DebugLib.h>\r |
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18 | #include <Library/IoLib.h>\r |
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19 | #include <Library/ArmGicLib.h>\r |
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20 | \r |
21 | /*\r |
22 | * This function configures the all interrupts to be Non-secure.\r |
23 | *\r |
24 | */\r |
25 | VOID\r |
26 | EFIAPI\r |
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27 | ArmGicSetupNonSecure (\r |
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28 | IN UINTN MpId,\r |
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29 | IN INTN GicDistributorBase,\r |
30 | IN INTN GicInterruptInterfaceBase\r |
31 | )\r |
32 | {\r |
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33 | UINTN InterruptId;\r |
34 | UINTN CachedPriorityMask;\r |
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35 | UINTN Index;\r |
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36 | \r |
37 | CachedPriorityMask = MmioRead32 (GicInterruptInterfaceBase + ARM_GIC_ICCPMR);\r |
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38 | \r |
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39 | // Set priority Mask so that no interrupts get through to CPU\r |
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40 | MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCPMR, 0);\r |
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41 | \r |
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42 | InterruptId = MmioRead32 (GicInterruptInterfaceBase + ARM_GIC_ICCIAR);\r |
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43 | \r |
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44 | // Only try to clear valid interrupts. Ignore spurious interrupts.\r |
45 | while ((InterruptId & 0x3FF) < ArmGicGetMaxNumInterrupts (GicDistributorBase)) {\r |
46 | // Some of the SGI's are still pending, read Ack register and send End of Interrupt Signal\r |
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47 | MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCEIOR, InterruptId);\r |
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48 | \r |
49 | // Next\r |
50 | InterruptId = MmioRead32 (GicInterruptInterfaceBase + ARM_GIC_ICCIAR);\r |
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51 | }\r |
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52 | \r |
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53 | // Only the primary core should set the Non Secure bit to the SPIs (Shared Peripheral Interrupt).\r |
54 | if (IS_PRIMARY_CORE(MpId)) {\r |
55 | // Ensure all GIC interrupts are Non-Secure\r |
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56 | for (Index = 0; Index < (ArmGicGetMaxNumInterrupts (GicDistributorBase) / 32); Index++) {\r |
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57 | MmioWrite32 (GicDistributorBase + ARM_GIC_ICDISR + (Index * 4), 0xffffffff);\r |
58 | }\r |
59 | } else {\r |
60 | // The secondary cores only set the Non Secure bit to their banked PPIs\r |
61 | MmioWrite32 (GicDistributorBase + ARM_GIC_ICDISR, 0xffffffff);\r |
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62 | }\r |
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63 | \r |
64 | // Ensure all interrupts can get through the priority mask\r |
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65 | MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCPMR, CachedPriorityMask);\r |
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66 | }\r |
67 | \r |
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68 | /*\r |
69 | * This function configures the interrupts set by the mask to be secure.\r |
70 | *\r |
71 | */\r |
72 | VOID\r |
73 | EFIAPI\r |
74 | ArmGicSetSecureInterrupts (\r |
75 | IN UINTN GicDistributorBase,\r |
76 | IN UINTN* GicSecureInterruptMask,\r |
77 | IN UINTN GicSecureInterruptMaskSize\r |
78 | )\r |
79 | {\r |
80 | UINTN Index;\r |
81 | UINT32 InterruptStatus;\r |
82 | \r |
83 | // We must not have more interrupts defined by the mask than the number of available interrupts\r |
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84 | ASSERT(GicSecureInterruptMaskSize <= (ArmGicGetMaxNumInterrupts (GicDistributorBase) / 32));\r |
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85 | \r |
86 | // Set all the interrupts defined by the mask as Secure\r |
87 | for (Index = 0; Index < GicSecureInterruptMaskSize; Index++) {\r |
88 | InterruptStatus = MmioRead32 (GicDistributorBase + ARM_GIC_ICDISR + (Index * 4));\r |
89 | MmioWrite32 (GicDistributorBase + ARM_GIC_ICDISR + (Index * 4), InterruptStatus & (~GicSecureInterruptMask[Index]));\r |
90 | }\r |
91 | }\r |
92 | \r |
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93 | VOID\r |
94 | EFIAPI\r |
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95 | ArmGicEnableInterruptInterface (\r |
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96 | IN INTN GicInterruptInterfaceBase\r |
97 | )\r |
98 | {\r |
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99 | // Set Priority Mask to allow interrupts\r |
100 | MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCPMR, 0x000000FF);\r |
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101 | \r |
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102 | // Enable CPU interface in Secure world\r |
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103 | // Enable CPU interface in Non-secure World\r |
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104 | // Signal Secure Interrupts to CPU using FIQ line *\r |
105 | MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCICR,\r |
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106 | ARM_GIC_ICCICR_ENABLE_SECURE |\r |
107 | ARM_GIC_ICCICR_ENABLE_NS |\r |
108 | ARM_GIC_ICCICR_SIGNAL_SECURE_TO_FIQ);\r |
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109 | }\r |
110 | \r |
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111 | VOID\r |
112 | EFIAPI\r |
113 | ArmGicDisableInterruptInterface (\r |
114 | IN INTN GicInterruptInterfaceBase\r |
115 | )\r |
116 | {\r |
117 | UINT32 ControlValue;\r |
118 | \r |
119 | // Disable CPU interface in Secure world and Non-secure World\r |
120 | ControlValue = MmioRead32 (GicInterruptInterfaceBase + ARM_GIC_ICCICR);\r |
121 | MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCICR, ControlValue & ~(ARM_GIC_ICCICR_ENABLE_SECURE | ARM_GIC_ICCICR_ENABLE_NS));\r |
122 | }\r |
123 | \r |
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124 | VOID\r |
125 | EFIAPI\r |
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126 | ArmGicEnableDistributor (\r |
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127 | IN INTN GicDistributorBase\r |
128 | )\r |
129 | {\r |
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130 | // Turn on the GIC distributor\r |
131 | MmioWrite32 (GicDistributorBase + ARM_GIC_ICDDCR, 1);\r |
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132 | }\r |