projects / mirror_edk2.git / blame
| Commit | Line | Data |
|---|---|---|
| 2ef2b01e A |
1 | ;%HEADER%\r |
| 2 | ;/** @file\r | |
| 3 | ; Macros to work around lack of Apple support for LDR register, =expr\r | |
| 4 | ;\r | |
| 5 | ; Copyright (c) 2009, Apple, Inc. All rights reserved.\r | |
| 6 | ;\r | |
| 7 | ;**/\r | |
| 8 | \r | |
| 9 | \r | |
| 10 | MACRO \r | |
| 11 | MmioWrite32Macro $Address, $Data \r | |
| 12 | ldr r1, = ($Address) \r | |
| 13 | ldr r0, = ($Data) \r | |
| 14 | str r0, [r1] \r | |
| 15 | MEND\r | |
| 16 | \r | |
| 17 | MACRO \r | |
| 18 | MmioOr32Macro $Address, $OrData \r | |
| 19 | ldr r1, =($Address) \r | |
| 20 | ldr r2, =($OrData) \r | |
| 21 | ldr r0, [r1] \r | |
| 22 | orr r0, r0, r2 \r | |
| 23 | str r0, [r1] \r | |
| 24 | MEND\r | |
| 25 | \r | |
| 26 | MACRO \r | |
| 27 | MmioAnd32Macro $Address, $AndData \r | |
| 28 | ldr r1, =($Address) \r | |
| 29 | ldr r2, =($AndData) \r | |
| 30 | ldr r0, [r1] \r | |
| 31 | and r0, r0, r2 \r | |
| 32 | str r0, [r1] \r | |
| 33 | MEND\r | |
| 34 | \r | |
| 35 | MACRO \r | |
| 36 | MmioAndThenOr32Macro $Address, $AndData, $OrData \r | |
| 37 | ldr r1, =($Address) \r | |
| 38 | ldr r0, [r1] \r | |
| 39 | ldr r2, =($AndData) \r | |
| 40 | and r0, r0, r2 \r | |
| 41 | ldr r2, =($OrData) \r | |
| 42 | orr r0, r0, r2 \r | |
| 43 | str r0, [r1] \r | |
| 44 | MEND\r | |
| 45 | \r | |
| 46 | MACRO \r | |
| 47 | MmioWriteFromReg32Macro $Address, $Reg \r | |
| 48 | ldr r1, =($Address) \r | |
| 49 | str $Reg, [r1] \r | |
| 50 | MEND\r | |
| 51 | \r | |
| 52 | MACRO \r | |
| 53 | MmioRead32Macro $Address \r | |
| 54 | ldr r1, =($Address) \r | |
| 55 | ldr r0, [r1] \r | |
| 56 | MEND\r | |
| 57 | \r | |
| 58 | MACRO \r | |
| 59 | MmioReadToReg32Macro $Address, $Reg \r | |
| 60 | ldr r1, =($Address) \r | |
| 61 | ldr $Reg, [r1] \r | |
| 62 | MEND\r | |
| 63 | \r | |
| 64 | MACRO \r | |
| 65 | LoadConstantMacro $Data \r | |
| 66 | ldr r0, =($Data) \r | |
| 67 | MEND\r | |
| 68 | \r | |
| 69 | MACRO \r | |
| 70 | LoadConstantToRegMacro $Data, $Reg \r | |
| 71 | ldr $Reg, =($Data) \r | |
| 72 | MEND \r | |
| 73 | \r | |
| 74 | END\r |