]>
Commit | Line | Data |
---|---|---|
25402f5d HL |
1 | /** @file\r |
2 | \r | |
3 | Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r | |
a4d95d7c | 4 | Copyright (c) 2011 - 2021, Arm Limited. All rights reserved.<BR>\r |
25402f5d | 5 | \r |
4059386c | 6 | SPDX-License-Identifier: BSD-2-Clause-Patent\r |
25402f5d HL |
7 | \r |
8 | **/\r | |
9 | \r | |
cc15a619 PG |
10 | #ifndef AARCH64_H_\r |
11 | #define AARCH64_H_\r | |
25402f5d HL |
12 | \r |
13 | #include <Chipset/AArch64Mmu.h>\r | |
25402f5d HL |
14 | \r |
15 | // ARM Interrupt ID in Exception Table\r | |
16 | #define ARM_ARCH_EXCEPTION_IRQ EXCEPT_AARCH64_IRQ\r | |
17 | \r | |
18 | // CPACR - Coprocessor Access Control Register definitions\r | |
19 | #define CPACR_TTA_EN (1UL << 28)\r | |
20 | #define CPACR_FPEN_EL1 (1UL << 20)\r | |
21 | #define CPACR_FPEN_FULL (3UL << 20)\r | |
22 | #define CPACR_CP_FULL_ACCESS 0x300000\r | |
23 | \r | |
24 | // Coprocessor Trap Register (CPTR)\r | |
25 | #define AARCH64_CPTR_TFP (1 << 10)\r | |
26 | \r | |
27 | // ID_AA64PFR0 - AArch64 Processor Feature Register 0 definitions\r | |
28 | #define AARCH64_PFR0_FP (0xF << 16)\r | |
27331bff | 29 | #define AARCH64_PFR0_GIC (0xF << 24)\r |
25402f5d | 30 | \r |
25402f5d HL |
31 | // SCR - Secure Configuration Register definitions\r |
32 | #define SCR_NS (1 << 0)\r | |
33 | #define SCR_IRQ (1 << 1)\r | |
34 | #define SCR_FIQ (1 << 2)\r | |
35 | #define SCR_EA (1 << 3)\r | |
36 | #define SCR_FW (1 << 4)\r | |
37 | #define SCR_AW (1 << 5)\r | |
38 | \r | |
39 | // MIDR - Main ID Register definitions\r | |
7aec2926 | 40 | #define ARM_CPU_TYPE_SHIFT 4\r |
25402f5d | 41 | #define ARM_CPU_TYPE_MASK 0xFFF\r |
a4d95d7c | 42 | #define ARM_CPU_TYPE_AEMV8 0xD0F\r |
b7dd4dbd OM |
43 | #define ARM_CPU_TYPE_A53 0xD03\r |
44 | #define ARM_CPU_TYPE_A57 0xD07\r | |
25654e24 | 45 | #define ARM_CPU_TYPE_A72 0xD08\r |
25402f5d HL |
46 | #define ARM_CPU_TYPE_A15 0xC0F\r |
47 | #define ARM_CPU_TYPE_A9 0xC09\r | |
7aec2926 | 48 | #define ARM_CPU_TYPE_A7 0xC07\r |
25402f5d HL |
49 | #define ARM_CPU_TYPE_A5 0xC05\r |
50 | \r | |
b7dd4dbd OM |
51 | #define ARM_CPU_REV_MASK ((0xF << 20) | (0xF) )\r |
52 | #define ARM_CPU_REV(rn, pn) ((((rn) & 0xF) << 20) | ((pn) & 0xF))\r | |
53 | \r | |
25402f5d | 54 | // Hypervisor Configuration Register\r |
6a44c227 OM |
55 | #define ARM_HCR_FMO BIT3\r |
56 | #define ARM_HCR_IMO BIT4\r | |
57 | #define ARM_HCR_AMO BIT5\r | |
58 | #define ARM_HCR_TSC BIT19\r | |
59 | #define ARM_HCR_TGE BIT27\r | |
25402f5d | 60 | \r |
f3c5066f OM |
61 | // Exception Syndrome Register\r |
62 | #define AARCH64_ESR_EC(Ecr) ((0x3F << 26) & (Ecr))\r | |
63 | #define AARCH64_ESR_ISS(Ecr) ((0x1FFFFFF) & (Ecr))\r | |
64 | \r | |
65 | #define AARCH64_ESR_EC_SMC32 (0x13 << 26)\r | |
66 | #define AARCH64_ESR_EC_SMC64 (0x17 << 26)\r | |
67 | \r | |
25402f5d HL |
68 | // AArch64 Exception Level\r |
69 | #define AARCH64_EL3 0xC\r | |
70 | #define AARCH64_EL2 0x8\r | |
71 | #define AARCH64_EL1 0x4\r | |
72 | \r | |
7e119c67 OM |
73 | // Saved Program Status Register definitions\r |
74 | #define SPSR_A BIT8\r | |
75 | #define SPSR_I BIT7\r | |
76 | #define SPSR_F BIT6\r | |
77 | \r | |
78 | #define SPSR_AARCH32 BIT4\r | |
79 | \r | |
80 | #define SPSR_AARCH32_MODE_USER 0x0\r | |
81 | #define SPSR_AARCH32_MODE_FIQ 0x1\r | |
82 | #define SPSR_AARCH32_MODE_IRQ 0x2\r | |
83 | #define SPSR_AARCH32_MODE_SVC 0x3\r | |
84 | #define SPSR_AARCH32_MODE_ABORT 0x7\r | |
85 | #define SPSR_AARCH32_MODE_UNDEF 0xB\r | |
86 | #define SPSR_AARCH32_MODE_SYS 0xF\r | |
87 | \r | |
88 | // Counter-timer Hypervisor Control register definitions\r | |
89 | #define CNTHCTL_EL2_EL1PCTEN BIT0\r | |
90 | #define CNTHCTL_EL2_EL1PCEN BIT1\r | |
91 | \r | |
25402f5d HL |
92 | #define ARM_VECTOR_TABLE_ALIGNMENT ((1 << 11)-1)\r |
93 | \r | |
d855b261 MR |
94 | // Vector table offset definitions\r |
95 | #define ARM_VECTOR_CUR_SP0_SYNC 0x000\r | |
96 | #define ARM_VECTOR_CUR_SP0_IRQ 0x080\r | |
97 | #define ARM_VECTOR_CUR_SP0_FIQ 0x100\r | |
98 | #define ARM_VECTOR_CUR_SP0_SERR 0x180\r | |
99 | \r | |
a4d95d7c PG |
100 | #define ARM_VECTOR_CUR_SPX_SYNC 0x200\r |
101 | #define ARM_VECTOR_CUR_SPX_IRQ 0x280\r | |
102 | #define ARM_VECTOR_CUR_SPX_FIQ 0x300\r | |
103 | #define ARM_VECTOR_CUR_SPX_SERR 0x380\r | |
d855b261 MR |
104 | \r |
105 | #define ARM_VECTOR_LOW_A64_SYNC 0x400\r | |
106 | #define ARM_VECTOR_LOW_A64_IRQ 0x480\r | |
107 | #define ARM_VECTOR_LOW_A64_FIQ 0x500\r | |
108 | #define ARM_VECTOR_LOW_A64_SERR 0x580\r | |
109 | \r | |
110 | #define ARM_VECTOR_LOW_A32_SYNC 0x600\r | |
111 | #define ARM_VECTOR_LOW_A32_IRQ 0x680\r | |
112 | #define ARM_VECTOR_LOW_A32_FIQ 0x700\r | |
113 | #define ARM_VECTOR_LOW_A32_SERR 0x780\r | |
114 | \r | |
92bdb2a9 RC |
115 | // The ID_AA64MMFR2_EL1 register was added in ARMv8.2. Since we\r |
116 | // build for ARMv8.0, we need to define the register here.\r | |
117 | #define ID_AA64MMFR2_EL1 S3_0_C0_C7_2\r | |
118 | \r | |
d855b261 | 119 | #define VECTOR_BASE(tbl) \\r |
e7e12013 | 120 | .section .text.##tbl##,"ax"; \\r |
d855b261 | 121 | .align 11; \\r |
e7e12013 | 122 | .org 0x0; \\r |
d855b261 MR |
123 | GCC_ASM_EXPORT(tbl); \\r |
124 | ASM_PFX(tbl): \\r | |
125 | \r | |
126 | #define VECTOR_ENTRY(tbl, off) \\r | |
e7e12013 | 127 | .org off\r |
d855b261 MR |
128 | \r |
129 | #define VECTOR_END(tbl) \\r | |
e7e12013 AB |
130 | .org 0x800; \\r |
131 | .previous\r | |
d855b261 | 132 | \r |
25402f5d HL |
133 | VOID\r |
134 | EFIAPI\r | |
135 | ArmEnableSWPInstruction (\r | |
136 | VOID\r | |
137 | );\r | |
138 | \r | |
139 | UINTN\r | |
140 | EFIAPI\r | |
141 | ArmReadCbar (\r | |
142 | VOID\r | |
143 | );\r | |
144 | \r | |
145 | UINTN\r | |
146 | EFIAPI\r | |
147 | ArmReadTpidrurw (\r | |
148 | VOID\r | |
149 | );\r | |
150 | \r | |
151 | VOID\r | |
152 | EFIAPI\r | |
153 | ArmWriteTpidrurw (\r | |
154 | UINTN Value\r | |
155 | );\r | |
156 | \r | |
25402f5d HL |
157 | UINTN\r |
158 | EFIAPI\r | |
159 | ArmGetTCR (\r | |
160 | VOID\r | |
161 | );\r | |
162 | \r | |
163 | VOID\r | |
164 | EFIAPI\r | |
165 | ArmSetTCR (\r | |
166 | UINTN Value\r | |
167 | );\r | |
168 | \r | |
169 | UINTN\r | |
170 | EFIAPI\r | |
171 | ArmGetMAIR (\r | |
172 | VOID\r | |
173 | );\r | |
174 | \r | |
175 | VOID\r | |
176 | EFIAPI\r | |
177 | ArmSetMAIR (\r | |
178 | UINTN Value\r | |
179 | );\r | |
180 | \r | |
181 | VOID\r | |
182 | EFIAPI\r | |
183 | ArmDisableAlignmentCheck (\r | |
184 | VOID\r | |
185 | );\r | |
186 | \r | |
25402f5d HL |
187 | VOID\r |
188 | EFIAPI\r | |
189 | ArmEnableAlignmentCheck (\r | |
190 | VOID\r | |
191 | );\r | |
192 | \r | |
97f0d01d AB |
193 | VOID\r |
194 | EFIAPI\r | |
195 | ArmDisableStackAlignmentCheck (\r | |
196 | VOID\r | |
197 | );\r | |
198 | \r | |
199 | VOID\r | |
200 | EFIAPI\r | |
201 | ArmEnableStackAlignmentCheck (\r | |
202 | VOID\r | |
203 | );\r | |
204 | \r | |
25402f5d HL |
205 | VOID\r |
206 | EFIAPI\r | |
207 | ArmDisableAllExceptions (\r | |
208 | VOID\r | |
209 | );\r | |
210 | \r | |
211 | VOID\r | |
212 | ArmWriteHcr (\r | |
213 | IN UINTN Hcr\r | |
214 | );\r | |
215 | \r | |
d2bb61a2 EC |
216 | UINTN\r |
217 | ArmReadHcr (\r | |
218 | VOID\r | |
219 | );\r | |
220 | \r | |
25402f5d HL |
221 | UINTN\r |
222 | ArmReadCurrentEL (\r | |
223 | VOID\r | |
224 | );\r | |
225 | \r | |
d6dc67ba OM |
226 | UINTN\r |
227 | ArmWriteCptr (\r | |
228 | IN UINT64 Cptr\r | |
229 | );\r | |
230 | \r | |
23d6348f SM |
231 | UINT32\r |
232 | ArmReadCntHctl (\r | |
233 | VOID\r | |
234 | );\r | |
235 | \r | |
236 | VOID\r | |
237 | ArmWriteCntHctl (\r | |
238 | IN UINT32 CntHctl\r | |
239 | );\r | |
240 | \r | |
cc15a619 | 241 | #endif // AARCH64_H_\r |