projects / mirror_edk2.git / blame
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|---|---|---|
| 25402f5d HL |
1 | /** @file\r |
| 2 | *\r | |
| 3 | * Copyright (c) 2011-2013, ARM Limited. All rights reserved.\r | |
| 4 | *\r | |
| 5 | * This program and the accompanying materials\r | |
| 6 | * are licensed and made available under the terms and conditions of the BSD License\r | |
| 7 | * which accompanies this distribution. The full text of the license may be found at\r | |
| 8 | * http://opensource.org/licenses/bsd-license.php\r | |
| 9 | *\r | |
| 10 | * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
| 11 | * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
| 12 | *\r | |
| 13 | **/\r | |
| 14 | \r | |
| 15 | #ifndef __AARCH64_MMU_H_\r | |
| 16 | #define __AARCH64_MMU_H_\r | |
| 17 | \r | |
| 18 | //\r | |
| 19 | // Memory Attribute Indirection register Definitions\r | |
| 20 | //\r | |
| 21 | #define MAIR_ATTR_DEVICE_MEMORY 0x0ULL\r | |
| 22 | #define MAIR_ATTR_NORMAL_MEMORY_NON_CACHEABLE 0x44ULL\r | |
| 23 | #define MAIR_ATTR_NORMAL_MEMORY_WRITE_THROUGH 0xBBULL\r | |
| 24 | #define MAIR_ATTR_NORMAL_MEMORY_WRITE_BACK 0xFFULL\r | |
| 25 | \r | |
| 26 | #define MAIR_ATTR(n,value) ((value) << (((n) >> 2)*8))\r | |
| 27 | \r | |
| 28 | //\r | |
| 29 | // Long-descriptor Translation Table format\r | |
| 30 | //\r | |
| 31 | \r | |
| 32 | // Return the smallest offset from the table level.\r | |
| 33 | // The first offset starts at 12bit. There are 4 levels of 9-bit address range from level 3 to level 0\r | |
| 34 | #define TT_ADDRESS_OFFSET_AT_LEVEL(TableLevel) (12 + ((3 - (TableLevel)) * 9))\r | |
| 35 | \r | |
| 88333703 | 36 | #define TT_BLOCK_ENTRY_SIZE_AT_LEVEL(Level) (1ULL << TT_ADDRESS_OFFSET_AT_LEVEL(Level))\r |
| 25402f5d HL |
37 | \r |
| 38 | // Get the associated entry in the given Translation Table\r | |
| 39 | #define TT_GET_ENTRY_FOR_ADDRESS(TranslationTable, Level, Address) \\r | |
| 88333703 | 40 | ((UINTN)(TranslationTable) + ((((UINTN)(Address) >> TT_ADDRESS_OFFSET_AT_LEVEL(Level)) & (BIT9-1)) * sizeof(UINT64)))\r |
| 25402f5d HL |
41 | \r |
| 42 | // Return the smallest address granularity from the table level.\r | |
| 43 | // The first offset starts at 12bit. There are 4 levels of 9-bit address range from level 3 to level 0\r | |
| 88333703 | 44 | #define TT_ADDRESS_AT_LEVEL(TableLevel) (1ULL << TT_ADDRESS_OFFSET_AT_LEVEL(TableLevel))\r |
| 25402f5d | 45 | \r |
| d9680b94 OM |
46 | #define TT_LAST_BLOCK_ADDRESS(TranslationTable, EntryCount) \\r |
| 47 | ((UINT64*)((EFI_PHYSICAL_ADDRESS)(TranslationTable) + (((EntryCount) - 1) * sizeof(UINT64))))\r | |
| 48 | \r | |
| 25402f5d HL |
49 | // There are 512 entries per table when 4K Granularity\r |
| 50 | #define TT_ENTRY_COUNT 512\r | |
| 51 | #define TT_ALIGNMENT_BLOCK_ENTRY BIT12\r | |
| 52 | #define TT_ALIGNMENT_DESCRIPTION_TABLE BIT12\r | |
| 53 | \r | |
| 829ea9b2 HG |
54 | #define TT_ADDRESS_MASK_BLOCK_ENTRY (0xFFFFFFFFFULL << 12)\r |
| 55 | #define TT_ADDRESS_MASK_DESCRIPTION_TABLE (0xFFFFFFFFFULL << 12)\r | |
| 25402f5d HL |
56 | \r |
| 57 | #define TT_TYPE_MASK 0x3\r | |
| 58 | #define TT_TYPE_TABLE_ENTRY 0x3\r | |
| 59 | #define TT_TYPE_BLOCK_ENTRY 0x1\r | |
| 60 | #define TT_TYPE_BLOCK_ENTRY_LEVEL3 0x3\r | |
| 61 | \r | |
| 62 | #define TT_ATTR_INDX_MASK (0x7 << 2)\r | |
| 63 | #define TT_ATTR_INDX_DEVICE_MEMORY (0x0 << 2)\r | |
| 64 | #define TT_ATTR_INDX_MEMORY_NON_CACHEABLE (0x1 << 2)\r | |
| 65 | #define TT_ATTR_INDX_MEMORY_WRITE_THROUGH (0x2 << 2)\r | |
| 66 | #define TT_ATTR_INDX_MEMORY_WRITE_BACK (0x3 << 2)\r | |
| 67 | \r | |
| 68 | #define TT_AP_MASK (0x3UL << 6)\r | |
| 69 | #define TT_AP_NO_RW (0x0UL << 6)\r | |
| 70 | #define TT_AP_RW_RW (0x1UL << 6)\r | |
| 71 | #define TT_AP_NO_RO (0x2UL << 6)\r | |
| 72 | #define TT_AP_RO_RO (0x3UL << 6)\r | |
| 73 | \r | |
| 74 | #define TT_NS BIT5\r | |
| 75 | #define TT_AF BIT10\r | |
| 76 | \r | |
| 0c9a522f AB |
77 | #define TT_SH_NON_SHAREABLE (0x0 << 8)\r |
| 78 | #define TT_SH_OUTER_SHAREABLE (0x2 << 8)\r | |
| 79 | #define TT_SH_INNER_SHAREABLE (0x3 << 8)\r | |
| 80 | #define TT_SH_MASK (0x3 << 8)\r | |
| 81 | \r | |
| 25402f5d | 82 | #define TT_PXN_MASK BIT53\r |
| 2afeabd1 AB |
83 | #define TT_UXN_MASK BIT54 // EL1&0\r |
| 84 | #define TT_XN_MASK BIT54 // EL2 / EL3\r | |
| 25402f5d HL |
85 | \r |
| 86 | #define TT_ATTRIBUTES_MASK ((0xFFFULL << 52) | (0x3FFULL << 2))\r | |
| 87 | \r | |
| 88 | #define TT_TABLE_PXN BIT59\r | |
| 2afeabd1 AB |
89 | #define TT_TABLE_UXN BIT60 // EL1&0\r |
| 90 | #define TT_TABLE_XN BIT60 // EL2 / EL3\r | |
| 25402f5d HL |
91 | #define TT_TABLE_NS BIT63\r |
| 92 | \r | |
| 93 | #define TT_TABLE_AP_MASK (BIT62 | BIT61)\r | |
| 94 | #define TT_TABLE_AP_NO_PERMISSION (0x0ULL << 61)\r | |
| 95 | #define TT_TABLE_AP_EL0_NO_ACCESS (0x1ULL << 61)\r | |
| 96 | #define TT_TABLE_AP_NO_WRITE_ACCESS (0x2ULL << 61)\r | |
| 97 | \r | |
| 98 | //\r | |
| 99 | // Translation Control Register\r | |
| 100 | //\r | |
| 101 | #define TCR_T0SZ_MASK 0x3F\r | |
| 102 | \r | |
| 103 | #define TCR_PS_4GB (0 << 16)\r | |
| 104 | #define TCR_PS_64GB (1 << 16)\r | |
| 105 | #define TCR_PS_1TB (2 << 16)\r | |
| 106 | #define TCR_PS_4TB (3 << 16)\r | |
| 107 | #define TCR_PS_16TB (4 << 16)\r | |
| 108 | #define TCR_PS_256TB (5 << 16)\r | |
| 109 | \r | |
| 110 | #define TCR_TG0_4KB (0 << 14)\r | |
| 111 | \r | |
| 62436c21 OM |
112 | #define TCR_IPS_4GB (0ULL << 32)\r |
| 113 | #define TCR_IPS_64GB (1ULL << 32)\r | |
| 114 | #define TCR_IPS_1TB (2ULL << 32)\r | |
| 115 | #define TCR_IPS_4TB (3ULL << 32)\r | |
| 116 | #define TCR_IPS_16TB (4ULL << 32)\r | |
| 117 | #define TCR_IPS_256TB (5ULL << 32)\r | |
| 25402f5d HL |
118 | \r |
| 119 | \r | |
| 120 | #define TTBR_ASID_FIELD (48)\r | |
| 121 | #define TTBR_ASID_MASK (0xFF << TTBR_ASID_FIELD)\r | |
| 122 | #define TTBR_BADDR_MASK (0xFFFFFFFFFFFF ) // The width of this field depends on the values in TxSZ. Addr occupies bottom 48bits\r | |
| 123 | \r | |
| 124 | #define TCR_EL1_T0SZ_FIELD (0)\r | |
| 125 | #define TCR_EL1_EPD0_FIELD (7)\r | |
| 126 | #define TCR_EL1_IRGN0_FIELD (8)\r | |
| 127 | #define TCR_EL1_ORGN0_FIELD (10)\r | |
| 128 | #define TCR_EL1_SH0_FIELD (12)\r | |
| 129 | #define TCR_EL1_TG0_FIELD (14)\r | |
| 130 | #define TCR_EL1_T1SZ_FIELD (16)\r | |
| 131 | #define TCR_EL1_A1_FIELD (22)\r | |
| 132 | #define TCR_EL1_EPD1_FIELD (23)\r | |
| 133 | #define TCR_EL1_IRGN1_FIELD (24)\r | |
| 134 | #define TCR_EL1_ORGN1_FIELD (26)\r | |
| 135 | #define TCR_EL1_SH1_FIELD (28)\r | |
| 136 | #define TCR_EL1_TG1_FIELD (30)\r | |
| 137 | #define TCR_EL1_IPS_FIELD (32)\r | |
| 138 | #define TCR_EL1_AS_FIELD (36)\r | |
| 139 | #define TCR_EL1_TBI0_FIELD (37)\r | |
| 140 | #define TCR_EL1_TBI1_FIELD (38)\r | |
| 141 | #define TCR_EL1_T0SZ_MASK (0x1F << TCR_EL1_T0SZ_FIELD)\r | |
| 142 | #define TCR_EL1_EPD0_MASK (0x1 << TCR_EL1_EPD0_FIELD)\r | |
| 143 | #define TCR_EL1_IRGN0_MASK (0x3 << TCR_EL1_IRGN0_FIELD)\r | |
| 144 | #define TCR_EL1_ORGN0_MASK (0x3 << TCR_EL1_ORGN0_FIELD)\r | |
| 145 | #define TCR_EL1_SH0_MASK (0x3 << TCR_EL1_SH0_FIELD)\r | |
| 146 | #define TCR_EL1_TG0_MASK (0x1 << TCR_EL1_TG0_FIELD)\r | |
| 147 | #define TCR_EL1_T1SZ_MASK (0x1F << TCR_EL1_T1SZ_FIELD)\r | |
| 148 | #define TCR_EL1_A1_MASK (0x1 << TCR_EL1_A1_FIELD)\r | |
| 149 | #define TCR_EL1_EPD1_MASK (0x1 << TCR_EL1_EPD1_FIELD)\r | |
| 150 | #define TCR_EL1_IRGN1_MASK (0x3 << TCR_EL1_IRGN1_FIELD)\r | |
| 151 | #define TCR_EL1_ORGN1_MASK (0x3 << TCR_EL1_ORGN1_FIELD)\r | |
| 152 | #define TCR_EL1_SH1_MASK (0x3 << TCR_EL1_SH1_FIELD)\r | |
| 153 | #define TCR_EL1_TG1_MASK (0x1 << TCR_EL1_TG1_FIELD)\r | |
| 154 | #define TCR_EL1_IPS_MASK (0x7 << TCR_EL1_IPS_FIELD)\r | |
| 155 | #define TCR_EL1_AS_MASK (0x1 << TCR_EL1_AS_FIELD)\r | |
| 156 | #define TCR_EL1_TBI0_MASK (0x1 << TCR_EL1_TBI0_FIELD)\r | |
| 157 | #define TCR_EL1_TBI1_MASK (0x1 << TCR_EL1_TBI1_FIELD)\r | |
| 158 | \r | |
| 159 | \r | |
| 160 | #define VTCR_EL23_T0SZ_FIELD (0)\r | |
| 161 | #define VTCR_EL23_IRGN0_FIELD (8)\r | |
| 162 | #define VTCR_EL23_ORGN0_FIELD (10)\r | |
| 163 | #define VTCR_EL23_SH0_FIELD (12)\r | |
| 164 | #define TCR_EL23_TG0_FIELD (14)\r | |
| 165 | #define VTCR_EL23_PS_FIELD (16)\r | |
| 166 | #define TCR_EL23_T0SZ_MASK (0x1F << VTCR_EL23_T0SZ_FIELD)\r | |
| 167 | #define TCR_EL23_IRGN0_MASK (0x3 << VTCR_EL23_IRGN0_FIELD)\r | |
| 168 | #define TCR_EL23_ORGN0_MASK (0x3 << VTCR_EL23_ORGN0_FIELD)\r | |
| 169 | #define TCR_EL23_SH0_MASK (0x3 << VTCR_EL23_SH0_FIELD)\r | |
| 170 | #define TCR_EL23_TG0_MASK (0x1 << TCR_EL23_TG0_FIELD)\r | |
| 171 | #define TCR_EL23_PS_MASK (0x7 << VTCR_EL23_PS_FIELD)\r | |
| 172 | \r | |
| 173 | \r | |
| 174 | #define VTCR_EL2_T0SZ_FIELD (0)\r | |
| 175 | #define VTCR_EL2_SL0_FIELD (6)\r | |
| 176 | #define VTCR_EL2_IRGN0_FIELD (8)\r | |
| 177 | #define VTCR_EL2_ORGN0_FIELD (10)\r | |
| 178 | #define VTCR_EL2_SH0_FIELD (12)\r | |
| 179 | #define VTCR_EL2_TG0_FIELD (14)\r | |
| 180 | #define VTCR_EL2_PS_FIELD (16)\r | |
| 181 | #define VTCR_EL2_T0SZ_MASK (0x1F << VTCR_EL2_T0SZ_FIELD)\r | |
| 182 | #define VTCR_EL2_SL0_MASK (0x1F << VTCR_EL2_SL0_FIELD)\r | |
| 183 | #define VTCR_EL2_IRGN0_MASK (0x3 << VTCR_EL2_IRGN0_FIELD)\r | |
| 184 | #define VTCR_EL2_ORGN0_MASK (0x3 << VTCR_EL2_ORGN0_FIELD)\r | |
| 185 | #define VTCR_EL2_SH0_MASK (0x3 << VTCR_EL2_SH0_FIELD)\r | |
| 186 | #define VTCR_EL2_TG0_MASK (0x1 << VTCR_EL2_TG0_FIELD)\r | |
| 187 | #define VTCR_EL2_PS_MASK (0x7 << VTCR_EL2_PS_FIELD)\r | |
| 188 | \r | |
| 189 | \r | |
| 190 | #define TCR_RGN_OUTER_NON_CACHEABLE (0x0 << 10)\r | |
| 191 | #define TCR_RGN_OUTER_WRITE_BACK_ALLOC (0x1 << 10)\r | |
| 192 | #define TCR_RGN_OUTER_WRITE_THROUGH (0x2 << 10)\r | |
| 193 | #define TCR_RGN_OUTER_WRITE_BACK_NO_ALLOC (0x3 << 10)\r | |
| 194 | \r | |
| 195 | #define TCR_RGN_INNER_NON_CACHEABLE (0x0 << 8)\r | |
| 196 | #define TCR_RGN_INNER_WRITE_BACK_ALLOC (0x1 << 8)\r | |
| 197 | #define TCR_RGN_INNER_WRITE_THROUGH (0x2 << 8)\r | |
| 198 | #define TCR_RGN_INNER_WRITE_BACK_NO_ALLOC (0x3 << 8)\r | |
| 199 | \r | |
| 200 | #define TCR_SH_NON_SHAREABLE (0x0 << 12)\r | |
| 201 | #define TCR_SH_OUTER_SHAREABLE (0x2 << 12)\r | |
| 202 | #define TCR_SH_INNER_SHAREABLE (0x3 << 12)\r | |
| 203 | \r | |
| 204 | #define TCR_PASZ_32BITS_4GB (0x0)\r | |
| 205 | #define TCR_PASZ_36BITS_64GB (0x1)\r | |
| 206 | #define TCR_PASZ_40BITS_1TB (0x2)\r | |
| 207 | #define TCR_PASZ_42BITS_4TB (0x3)\r | |
| 208 | #define TCR_PASZ_44BITS_16TB (0x4)\r | |
| 209 | #define TCR_PASZ_48BITS_256TB (0x5)\r | |
| 210 | \r | |
| 211 | // The value written to the T*SZ fields are defined as 2^(64-T*SZ). So a 39Bit\r | |
| 212 | // Virtual address range for 512GB of virtual space sets T*SZ to 25\r | |
| 213 | #define INPUT_ADDRESS_SIZE_TO_TxSZ(a) (64 - a)\r | |
| 214 | \r | |
| 215 | // Uses LPAE Page Table format\r | |
| 216 | \r | |
| 217 | #endif // __AARCH64_MMU_H_\r | |
| 218 | \r |