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3127615b | 1 | /** @file\r |
2 | \r | |
3 | Copyright (c) 2011, ARM Limited. All rights reserved.\r | |
4 | \r | |
4059386c | 5 | SPDX-License-Identifier: BSD-2-Clause-Patent\r |
3127615b | 6 | \r |
7 | **/\r | |
8 | \r | |
cc15a619 PG |
9 | #ifndef ARM_CORTEX_A9_H_\r |
10 | #define ARM_CORTEX_A9_H_\r | |
3127615b | 11 | \r |
12 | #include <Chipset/ArmV7.h>\r | |
13 | \r | |
14 | //\r | |
15 | // Cortex A9 feature bit definitions\r | |
16 | //\r | |
17 | #define A9_FEATURE_PARITY (1<<9)\r | |
18 | #define A9_FEATURE_AOW (1<<8)\r | |
19 | #define A9_FEATURE_EXCL (1<<7)\r | |
20 | #define A9_FEATURE_SMP (1<<6)\r | |
21 | #define A9_FEATURE_FOZ (1<<3)\r | |
22 | #define A9_FEATURE_DPREF (1<<2)\r | |
23 | #define A9_FEATURE_HINT (1<<1)\r | |
24 | #define A9_FEATURE_FWD (1<<0)\r | |
25 | \r | |
26 | //\r | |
27 | // Cortex A9 Watchdog\r | |
28 | //\r | |
29 | #define ARM_A9_WATCHDOG_REGION 0x600\r | |
30 | \r | |
31 | #define ARM_A9_WATCHDOG_LOAD_REGISTER 0x20\r | |
32 | #define ARM_A9_WATCHDOG_CONTROL_REGISTER 0x28\r | |
33 | \r | |
34 | #define ARM_A9_WATCHDOG_WATCHDOG_MODE (1 << 3)\r | |
35 | #define ARM_A9_WATCHDOG_TIMER_MODE (0 << 3)\r | |
36 | #define ARM_A9_WATCHDOG_SINGLE_SHOT (0 << 1)\r | |
37 | #define ARM_A9_WATCHDOG_AUTORELOAD (1 << 1)\r | |
38 | #define ARM_A9_WATCHDOG_ENABLE 1\r | |
39 | \r | |
40 | //\r | |
41 | // SCU register offsets & masks\r | |
42 | //\r | |
43 | #define A9_SCU_CONTROL_OFFSET 0x0\r | |
44 | #define A9_SCU_CONFIG_OFFSET 0x4\r | |
45 | #define A9_SCU_INVALL_OFFSET 0xC\r | |
46 | #define A9_SCU_FILT_START_OFFSET 0x40\r | |
47 | #define A9_SCU_FILT_END_OFFSET 0x44\r | |
48 | #define A9_SCU_SACR_OFFSET 0x50\r | |
49 | #define A9_SCU_SSACR_OFFSET 0x54\r | |
50 | \r | |
51 | \r | |
52 | UINTN\r | |
53 | EFIAPI\r | |
54 | ArmGetScuBaseAddress (\r | |
55 | VOID\r | |
56 | );\r | |
57 | \r | |
cc15a619 | 58 | #endif // ARM_CORTEX_A9_H_\r |
3127615b | 59 | \r |