ArmPkg: Rename include guard in ArmGicLib.h

[mirror_edk2.git] / ArmPkg / Include / Library / ArmGicLib.h

/** @file\r
*\r
*  Copyright (c) 2011-2021, Arm Limited. All rights reserved.<BR>\r
*\r
*  SPDX-License-Identifier: BSD-2-Clause-Patent\r
*\r
**/\r
\r
#ifndef ARMGIC_H_\r
#define ARMGIC_H_\r
\r
#include <Library/ArmGicArchLib.h>\r
\r
// GIC Distributor\r
#define ARM_GIC_ICDDCR          0x000 // Distributor Control Register\r
#define ARM_GIC_ICDICTR         0x004 // Interrupt Controller Type Register\r
#define ARM_GIC_ICDIIDR         0x008 // Implementer Identification Register\r
\r
// Each reg base below repeats for Number of interrupts / 4 (see GIC spec)\r
#define ARM_GIC_ICDISR          0x080 // Interrupt Security Registers\r
#define ARM_GIC_ICDISER         0x100 // Interrupt Set-Enable Registers\r
#define ARM_GIC_ICDICER         0x180 // Interrupt Clear-Enable Registers\r
#define ARM_GIC_ICDSPR          0x200 // Interrupt Set-Pending Registers\r
#define ARM_GIC_ICDICPR         0x280 // Interrupt Clear-Pending Registers\r
#define ARM_GIC_ICDABR          0x300 // Active Bit Registers\r
\r
// Each reg base below repeats for Number of interrupts / 4\r
#define ARM_GIC_ICDIPR          0x400 // Interrupt Priority Registers\r
\r
// Each reg base below repeats for Number of interrupts\r
#define ARM_GIC_ICDIPTR         0x800 // Interrupt Processor Target Registers\r
#define ARM_GIC_ICDICFR         0xC00 // Interrupt Configuration Registers\r
\r
#define ARM_GIC_ICDPPISR        0xD00 // PPI Status register\r
\r
// just one of these\r
#define ARM_GIC_ICDSGIR         0xF00 // Software Generated Interrupt Register\r
\r
// GICv3 specific registers\r
#define ARM_GICD_IROUTER        0x6100 // Interrupt Routing Registers\r
\r
// GICD_CTLR bits\r
#define ARM_GIC_ICDDCR_ARE      (1 << 4) // Affinity Routing Enable (ARE)\r
#define ARM_GIC_ICDDCR_DS       (1 << 6) // Disable Security (DS)\r
\r
// GICD_ICDICFR bits\r
#define ARM_GIC_ICDICFR_WIDTH            32   // ICDICFR is a 32 bit register\r
#define ARM_GIC_ICDICFR_BYTES            (ARM_GIC_ICDICFR_WIDTH / 8)\r
#define ARM_GIC_ICDICFR_F_WIDTH          2    // Each F field is 2 bits\r
#define ARM_GIC_ICDICFR_F_STRIDE         16   // (32/2) F fields per register\r
#define ARM_GIC_ICDICFR_F_CONFIG1_BIT    1    // Bit number within F field\r
#define ARM_GIC_ICDICFR_LEVEL_TRIGGERED  0x0  // Level triggered interrupt\r
#define ARM_GIC_ICDICFR_EDGE_TRIGGERED   0x1  // Edge triggered interrupt\r
\r
\r
// GIC Redistributor\r
#define ARM_GICR_CTLR_FRAME_SIZE         SIZE_64KB\r
#define ARM_GICR_SGI_PPI_FRAME_SIZE      SIZE_64KB\r
#define ARM_GICR_SGI_VLPI_FRAME_SIZE     SIZE_64KB\r
#define ARM_GICR_SGI_RESERVED_FRAME_SIZE SIZE_64KB\r
\r
// GIC Redistributor Control frame\r
#define ARM_GICR_TYPER          0x0008  // Redistributor Type Register\r
\r
// GIC Redistributor TYPER bit assignments\r
#define ARM_GICR_TYPER_PLPIS        (1 << 0)              // Physical LPIs\r
#define ARM_GICR_TYPER_VLPIS        (1 << 1)              // Virtual LPIs\r
#define ARM_GICR_TYPER_DIRECTLPI    (1 << 3)              // Direct LPIs\r
#define ARM_GICR_TYPER_LAST         (1 << 4)              // Last Redistributor in series\r
#define ARM_GICR_TYPER_DPGS         (1 << 5)              // Disable Processor Group\r
                                                          // Selection Support\r
#define ARM_GICR_TYPER_PROCNO       (0xFFFF << 8)         // Processor Number\r
#define ARM_GICR_TYPER_COMMONLPIAFF (0x3 << 24)           // Common LPI Affinity\r
#define ARM_GICR_TYPER_AFFINITY     (0xFFFFFFFFULL << 32) // Redistributor Affinity\r
\r
#define ARM_GICR_TYPER_GET_AFFINITY(TypeReg)  (((TypeReg) & \\r
                                                ARM_GICR_TYPER_AFFINITY) >> 32)\r
\r
// GIC SGI & PPI Redistributor frame\r
#define ARM_GICR_ISENABLER      0x0100  // Interrupt Set-Enable Registers\r
#define ARM_GICR_ICENABLER      0x0180  // Interrupt Clear-Enable Registers\r
\r
// GIC Cpu interface\r
#define ARM_GIC_ICCICR          0x00  // CPU Interface Control Register\r
#define ARM_GIC_ICCPMR          0x04  // Interrupt Priority Mask Register\r
#define ARM_GIC_ICCBPR          0x08  // Binary Point Register\r
#define ARM_GIC_ICCIAR          0x0C  // Interrupt Acknowledge Register\r
#define ARM_GIC_ICCEIOR         0x10  // End Of Interrupt Register\r
#define ARM_GIC_ICCRPR          0x14  // Running Priority Register\r
#define ARM_GIC_ICCPIR          0x18  // Highest Pending Interrupt Register\r
#define ARM_GIC_ICCABPR         0x1C  // Aliased Binary Point Register\r
#define ARM_GIC_ICCIIDR         0xFC  // Identification Register\r
\r
#define ARM_GIC_ICDSGIR_FILTER_TARGETLIST       0x0\r
#define ARM_GIC_ICDSGIR_FILTER_EVERYONEELSE     0x1\r
#define ARM_GIC_ICDSGIR_FILTER_ITSELF           0x2\r
\r
// Bit-masks to configure the CPU Interface Control register\r
#define ARM_GIC_ICCICR_ENABLE_SECURE            0x01\r
#define ARM_GIC_ICCICR_ENABLE_NS                0x02\r
#define ARM_GIC_ICCICR_ACK_CTL                  0x04\r
#define ARM_GIC_ICCICR_SIGNAL_SECURE_TO_FIQ     0x08\r
#define ARM_GIC_ICCICR_USE_SBPR                 0x10\r
\r
// Bit Mask for GICC_IIDR\r
#define ARM_GIC_ICCIIDR_GET_PRODUCT_ID(IccIidr)   (((IccIidr) >> 20) & 0xFFF)\r
#define ARM_GIC_ICCIIDR_GET_ARCH_VERSION(IccIidr) (((IccIidr) >> 16) & 0xF)\r
#define ARM_GIC_ICCIIDR_GET_REVISION(IccIidr)     (((IccIidr) >> 12) & 0xF)\r
#define ARM_GIC_ICCIIDR_GET_IMPLEMENTER(IccIidr)  ((IccIidr) & 0xFFF)\r
\r
// Bit Mask for\r
#define ARM_GIC_ICCIAR_ACKINTID                 0x3FF\r
\r
UINTN\r
EFIAPI\r
ArmGicGetInterfaceIdentification (\r
  IN  INTN          GicInterruptInterfaceBase\r
  );\r
\r
// GIC Secure interfaces\r
VOID\r
EFIAPI\r
ArmGicSetupNonSecure (\r
  IN  UINTN         MpId,\r
  IN  INTN          GicDistributorBase,\r
  IN  INTN          GicInterruptInterfaceBase\r
  );\r
\r
VOID\r
EFIAPI\r
ArmGicSetSecureInterrupts (\r
  IN  UINTN         GicDistributorBase,\r
  IN  UINTN*        GicSecureInterruptMask,\r
  IN  UINTN         GicSecureInterruptMaskSize\r
  );\r
\r
VOID\r
EFIAPI\r
ArmGicEnableInterruptInterface (\r
  IN  INTN          GicInterruptInterfaceBase\r
  );\r
\r
VOID\r
EFIAPI\r
ArmGicDisableInterruptInterface (\r
  IN  INTN          GicInterruptInterfaceBase\r
  );\r
\r
VOID\r
EFIAPI\r
ArmGicEnableDistributor (\r
  IN  INTN          GicDistributorBase\r
  );\r
\r
VOID\r
EFIAPI\r
ArmGicDisableDistributor (\r
  IN  INTN          GicDistributorBase\r
  );\r
\r
UINTN\r
EFIAPI\r
ArmGicGetMaxNumInterrupts (\r
  IN  INTN          GicDistributorBase\r
  );\r
\r
VOID\r
EFIAPI\r
ArmGicSendSgiTo (\r
  IN  INTN          GicDistributorBase,\r
  IN  INTN          TargetListFilter,\r
  IN  INTN          CPUTargetList,\r
  IN  INTN          SgiId\r
  );\r
\r
/*\r
 * Acknowledge and return the value of the Interrupt Acknowledge Register\r
 *\r
 * InterruptId is returned separately from the register value because in\r
 * the GICv2 the register value contains the CpuId and InterruptId while\r
 * in the GICv3 the register value is only the InterruptId.\r
 *\r
 * @param GicInterruptInterfaceBase   Base Address of the GIC CPU Interface\r
 * @param InterruptId                 InterruptId read from the Interrupt\r
 *                                    Acknowledge Register\r
 *\r
 * @retval value returned by the Interrupt Acknowledge Register\r
 *\r
 */\r
UINTN\r
EFIAPI\r
ArmGicAcknowledgeInterrupt (\r
  IN  UINTN          GicInterruptInterfaceBase,\r
  OUT UINTN          *InterruptId\r
  );\r
\r
VOID\r
EFIAPI\r
ArmGicEndOfInterrupt (\r
  IN  UINTN                 GicInterruptInterfaceBase,\r
  IN UINTN                  Source\r
  );\r
\r
UINTN\r
EFIAPI\r
ArmGicSetPriorityMask (\r
  IN  INTN          GicInterruptInterfaceBase,\r
  IN  INTN          PriorityMask\r
  );\r
\r
VOID\r
EFIAPI\r
ArmGicSetInterruptPriority (\r
  IN UINTN                  GicDistributorBase,\r
  IN UINTN                  GicRedistributorBase,\r
  IN UINTN                  Source,\r
  IN UINTN                  Priority\r
  );\r
\r
VOID\r
EFIAPI\r
ArmGicEnableInterrupt (\r
  IN UINTN                  GicDistributorBase,\r
  IN UINTN                  GicRedistributorBase,\r
  IN UINTN                  Source\r
  );\r
\r
VOID\r
EFIAPI\r
ArmGicDisableInterrupt (\r
  IN UINTN                  GicDistributorBase,\r
  IN UINTN                  GicRedistributorBase,\r
  IN UINTN                  Source\r
  );\r
\r
BOOLEAN\r
EFIAPI\r
ArmGicIsInterruptEnabled (\r
  IN UINTN                  GicDistributorBase,\r
  IN UINTN                  GicRedistributorBase,\r
  IN UINTN                  Source\r
  );\r
\r
// GIC revision 2 specific declarations\r
\r
// Interrupts from 1020 to 1023 are considered as special interrupts\r
// (eg: spurious interrupts)\r
#define ARM_GIC_IS_SPECIAL_INTERRUPTS(Interrupt) \\r
          (((Interrupt) >= 1020) && ((Interrupt) <= 1023))\r
\r
VOID\r
EFIAPI\r
ArmGicV2SetupNonSecure (\r
  IN  UINTN         MpId,\r
  IN  INTN          GicDistributorBase,\r
  IN  INTN          GicInterruptInterfaceBase\r
  );\r
\r
VOID\r
EFIAPI\r
ArmGicV2EnableInterruptInterface (\r
  IN  INTN          GicInterruptInterfaceBase\r
  );\r
\r
VOID\r
EFIAPI\r
ArmGicV2DisableInterruptInterface (\r
  IN  INTN          GicInterruptInterfaceBase\r
  );\r
\r
UINTN\r
EFIAPI\r
ArmGicV2AcknowledgeInterrupt (\r
  IN  UINTN          GicInterruptInterfaceBase\r
  );\r
\r
VOID\r
EFIAPI\r
ArmGicV2EndOfInterrupt (\r
  IN UINTN                  GicInterruptInterfaceBase,\r
  IN UINTN                  Source\r
  );\r
\r
// GIC revision 3 specific declarations\r
\r
#define ICC_SRE_EL2_SRE         (1 << 0)\r
\r
#define ARM_GICD_IROUTER_IRM BIT31\r
\r
UINT32\r
EFIAPI\r
ArmGicV3GetControlSystemRegisterEnable (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmGicV3SetControlSystemRegisterEnable (\r
  IN UINT32         ControlSystemRegisterEnable\r
  );\r
\r
VOID\r
EFIAPI\r
ArmGicV3EnableInterruptInterface (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmGicV3DisableInterruptInterface (\r
  VOID\r
  );\r
\r
UINTN\r
EFIAPI\r
ArmGicV3AcknowledgeInterrupt (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmGicV3EndOfInterrupt (\r
  IN UINTN                  Source\r
  );\r
\r
VOID\r
ArmGicV3SetBinaryPointer (\r
  IN UINTN                  BinaryPoint\r
  );\r
\r
VOID\r
ArmGicV3SetPriorityMask (\r
  IN UINTN                  Priority\r
  );\r
\r
#endif // ARMGIC_H_\r