[mirror_edk2.git] / ArmPkg / Include / Library / ArmGicLib.h

/** @file\r
*\r
*  Copyright (c) 2011, ARM Limited. All rights reserved.\r
*  \r
*  This program and the accompanying materials                          \r
*  are licensed and made available under the terms and conditions of the BSD License         \r
*  which accompanies this distribution.  The full text of the license may be found at        \r
*  http://opensource.org/licenses/bsd-license.php                                            \r
*\r
*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     \r
*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             \r
*\r
**/\r
\r
#ifndef __PL390GIC_H\r
#define __PL390GIC_H\r
\r
//\r
// GIC definitions\r
//\r
\r
//\r
// GIC Distributor\r
//\r
#define ARM_GIC_ICDDCR          0x000 // Distributor Control Register\r
#define ARM_GIC_ICDICTR         0x004 // Interrupt Controller Type Register\r
#define ARM_GIC_ICDIIDR         0x008 // Implementer Identification Register\r
\r
// Each reg base below repeats for VE_NUM_ARM_GIC_REG_PER_INT_BITS (see GIC spec)\r
#define ARM_GIC_ICDISR          0x080 // Interrupt Security Registers\r
#define ARM_GIC_ICDISER         0x100 // Interrupt Set-Enable Registers\r
#define ARM_GIC_ICDICER         0x180 // Interrupt Clear-Enable Registers\r
#define ARM_GIC_ICDSPR          0x200 // Interrupt Set-Pending Registers\r
#define ARM_GIC_ICDICPR         0x280 // Interrupt Clear-Pending Registers\r
#define ARM_GIC_ICDABR          0x300 // Active Bit Registers\r
\r
// Each reg base below repeats for VE_NUM_ARM_GIC_REG_PER_INT_BYTES\r
#define ARM_GIC_ICDIPR          0x400 // Interrupt Priority Registers\r
\r
// Each reg base below repeats for VE_NUM_ARM_GIC_INTERRUPTS\r
#define ARM_GIC_ICDIPTR         0x800 // Interrupt Processor Target Registers\r
#define ARM_GIC_ICDICFR         0xC00 // Interrupt Configuration Registers\r
\r
#define ARM_GIC_ICDPPISR        0xD00 // PPI Status register\r
\r
// just one of these\r
#define ARM_GIC_ICDSGIR         0xF00 // Software Generated Interrupt Register\r
\r
//\r
// GIC Cpu interface\r
//\r
#define ARM_GIC_ICCICR          0x00  // CPU Interface Control Register\r
#define ARM_GIC_ICCPMR          0x04  // Interrupt Priority Mask Register\r
#define ARM_GIC_ICCBPR          0x08  // Binary Point Register\r
#define ARM_GIC_ICCIAR          0x0C  // Interrupt Acknowledge Register\r
#define ARM_GIC_ICCEIOR         0x10  // End Of Interrupt Register\r
#define ARM_GIC_ICCRPR          0x14  // Running Priority Register\r
#define ARM_GIC_ICCPIR          0x18  // Highest Pending Interrupt Register\r
#define ARM_GIC_ICCABPR         0x1C  // Aliased Binary Point Register\r
#define ARM_GIC_ICCIDR          0xFC  // Identification Register\r
\r
#define ARM_GIC_ICDSGIR_FILTER_TARGETLIST       0x0\r
#define ARM_GIC_ICDSGIR_FILTER_EVERYONEELSE     0x1\r
#define ARM_GIC_ICDSGIR_FILTER_ITSELF           0x2\r
\r
// Bit-masks to configure the CPU Interface Control register\r
#define ARM_GIC_ICCICR_ENABLE_SECURE            0x01\r
#define ARM_GIC_ICCICR_ENABLE_NS                0x02\r
#define ARM_GIC_ICCICR_ACK_CTL                  0x04\r
#define ARM_GIC_ICCICR_SIGNAL_SECURE_TO_FIQ     0x08\r
#define ARM_GIC_ICCICR_USE_SBPR                 0x10\r
\r
\r
//\r
// GIC SEC interfaces\r
//\r
VOID\r
EFIAPI\r
ArmGicSetupNonSecure (\r
  IN  INTN          GicDistributorBase,\r
  IN  INTN          GicInterruptInterfaceBase\r
  );\r
\r
VOID\r
EFIAPI\r
ArmGicEnableInterruptInterface (\r
  IN  INTN          GicInterruptInterfaceBase\r
  );\r
\r
VOID\r
EFIAPI\r
ArmGicEnableDistributor (\r
  IN  INTN          GicDistributorBase\r
  );\r
\r
VOID\r
EFIAPI\r
ArmGicSendSgiTo (\r
  IN  INTN          GicDistributorBase,\r
  IN  INTN          TargetListFilter,\r
  IN  INTN          CPUTargetList\r
  );\r
\r
UINT32\r
EFIAPI\r
ArmGicAcknowledgeSgiFrom (\r
  IN  INTN          GicInterruptInterfaceBase,\r
  IN  INTN          CoreId\r
  );\r
\r
UINT32\r
EFIAPI\r
ArmGicAcknowledgeSgi2From (\r
  IN  INTN          GicInterruptInterfaceBase,\r
  IN  INTN          CoreId,\r
  IN  INTN          SgiId\r
  );\r
\r
UINTN\r
EFIAPI\r
ArmGicSetPriorityMask (\r
  IN  INTN          GicInterruptInterfaceBase,\r
  IN  INTN          PriorityMask\r
  );\r
\r
#endif\r
Commit	Line	Data
55a0d64b	1	/** @file\r
	2	*\r
	3	* Copyright (c) 2011, ARM Limited. All rights reserved.\r
	4	* \r
	5	* This program and the accompanying materials \r
	6	* are licensed and made available under the terms and conditions of the BSD License \r
	7	* which accompanies this distribution. The full text of the license may be found at \r
	8	* http://opensource.org/licenses/bsd-license.php \r
	9	*\r
	10	* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
	11	* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
	12	*\r
	13	**/\r
	14	\r
	15	#ifndef __PL390GIC_H\r
	16	#define __PL390GIC_H\r
	17	\r
	18	//\r
	19	// GIC definitions\r
	20	//\r
	21	\r
	22	//\r
	23	// GIC Distributor\r
	24	//\r
	25	#define ARM_GIC_ICDDCR 0x000 // Distributor Control Register\r
	26	#define ARM_GIC_ICDICTR 0x004 // Interrupt Controller Type Register\r
	27	#define ARM_GIC_ICDIIDR 0x008 // Implementer Identification Register\r
	28	\r
	29	// Each reg base below repeats for VE_NUM_ARM_GIC_REG_PER_INT_BITS (see GIC spec)\r
	30	#define ARM_GIC_ICDISR 0x080 // Interrupt Security Registers\r
	31	#define ARM_GIC_ICDISER 0x100 // Interrupt Set-Enable Registers\r
	32	#define ARM_GIC_ICDICER 0x180 // Interrupt Clear-Enable Registers\r
	33	#define ARM_GIC_ICDSPR 0x200 // Interrupt Set-Pending Registers\r
	34	#define ARM_GIC_ICDICPR 0x280 // Interrupt Clear-Pending Registers\r
	35	#define ARM_GIC_ICDABR 0x300 // Active Bit Registers\r
	36	\r
	37	// Each reg base below repeats for VE_NUM_ARM_GIC_REG_PER_INT_BYTES\r
	38	#define ARM_GIC_ICDIPR 0x400 // Interrupt Priority Registers\r
	39	\r
	40	// Each reg base below repeats for VE_NUM_ARM_GIC_INTERRUPTS\r
	41	#define ARM_GIC_ICDIPTR 0x800 // Interrupt Processor Target Registers\r
	42	#define ARM_GIC_ICDICFR 0xC00 // Interrupt Configuration Registers\r
	43	\r
	44	#define ARM_GIC_ICDPPISR 0xD00 // PPI Status register\r
	45	\r
	46	// just one of these\r
	47	#define ARM_GIC_ICDSGIR 0xF00 // Software Generated Interrupt Register\r
	48	\r
	49	//\r
	50	// GIC Cpu interface\r
	51	//\r
	52	#define ARM_GIC_ICCICR 0x00 // CPU Interface Control Register\r
	53	#define ARM_GIC_ICCPMR 0x04 // Interrupt Priority Mask Register\r
	54	#define ARM_GIC_ICCBPR 0x08 // Binary Point Register\r
	55	#define ARM_GIC_ICCIAR 0x0C // Interrupt Acknowledge Register\r
	56	#define ARM_GIC_ICCEIOR 0x10 // End Of Interrupt Register\r
	57	#define ARM_GIC_ICCRPR 0x14 // Running Priority Register\r
	58	#define ARM_GIC_ICCPIR 0x18 // Highest Pending Interrupt Register\r
	59	#define ARM_GIC_ICCABPR 0x1C // Aliased Binary Point Register\r
	60	#define ARM_GIC_ICCIDR 0xFC // Identification Register\r
	61	\r
	62	#define ARM_GIC_ICDSGIR_FILTER_TARGETLIST 0x0\r
	63	#define ARM_GIC_ICDSGIR_FILTER_EVERYONEELSE 0x1\r
	64	#define ARM_GIC_ICDSGIR_FILTER_ITSELF 0x2\r
65	\r
66	// Bit-masks to configure the CPU Interface Control register\r
67	#define ARM_GIC_ICCICR_ENABLE_SECURE 0x01\r
68	#define ARM_GIC_ICCICR_ENABLE_NS 0x02\r
69	#define ARM_GIC_ICCICR_ACK_CTL 0x04\r
70	#define ARM_GIC_ICCICR_SIGNAL_SECURE_TO_FIQ 0x08\r
71	#define ARM_GIC_ICCICR_USE_SBPR 0x10\r
72	\r
73	\r
74	//\r
75	// GIC SEC interfaces\r
76	//\r
77	VOID\r
78	EFIAPI\r
79	ArmGicSetupNonSecure (\r
80	IN INTN GicDistributorBase,\r
81	IN INTN GicInterruptInterfaceBase\r
82	);\r
83	\r
84	VOID\r
85	EFIAPI\r
86	ArmGicEnableInterruptInterface (\r
87	IN INTN GicInterruptInterfaceBase\r
88	);\r
89	\r
90	VOID\r
91	EFIAPI\r
92	ArmGicEnableDistributor (\r
93	IN INTN GicDistributorBase\r
94	);\r
95	\r
96	VOID\r
97	EFIAPI\r
98	ArmGicSendSgiTo (\r
99	IN INTN GicDistributorBase,\r
100	IN INTN TargetListFilter,\r
101	IN INTN CPUTargetList\r
102	);\r
103	\r
104	UINT32\r
105	EFIAPI\r
106	ArmGicAcknowledgeSgiFrom (\r
107	IN INTN GicInterruptInterfaceBase,\r
108	IN INTN CoreId\r
109	);\r
110	\r
111	UINT32\r
112	EFIAPI\r
113	ArmGicAcknowledgeSgi2From (\r
114	IN INTN GicInterruptInterfaceBase,\r
115	IN INTN CoreId,\r
116	IN INTN SgiId\r
117	);\r
118	\r
119	UINTN\r
120	EFIAPI\r
121	ArmGicSetPriorityMask (\r
122	IN INTN GicInterruptInterfaceBase,\r
123	IN INTN PriorityMask\r
124	);\r
125	\r
126	#endif\r