ArmPkg/ArmGicLib: Added function ArmGicSetSecureInterrupts() to define the secure...
[mirror_edk2.git] / ArmPkg / Include / Library / ArmGicLib.h
CommitLineData
55a0d64b 1/** @file\r
2*\r
3* Copyright (c) 2011, ARM Limited. All rights reserved.\r
4* \r
5* This program and the accompanying materials \r
6* are licensed and made available under the terms and conditions of the BSD License \r
7* which accompanies this distribution. The full text of the license may be found at \r
8* http://opensource.org/licenses/bsd-license.php \r
9*\r
10* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
11* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
12*\r
13**/\r
14\r
15#ifndef __PL390GIC_H\r
16#define __PL390GIC_H\r
17\r
18//\r
19// GIC definitions\r
20//\r
21\r
22//\r
23// GIC Distributor\r
24//\r
25#define ARM_GIC_ICDDCR 0x000 // Distributor Control Register\r
26#define ARM_GIC_ICDICTR 0x004 // Interrupt Controller Type Register\r
27#define ARM_GIC_ICDIIDR 0x008 // Implementer Identification Register\r
28\r
29// Each reg base below repeats for VE_NUM_ARM_GIC_REG_PER_INT_BITS (see GIC spec)\r
30#define ARM_GIC_ICDISR 0x080 // Interrupt Security Registers\r
31#define ARM_GIC_ICDISER 0x100 // Interrupt Set-Enable Registers\r
32#define ARM_GIC_ICDICER 0x180 // Interrupt Clear-Enable Registers\r
33#define ARM_GIC_ICDSPR 0x200 // Interrupt Set-Pending Registers\r
34#define ARM_GIC_ICDICPR 0x280 // Interrupt Clear-Pending Registers\r
35#define ARM_GIC_ICDABR 0x300 // Active Bit Registers\r
36\r
37// Each reg base below repeats for VE_NUM_ARM_GIC_REG_PER_INT_BYTES\r
38#define ARM_GIC_ICDIPR 0x400 // Interrupt Priority Registers\r
39\r
40// Each reg base below repeats for VE_NUM_ARM_GIC_INTERRUPTS\r
41#define ARM_GIC_ICDIPTR 0x800 // Interrupt Processor Target Registers\r
42#define ARM_GIC_ICDICFR 0xC00 // Interrupt Configuration Registers\r
43\r
44#define ARM_GIC_ICDPPISR 0xD00 // PPI Status register\r
45\r
46// just one of these\r
47#define ARM_GIC_ICDSGIR 0xF00 // Software Generated Interrupt Register\r
48\r
49//\r
50// GIC Cpu interface\r
51//\r
52#define ARM_GIC_ICCICR 0x00 // CPU Interface Control Register\r
53#define ARM_GIC_ICCPMR 0x04 // Interrupt Priority Mask Register\r
54#define ARM_GIC_ICCBPR 0x08 // Binary Point Register\r
55#define ARM_GIC_ICCIAR 0x0C // Interrupt Acknowledge Register\r
56#define ARM_GIC_ICCEIOR 0x10 // End Of Interrupt Register\r
57#define ARM_GIC_ICCRPR 0x14 // Running Priority Register\r
58#define ARM_GIC_ICCPIR 0x18 // Highest Pending Interrupt Register\r
59#define ARM_GIC_ICCABPR 0x1C // Aliased Binary Point Register\r
60#define ARM_GIC_ICCIDR 0xFC // Identification Register\r
61\r
62#define ARM_GIC_ICDSGIR_FILTER_TARGETLIST 0x0\r
63#define ARM_GIC_ICDSGIR_FILTER_EVERYONEELSE 0x1\r
64#define ARM_GIC_ICDSGIR_FILTER_ITSELF 0x2\r
65\r
66// Bit-masks to configure the CPU Interface Control register\r
67#define ARM_GIC_ICCICR_ENABLE_SECURE 0x01\r
68#define ARM_GIC_ICCICR_ENABLE_NS 0x02\r
69#define ARM_GIC_ICCICR_ACK_CTL 0x04\r
70#define ARM_GIC_ICCICR_SIGNAL_SECURE_TO_FIQ 0x08\r
71#define ARM_GIC_ICCICR_USE_SBPR 0x10\r
72\r
73\r
74//\r
92534106 75// GIC Secure interfaces\r
55a0d64b 76//\r
77VOID\r
78EFIAPI\r
79ArmGicSetupNonSecure (\r
80 IN INTN GicDistributorBase,\r
81 IN INTN GicInterruptInterfaceBase\r
82 );\r
83\r
92534106 84VOID\r
85EFIAPI\r
86ArmGicSetSecureInterrupts (\r
87 IN UINTN GicDistributorBase,\r
88 IN UINTN* GicSecureInterruptMask,\r
89 IN UINTN GicSecureInterruptMaskSize\r
90 );\r
91\r
55a0d64b 92VOID\r
93EFIAPI\r
94ArmGicEnableInterruptInterface (\r
95 IN INTN GicInterruptInterfaceBase\r
96 );\r
97\r
98VOID\r
99EFIAPI\r
100ArmGicEnableDistributor (\r
101 IN INTN GicDistributorBase\r
102 );\r
103\r
104VOID\r
105EFIAPI\r
106ArmGicSendSgiTo (\r
107 IN INTN GicDistributorBase,\r
108 IN INTN TargetListFilter,\r
109 IN INTN CPUTargetList\r
110 );\r
111\r
112UINT32\r
113EFIAPI\r
114ArmGicAcknowledgeSgiFrom (\r
115 IN INTN GicInterruptInterfaceBase,\r
116 IN INTN CoreId\r
117 );\r
118\r
119UINT32\r
120EFIAPI\r
121ArmGicAcknowledgeSgi2From (\r
122 IN INTN GicInterruptInterfaceBase,\r
123 IN INTN CoreId,\r
124 IN INTN SgiId\r
125 );\r
126\r
127UINTN\r
128EFIAPI\r
129ArmGicSetPriorityMask (\r
130 IN INTN GicInterruptInterfaceBase,\r
131 IN INTN PriorityMask\r
132 );\r
133\r
134#endif\r