[mirror_edk2.git] / ArmPkg / Include / Library / ArmLib.h

/** @file\r
\r
  Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
  Copyright (c) 2011 - 2016, ARM Ltd. All rights reserved.<BR>\r
\r
  This program and the accompanying materials\r
  are licensed and made available under the terms and conditions of the BSD License\r
  which accompanies this distribution.  The full text of the license may be found at\r
  http://opensource.org/licenses/bsd-license.php\r
\r
  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
**/\r
\r
#ifndef __ARM_LIB__\r
#define __ARM_LIB__\r
\r
#include <Uefi/UefiBaseType.h>\r
\r
#ifdef MDE_CPU_ARM\r
  #include <Chipset/ArmV7.h>\r
#elif defined(MDE_CPU_AARCH64)\r
  #include <Chipset/AArch64.h>\r
#else\r
 #error "Unknown chipset."\r
#endif\r
\r
#define EFI_MEMORY_CACHETYPE_MASK   (EFI_MEMORY_UC | EFI_MEMORY_WC | \\r
                                     EFI_MEMORY_WT | EFI_MEMORY_WB | \\r
                                     EFI_MEMORY_UCE)\r
\r
/**\r
 * The UEFI firmware must not use the ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_* attributes.\r
 *\r
 * The Non Secure memory attribute (ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_*) should only\r
 * be used in Secure World to distinguished Secure to Non-Secure memory.\r
 */\r
typedef enum {\r
  ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED = 0,\r
  ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_UNCACHED_UNBUFFERED,\r
  ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK,\r
  ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK,\r
\r
  // On some platforms, memory mapped flash region is designed as not supporting\r
  // shareable attribute, so WRITE_BACK_NONSHAREABLE is added for such special\r
  // need.\r
  // Do NOT use below two attributes if you are not sure.\r
  ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK_NONSHAREABLE,\r
  ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK_NONSHAREABLE,\r
\r
  ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH,\r
  ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_THROUGH,\r
  ARM_MEMORY_REGION_ATTRIBUTE_DEVICE,\r
  ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_DEVICE\r
} ARM_MEMORY_REGION_ATTRIBUTES;\r
\r
#define IS_ARM_MEMORY_REGION_ATTRIBUTES_SECURE(attr) ((UINT32)(attr) & 1)\r
\r
typedef struct {\r
  EFI_PHYSICAL_ADDRESS          PhysicalBase;\r
  EFI_VIRTUAL_ADDRESS           VirtualBase;\r
  UINT64                        Length;\r
  ARM_MEMORY_REGION_ATTRIBUTES  Attributes;\r
} ARM_MEMORY_REGION_DESCRIPTOR;\r
\r
typedef VOID (*CACHE_OPERATION)(VOID);\r
typedef VOID (*LINE_OPERATION)(UINTN);\r
\r
//\r
// ARM Processor Mode\r
//\r
typedef enum {\r
  ARM_PROCESSOR_MODE_USER       = 0x10,\r
  ARM_PROCESSOR_MODE_FIQ        = 0x11,\r
  ARM_PROCESSOR_MODE_IRQ        = 0x12,\r
  ARM_PROCESSOR_MODE_SUPERVISOR = 0x13,\r
  ARM_PROCESSOR_MODE_ABORT      = 0x17,\r
  ARM_PROCESSOR_MODE_HYP        = 0x1A,\r
  ARM_PROCESSOR_MODE_UNDEFINED  = 0x1B,\r
  ARM_PROCESSOR_MODE_SYSTEM     = 0x1F,\r
  ARM_PROCESSOR_MODE_MASK       = 0x1F\r
} ARM_PROCESSOR_MODE;\r
\r
//\r
// ARM Cpu IDs\r
//\r
#define ARM_CPU_IMPLEMENTER_MASK          (0xFFU << 24)\r
#define ARM_CPU_IMPLEMENTER_ARMLTD        (0x41U << 24)\r
#define ARM_CPU_IMPLEMENTER_DEC           (0x44U << 24)\r
#define ARM_CPU_IMPLEMENTER_MOT           (0x4DU << 24)\r
#define ARM_CPU_IMPLEMENTER_QUALCOMM      (0x51U << 24)\r
#define ARM_CPU_IMPLEMENTER_MARVELL       (0x56U << 24)\r
\r
#define ARM_CPU_PRIMARY_PART_MASK         (0xFFF << 4)\r
#define ARM_CPU_PRIMARY_PART_CORTEXA5     (0xC05 << 4)\r
#define ARM_CPU_PRIMARY_PART_CORTEXA7     (0xC07 << 4)\r
#define ARM_CPU_PRIMARY_PART_CORTEXA8     (0xC08 << 4)\r
#define ARM_CPU_PRIMARY_PART_CORTEXA9     (0xC09 << 4)\r
#define ARM_CPU_PRIMARY_PART_CORTEXA15    (0xC0F << 4)\r
\r
//\r
// ARM MP Core IDs\r
//\r
#define ARM_CORE_AFF0         0xFF\r
#define ARM_CORE_AFF1         (0xFF << 8)\r
#define ARM_CORE_AFF2         (0xFF << 16)\r
#define ARM_CORE_AFF3         (0xFFULL << 32)\r
\r
#define ARM_CORE_MASK         ARM_CORE_AFF0\r
#define ARM_CLUSTER_MASK      ARM_CORE_AFF1\r
#define GET_CORE_ID(MpId)     ((MpId) & ARM_CORE_MASK)\r
#define GET_CLUSTER_ID(MpId)  (((MpId) & ARM_CLUSTER_MASK) >> 8)\r
#define GET_MPID(ClusterId, CoreId)   (((ClusterId) << 8) | (CoreId))\r
#define PRIMARY_CORE_ID       (PcdGet32(PcdArmPrimaryCore) & ARM_CORE_MASK)\r
\r
UINTN\r
EFIAPI\r
ArmDataCacheLineLength (\r
  VOID\r
  );\r
\r
UINTN\r
EFIAPI\r
ArmInstructionCacheLineLength (\r
  VOID\r
  );\r
\r
UINTN\r
EFIAPI\r
ArmCacheWritebackGranule (\r
  VOID\r
  );\r
\r
UINTN\r
EFIAPI\r
ArmIsArchTimerImplemented (\r
  VOID\r
  );\r
\r
UINTN\r
EFIAPI\r
ArmReadIdPfr0 (\r
  VOID\r
  );\r
\r
UINTN\r
EFIAPI\r
ArmReadIdPfr1 (\r
  VOID\r
  );\r
\r
UINTN\r
EFIAPI\r
ArmCacheInfo (\r
  VOID\r
  );\r
\r
BOOLEAN\r
EFIAPI\r
ArmIsMpCore (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmInvalidateDataCache (\r
  VOID\r
  );\r
\r
\r
VOID\r
EFIAPI\r
ArmCleanInvalidateDataCache (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmCleanDataCache (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmInvalidateInstructionCache (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmInvalidateDataCacheEntryByMVA (\r
  IN  UINTN   Address\r
  );\r
\r
VOID\r
EFIAPI\r
ArmCleanDataCacheEntryToPoUByMVA (\r
  IN  UINTN   Address\r
  );\r
\r
VOID\r
EFIAPI\r
ArmInvalidateInstructionCacheEntryToPoUByMVA (\r
  IN  UINTN   Address\r
  );\r
\r
VOID\r
EFIAPI\r
ArmCleanDataCacheEntryByMVA (\r
IN  UINTN   Address\r
);\r
\r
VOID\r
EFIAPI\r
ArmCleanInvalidateDataCacheEntryByMVA (\r
  IN  UINTN   Address\r
  );\r
\r
VOID\r
EFIAPI\r
ArmInvalidateDataCacheEntryBySetWay (\r
  IN  UINTN  SetWayFormat\r
  );\r
\r
VOID\r
EFIAPI\r
ArmCleanDataCacheEntryBySetWay (\r
  IN  UINTN  SetWayFormat\r
  );\r
\r
VOID\r
EFIAPI\r
ArmCleanInvalidateDataCacheEntryBySetWay (\r
  IN  UINTN   SetWayFormat\r
  );\r
\r
VOID\r
EFIAPI\r
ArmEnableDataCache (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmDisableDataCache (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmEnableInstructionCache (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmDisableInstructionCache (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmEnableMmu (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmDisableMmu (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmEnableCachesAndMmu (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmDisableCachesAndMmu (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmEnableInterrupts (\r
  VOID\r
  );\r
\r
UINTN\r
EFIAPI\r
ArmDisableInterrupts (\r
  VOID\r
  );\r
\r
BOOLEAN\r
EFIAPI\r
ArmGetInterruptState (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmEnableAsynchronousAbort (\r
  VOID\r
  );\r
\r
UINTN\r
EFIAPI\r
ArmDisableAsynchronousAbort (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmEnableIrq (\r
  VOID\r
  );\r
\r
UINTN\r
EFIAPI\r
ArmDisableIrq (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmEnableFiq (\r
  VOID\r
  );\r
\r
UINTN\r
EFIAPI\r
ArmDisableFiq (\r
  VOID\r
  );\r
\r
BOOLEAN\r
EFIAPI\r
ArmGetFiqState (\r
  VOID\r
  );\r
\r
/**\r
 * Invalidate Data and Instruction TLBs\r
 */\r
VOID\r
EFIAPI\r
ArmInvalidateTlb (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmUpdateTranslationTableEntry (\r
  IN  VOID     *TranslationTableEntry,\r
  IN  VOID     *Mva\r
  );\r
\r
VOID\r
EFIAPI\r
ArmSetDomainAccessControl (\r
  IN  UINT32  Domain\r
  );\r
\r
VOID\r
EFIAPI\r
ArmSetTTBR0 (\r
  IN  VOID  *TranslationTableBase\r
  );\r
\r
VOID\r
EFIAPI\r
ArmSetTTBCR (\r
  IN  UINT32 Bits\r
  );\r
\r
VOID *\r
EFIAPI\r
ArmGetTTBR0BaseAddress (\r
  VOID\r
  );\r
\r
BOOLEAN\r
EFIAPI\r
ArmMmuEnabled (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmEnableBranchPrediction (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmDisableBranchPrediction (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmSetLowVectors (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmSetHighVectors (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmDataMemoryBarrier (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmDataSynchronizationBarrier (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmInstructionSynchronizationBarrier (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmWriteVBar (\r
  IN  UINTN   VectorBase\r
  );\r
\r
UINTN\r
EFIAPI\r
ArmReadVBar (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmWriteAuxCr (\r
  IN  UINT32    Bit\r
  );\r
\r
UINT32\r
EFIAPI\r
ArmReadAuxCr (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmSetAuxCrBit (\r
  IN  UINT32    Bits\r
  );\r
\r
VOID\r
EFIAPI\r
ArmUnsetAuxCrBit (\r
  IN  UINT32    Bits\r
  );\r
\r
VOID\r
EFIAPI\r
ArmCallSEV (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmCallWFE (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmCallWFI (\r
\r
  VOID\r
  );\r
\r
UINTN\r
EFIAPI\r
ArmReadMpidr (\r
  VOID\r
  );\r
\r
UINTN\r
EFIAPI\r
ArmReadMidr (\r
  VOID\r
  );\r
\r
UINT32\r
EFIAPI\r
ArmReadCpacr (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmWriteCpacr (\r
  IN  UINT32   Access\r
  );\r
\r
VOID\r
EFIAPI\r
ArmEnableVFP (\r
  VOID\r
  );\r
\r
/**\r
  Get the Secure Configuration Register value\r
\r
  @return   Value read from the Secure Configuration Register\r
\r
**/\r
UINT32\r
EFIAPI\r
ArmReadScr (\r
  VOID\r
  );\r
\r
/**\r
  Set the Secure Configuration Register\r
\r
  @param Value   Value to write to the Secure Configuration Register\r
\r
**/\r
VOID\r
EFIAPI\r
ArmWriteScr (\r
  IN  UINT32   Value\r
  );\r
\r
UINT32\r
EFIAPI\r
ArmReadMVBar (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmWriteMVBar (\r
  IN  UINT32   VectorMonitorBase\r
  );\r
\r
UINT32\r
EFIAPI\r
ArmReadSctlr (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmWriteSctlr (\r
  IN  UINT32   Value\r
  );\r
\r
UINTN\r
EFIAPI\r
ArmReadHVBar (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmWriteHVBar (\r
  IN  UINTN   HypModeVectorBase\r
  );\r
\r
\r
//\r
// Helper functions for accessing CPU ACTLR\r
//\r
\r
UINTN\r
EFIAPI\r
ArmReadCpuActlr (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmWriteCpuActlr (\r
  IN  UINTN Val\r
  );\r
\r
VOID\r
EFIAPI\r
ArmSetCpuActlrBit (\r
  IN  UINTN    Bits\r
  );\r
\r
VOID\r
EFIAPI\r
ArmUnsetCpuActlrBit (\r
  IN  UINTN    Bits\r
  );\r
\r
//\r
// Accessors for the architected generic timer registers\r
//\r
\r
#define ARM_ARCH_TIMER_ENABLE           (1 << 0)\r
#define ARM_ARCH_TIMER_IMASK            (1 << 1)\r
#define ARM_ARCH_TIMER_ISTATUS          (1 << 2)\r
\r
UINTN\r
EFIAPI\r
ArmReadCntFrq (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmWriteCntFrq (\r
  UINTN   FreqInHz\r
  );\r
\r
UINT64\r
EFIAPI\r
ArmReadCntPct (\r
  VOID\r
  );\r
\r
UINTN\r
EFIAPI\r
ArmReadCntkCtl (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmWriteCntkCtl (\r
  UINTN   Val\r
  );\r
\r
UINTN\r
EFIAPI\r
ArmReadCntpTval (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmWriteCntpTval (\r
  UINTN   Val\r
  );\r
\r
UINTN\r
EFIAPI\r
ArmReadCntpCtl (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmWriteCntpCtl (\r
  UINTN   Val\r
  );\r
\r
UINTN\r
EFIAPI\r
ArmReadCntvTval (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmWriteCntvTval (\r
  UINTN   Val\r
  );\r
\r
UINTN\r
EFIAPI\r
ArmReadCntvCtl (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmWriteCntvCtl (\r
  UINTN   Val\r
  );\r
\r
UINT64\r
EFIAPI\r
ArmReadCntvCt (\r
  VOID\r
  );\r
\r
UINT64\r
EFIAPI\r
ArmReadCntpCval (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmWriteCntpCval (\r
  UINT64   Val\r
  );\r
\r
UINT64\r
EFIAPI\r
ArmReadCntvCval (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmWriteCntvCval (\r
  UINT64   Val\r
  );\r
\r
UINT64\r
EFIAPI\r
ArmReadCntvOff (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmWriteCntvOff (\r
  UINT64   Val\r
  );\r
\r
UINTN\r
EFIAPI\r
ArmGetPhysicalAddressBits (\r
  VOID\r
  );\r
\r
#endif // __ARM_LIB__\r
Commit	Line	Data
1e57a462	1	/** @file\r
	2	\r
	3	Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
ff1f27c0	4	Copyright (c) 2011 - 2016, ARM Ltd. All rights reserved.<BR>\r
1e57a462	5	\r
	6	This program and the accompanying materials\r
	7	are licensed and made available under the terms and conditions of the BSD License\r
	8	which accompanies this distribution. The full text of the license may be found at\r
	9	http://opensource.org/licenses/bsd-license.php\r
	10	\r
	11	THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
	12	WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
	13	\r
	14	**/\r
	15	\r
	16	#ifndef __ARM_LIB__\r
	17	#define __ARM_LIB__\r
	18	\r
	19	#include <Uefi/UefiBaseType.h>\r
	20	\r
25402f5d	21	#ifdef MDE_CPU_ARM\r
70119d27	22	#include <Chipset/ArmV7.h>\r
25402f5d HL	23	#elif defined(MDE_CPU_AARCH64)\r
25402f5d HL	24	#include <Chipset/AArch64.h>\r
1e57a462	25	#else\r
25402f5d	26	#error "Unknown chipset."\r
1e57a462	27	#endif\r
1e57a462	28	\r
e0307a7d AB	29	#define EFI_MEMORY_CACHETYPE_MASK (EFI_MEMORY_UC \| EFI_MEMORY_WC \| \\r
	30	EFI_MEMORY_WT \| EFI_MEMORY_WB \| \\r
	31	EFI_MEMORY_UCE)\r
	32	\r
1e57a462	33	/**\r
	34	* The UEFI firmware must not use the ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_* attributes.\r
	35	*\r
	36	* The Non Secure memory attribute (ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_*) should only\r
	37	* be used in Secure World to distinguished Secure to Non-Secure memory.\r
	38	*/\r
	39	typedef enum {\r
	40	ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED = 0,\r
	41	ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_UNCACHED_UNBUFFERED,\r
	42	ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK,\r
	43	ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK,\r
829633e3 PL	44	\r
	45	// On some platforms, memory mapped flash region is designed as not supporting\r
	46	// shareable attribute, so WRITE_BACK_NONSHAREABLE is added for such special\r
	47	// need.\r
	48	// Do NOT use below two attributes if you are not sure.\r
	49	ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK_NONSHAREABLE,\r
	50	ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK_NONSHAREABLE,\r
	51	\r
1e57a462	52	ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH,\r
	53	ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_THROUGH,\r
	54	ARM_MEMORY_REGION_ATTRIBUTE_DEVICE,\r
	55	ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_DEVICE\r
	56	} ARM_MEMORY_REGION_ATTRIBUTES;\r
	57	\r
	58	#define IS_ARM_MEMORY_REGION_ATTRIBUTES_SECURE(attr) ((UINT32)(attr) & 1)\r
	59	\r
	60	typedef struct {\r
	61	EFI_PHYSICAL_ADDRESS PhysicalBase;\r
	62	EFI_VIRTUAL_ADDRESS VirtualBase;\r
c357fd6a	63	UINT64 Length;\r
1e57a462	64	ARM_MEMORY_REGION_ATTRIBUTES Attributes;\r
	65	} ARM_MEMORY_REGION_DESCRIPTOR;\r
	66	\r
	67	typedef VOID (*CACHE_OPERATION)(VOID);\r
	68	typedef VOID (*LINE_OPERATION)(UINTN);\r
	69	\r
	70	//\r
	71	// ARM Processor Mode\r
	72	//\r
	73	typedef enum {\r
	74	ARM_PROCESSOR_MODE_USER = 0x10,\r
	75	ARM_PROCESSOR_MODE_FIQ = 0x11,\r
	76	ARM_PROCESSOR_MODE_IRQ = 0x12,\r
	77	ARM_PROCESSOR_MODE_SUPERVISOR = 0x13,\r
	78	ARM_PROCESSOR_MODE_ABORT = 0x17,\r
	79	ARM_PROCESSOR_MODE_HYP = 0x1A,\r
	80	ARM_PROCESSOR_MODE_UNDEFINED = 0x1B,\r
	81	ARM_PROCESSOR_MODE_SYSTEM = 0x1F,\r
	82	ARM_PROCESSOR_MODE_MASK = 0x1F\r
	83	} ARM_PROCESSOR_MODE;\r
	84	\r
	85	//\r
	86	// ARM Cpu IDs\r
	87	//\r
	88	#define ARM_CPU_IMPLEMENTER_MASK (0xFFU << 24)\r
	89	#define ARM_CPU_IMPLEMENTER_ARMLTD (0x41U << 24)\r
	90	#define ARM_CPU_IMPLEMENTER_DEC (0x44U << 24)\r
	91	#define ARM_CPU_IMPLEMENTER_MOT (0x4DU << 24)\r
	92	#define ARM_CPU_IMPLEMENTER_QUALCOMM (0x51U << 24)\r
	93	#define ARM_CPU_IMPLEMENTER_MARVELL (0x56U << 24)\r
	94	\r
	95	#define ARM_CPU_PRIMARY_PART_MASK (0xFFF << 4)\r
	96	#define ARM_CPU_PRIMARY_PART_CORTEXA5 (0xC05 << 4)\r
	97	#define ARM_CPU_PRIMARY_PART_CORTEXA7 (0xC07 << 4)\r
	98	#define ARM_CPU_PRIMARY_PART_CORTEXA8 (0xC08 << 4)\r
	99	#define ARM_CPU_PRIMARY_PART_CORTEXA9 (0xC09 << 4)\r
	100	#define ARM_CPU_PRIMARY_PART_CORTEXA15 (0xC0F << 4)\r
	101	\r
	102	//\r
	103	// ARM MP Core IDs\r
	104	//\r
90ed18ca OM	105	#define ARM_CORE_AFF0 0xFF\r
	106	#define ARM_CORE_AFF1 (0xFF << 8)\r
	107	#define ARM_CORE_AFF2 (0xFF << 16)\r
	108	#define ARM_CORE_AFF3 (0xFFULL << 32)\r
	109	\r
	110	#define ARM_CORE_MASK ARM_CORE_AFF0\r
	111	#define ARM_CLUSTER_MASK ARM_CORE_AFF1\r
1e57a462	112	#define GET_CORE_ID(MpId) ((MpId) & ARM_CORE_MASK)\r
1e57a462	113	#define GET_CLUSTER_ID(MpId) (((MpId) & ARM_CLUSTER_MASK) >> 8)\r
e359565e	114	#define GET_MPID(ClusterId, CoreId) (((ClusterId) << 8) \| (CoreId))\r
1e57a462	115	#define PRIMARY_CORE_ID (PcdGet32(PcdArmPrimaryCore) & ARM_CORE_MASK)\r
1e57a462	116	\r
1e57a462	117	UINTN\r
	118	EFIAPI\r
	119	ArmDataCacheLineLength (\r
	120	VOID\r
	121	);\r
3402aac7	122	\r
1e57a462	123	UINTN\r
	124	EFIAPI\r
	125	ArmInstructionCacheLineLength (\r
	126	VOID\r
	127	);\r
168d7245	128	\r
c653fc2a AB	129	UINTN\r
	130	EFIAPI\r
	131	ArmCacheWritebackGranule (\r
	132	VOID\r
	133	);\r
	134	\r
168d7245 OM	135	UINTN\r
	136	EFIAPI\r
	137	ArmIsArchTimerImplemented (\r
	138	VOID\r
	139	);\r
	140	\r
	141	UINTN\r
	142	EFIAPI\r
	143	ArmReadIdPfr0 (\r
	144	VOID\r
	145	);\r
	146	\r
	147	UINTN\r
	148	EFIAPI\r
	149	ArmReadIdPfr1 (\r
	150	VOID\r
	151	);\r
	152	\r
64751727	153	UINTN\r
1e57a462	154	EFIAPI\r
64751727	155	ArmCacheInfo (\r
1e57a462	156	VOID\r
	157	);\r
	158	\r
	159	BOOLEAN\r
	160	EFIAPI\r
	161	ArmIsMpCore (\r
	162	VOID\r
	163	);\r
	164	\r
	165	VOID\r
	166	EFIAPI\r
	167	ArmInvalidateDataCache (\r
	168	VOID\r
	169	);\r
	170	\r
	171	\r
	172	VOID\r
	173	EFIAPI\r
	174	ArmCleanInvalidateDataCache (\r
	175	VOID\r
	176	);\r
	177	\r
	178	VOID\r
	179	EFIAPI\r
	180	ArmCleanDataCache (\r
	181	VOID\r
	182	);\r
	183	\r
1e57a462	184	VOID\r
	185	EFIAPI\r
	186	ArmInvalidateInstructionCache (\r
	187	VOID\r
	188	);\r
	189	\r
	190	VOID\r
	191	EFIAPI\r
	192	ArmInvalidateDataCacheEntryByMVA (\r
	193	IN UINTN Address\r
	194	);\r
	195	\r
	196	VOID\r
	197	EFIAPI\r
cf580da1	198	ArmCleanDataCacheEntryToPoUByMVA (\r
1e57a462	199	IN UINTN Address\r
	200	);\r
	201	\r
b7de7e3c EC	202	VOID\r
b7de7e3c EC	203	EFIAPI\r
cf580da1 AB	204	ArmInvalidateInstructionCacheEntryToPoUByMVA (\r
	205	IN UINTN Address\r
	206	);\r
	207	\r
	208	VOID\r
	209	EFIAPI\r
	210	ArmCleanDataCacheEntryByMVA (\r
b7de7e3c EC	211	IN UINTN Address\r
	212	);\r
	213	\r
1e57a462	214	VOID\r
	215	EFIAPI\r
	216	ArmCleanInvalidateDataCacheEntryByMVA (\r
	217	IN UINTN Address\r
	218	);\r
	219	\r
0ff0e414 OM	220	VOID\r
	221	EFIAPI\r
	222	ArmInvalidateDataCacheEntryBySetWay (\r
	223	IN UINTN SetWayFormat\r
	224	);\r
	225	\r
	226	VOID\r
	227	EFIAPI\r
	228	ArmCleanDataCacheEntryBySetWay (\r
	229	IN UINTN SetWayFormat\r
	230	);\r
	231	\r
	232	VOID\r
	233	EFIAPI\r
	234	ArmCleanInvalidateDataCacheEntryBySetWay (\r
	235	IN UINTN SetWayFormat\r
	236	);\r
	237	\r
1e57a462	238	VOID\r
	239	EFIAPI\r
	240	ArmEnableDataCache (\r
	241	VOID\r
	242	);\r
	243	\r
	244	VOID\r
	245	EFIAPI\r
	246	ArmDisableDataCache (\r
	247	VOID\r
	248	);\r
	249	\r
	250	VOID\r
	251	EFIAPI\r
	252	ArmEnableInstructionCache (\r
	253	VOID\r
	254	);\r
	255	\r
	256	VOID\r
	257	EFIAPI\r
	258	ArmDisableInstructionCache (\r
	259	VOID\r
	260	);\r
3402aac7	261	\r
1e57a462	262	VOID\r
	263	EFIAPI\r
	264	ArmEnableMmu (\r
	265	VOID\r
	266	);\r
	267	\r
	268	VOID\r
	269	EFIAPI\r
	270	ArmDisableMmu (\r
	271	VOID\r
	272	);\r
	273	\r
0ff0e414 OM	274	VOID\r
	275	EFIAPI\r
	276	ArmEnableCachesAndMmu (\r
	277	VOID\r
	278	);\r
	279	\r
1e57a462	280	VOID\r
	281	EFIAPI\r
	282	ArmDisableCachesAndMmu (\r
	283	VOID\r
	284	);\r
	285	\r
1e57a462	286	VOID\r
	287	EFIAPI\r
	288	ArmEnableInterrupts (\r
	289	VOID\r
	290	);\r
	291	\r
	292	UINTN\r
	293	EFIAPI\r
	294	ArmDisableInterrupts (\r
	295	VOID\r
	296	);\r
47585ed5	297	\r
1e57a462	298	BOOLEAN\r
	299	EFIAPI\r
	300	ArmGetInterruptState (\r
	301	VOID\r
	302	);\r
	303	\r
0ff0e414 OM	304	VOID\r
	305	EFIAPI\r
	306	ArmEnableAsynchronousAbort (\r
	307	VOID\r
	308	);\r
	309	\r
47585ed5	310	UINTN\r
47585ed5	311	EFIAPI\r
0ff0e414	312	ArmDisableAsynchronousAbort (\r
47585ed5	313	VOID\r
	314	);\r
	315	\r
	316	VOID\r
	317	EFIAPI\r
	318	ArmEnableIrq (\r
	319	VOID\r
	320	);\r
	321	\r
0ff0e414 OM	322	UINTN\r
	323	EFIAPI\r
	324	ArmDisableIrq (\r
	325	VOID\r
	326	);\r
	327	\r
1e57a462	328	VOID\r
	329	EFIAPI\r
	330	ArmEnableFiq (\r
	331	VOID\r
	332	);\r
	333	\r
	334	UINTN\r
	335	EFIAPI\r
	336	ArmDisableFiq (\r
	337	VOID\r
	338	);\r
3402aac7	339	\r
1e57a462	340	BOOLEAN\r
	341	EFIAPI\r
	342	ArmGetFiqState (\r
	343	VOID\r
	344	);\r
	345	\r
8dd618d2 OM	346	/**\r
	347	* Invalidate Data and Instruction TLBs\r
	348	*/\r
1e57a462	349	VOID\r
	350	EFIAPI\r
	351	ArmInvalidateTlb (\r
	352	VOID\r
	353	);\r
3402aac7	354	\r
1e57a462	355	VOID\r
	356	EFIAPI\r
	357	ArmUpdateTranslationTableEntry (\r
	358	IN VOID *TranslationTableEntry,\r
	359	IN VOID *Mva\r
	360	);\r
3402aac7	361	\r
1e57a462	362	VOID\r
	363	EFIAPI\r
	364	ArmSetDomainAccessControl (\r
	365	IN UINT32 Domain\r
	366	);\r
	367	\r
	368	VOID\r
	369	EFIAPI\r
	370	ArmSetTTBR0 (\r
	371	IN VOID *TranslationTableBase\r
	372	);\r
	373	\r
ff1f27c0 EL	374	VOID\r
	375	EFIAPI\r
	376	ArmSetTTBCR (\r
	377	IN UINT32 Bits\r
	378	);\r
	379	\r
1e57a462	380	VOID *\r
	381	EFIAPI\r
	382	ArmGetTTBR0BaseAddress (\r
	383	VOID\r
	384	);\r
	385	\r
1e57a462	386	BOOLEAN\r
	387	EFIAPI\r
	388	ArmMmuEnabled (\r
	389	VOID\r
	390	);\r
3402aac7	391	\r
1e57a462	392	VOID\r
	393	EFIAPI\r
	394	ArmEnableBranchPrediction (\r
	395	VOID\r
	396	);\r
	397	\r
	398	VOID\r
	399	EFIAPI\r
	400	ArmDisableBranchPrediction (\r
	401	VOID\r
	402	);\r
	403	\r
	404	VOID\r
	405	EFIAPI\r
	406	ArmSetLowVectors (\r
	407	VOID\r
	408	);\r
	409	\r
	410	VOID\r
	411	EFIAPI\r
	412	ArmSetHighVectors (\r
	413	VOID\r
	414	);\r
	415	\r
	416	VOID\r
	417	EFIAPI\r
	418	ArmDataMemoryBarrier (\r
	419	VOID\r
	420	);\r
3402aac7	421	\r
1e57a462	422	VOID\r
1e57a462	423	EFIAPI\r
cf93a378	424	ArmDataSynchronizationBarrier (\r
1e57a462	425	VOID\r
1e57a462	426	);\r
3402aac7	427	\r
1e57a462	428	VOID\r
	429	EFIAPI\r
	430	ArmInstructionSynchronizationBarrier (\r
	431	VOID\r
	432	);\r
	433	\r
	434	VOID\r
	435	EFIAPI\r
	436	ArmWriteVBar (\r
4e57d6d7	437	IN UINTN VectorBase\r
1e57a462	438	);\r
1e57a462	439	\r
4e57d6d7	440	UINTN\r
1e57a462	441	EFIAPI\r
	442	ArmReadVBar (\r
	443	VOID\r
	444	);\r
	445	\r
	446	VOID\r
	447	EFIAPI\r
	448	ArmWriteAuxCr (\r
	449	IN UINT32 Bit\r
	450	);\r
	451	\r
	452	UINT32\r
	453	EFIAPI\r
	454	ArmReadAuxCr (\r
	455	VOID\r
	456	);\r
	457	\r
	458	VOID\r
	459	EFIAPI\r
	460	ArmSetAuxCrBit (\r
	461	IN UINT32 Bits\r
	462	);\r
	463	\r
	464	VOID\r
	465	EFIAPI\r
	466	ArmUnsetAuxCrBit (\r
	467	IN UINT32 Bits\r
	468	);\r
	469	\r
	470	VOID\r
	471	EFIAPI\r
	472	ArmCallSEV (\r
	473	VOID\r
	474	);\r
	475	\r
	476	VOID\r
	477	EFIAPI\r
	478	ArmCallWFE (\r
	479	VOID\r
	480	);\r
	481	\r
	482	VOID\r
	483	EFIAPI\r
	484	ArmCallWFI (\r
25402f5d	485	\r
1e57a462	486	VOID\r
	487	);\r
	488	\r
	489	UINTN\r
	490	EFIAPI\r
	491	ArmReadMpidr (\r
	492	VOID\r
	493	);\r
	494	\r
9401d6f4 OM	495	UINTN\r
	496	EFIAPI\r
	497	ArmReadMidr (\r
	498	VOID\r
	499	);\r
	500	\r
1e57a462	501	UINT32\r
	502	EFIAPI\r
	503	ArmReadCpacr (\r
	504	VOID\r
	505	);\r
	506	\r
	507	VOID\r
	508	EFIAPI\r
	509	ArmWriteCpacr (\r
	510	IN UINT32 Access\r
	511	);\r
	512	\r
	513	VOID\r
	514	EFIAPI\r
	515	ArmEnableVFP (\r
	516	VOID\r
	517	);\r
	518	\r
46d4d75c OM	519	/**\r
	520	Get the Secure Configuration Register value\r
	521	\r
	522	@return Value read from the Secure Configuration Register\r
	523	\r
	524	**/\r
1e57a462	525	UINT32\r
	526	EFIAPI\r
	527	ArmReadScr (\r
	528	VOID\r
	529	);\r
	530	\r
46d4d75c OM	531	/**\r
	532	Set the Secure Configuration Register\r
	533	\r
	534	@param Value Value to write to the Secure Configuration Register\r
	535	\r
	536	**/\r
1e57a462	537	VOID\r
	538	EFIAPI\r
	539	ArmWriteScr (\r
46d4d75c	540	IN UINT32 Value\r
1e57a462	541	);\r
	542	\r
	543	UINT32\r
	544	EFIAPI\r
	545	ArmReadMVBar (\r
	546	VOID\r
	547	);\r
	548	\r
	549	VOID\r
	550	EFIAPI\r
	551	ArmWriteMVBar (\r
	552	IN UINT32 VectorMonitorBase\r
	553	);\r
	554	\r
	555	UINT32\r
	556	EFIAPI\r
	557	ArmReadSctlr (\r
	558	VOID\r
	559	);\r
	560	\r
1e1d1697 MZ	561	VOID\r
	562	EFIAPI\r
	563	ArmWriteSctlr (\r
	564	IN UINT32 Value\r
	565	);\r
	566	\r
5ea2c2d3	567	UINTN\r
	568	EFIAPI\r
	569	ArmReadHVBar (\r
	570	VOID\r
	571	);\r
	572	\r
	573	VOID\r
	574	EFIAPI\r
	575	ArmWriteHVBar (\r
	576	IN UINTN HypModeVectorBase\r
	577	);\r
	578	\r
52d44f77 OM	579	\r
	580	//\r
	581	// Helper functions for accessing CPU ACTLR\r
	582	//\r
	583	\r
	584	UINTN\r
	585	EFIAPI\r
	586	ArmReadCpuActlr (\r
	587	VOID\r
	588	);\r
	589	\r
	590	VOID\r
	591	EFIAPI\r
	592	ArmWriteCpuActlr (\r
	593	IN UINTN Val\r
	594	);\r
	595	\r
	596	VOID\r
	597	EFIAPI\r
	598	ArmSetCpuActlrBit (\r
	599	IN UINTN Bits\r
	600	);\r
	601	\r
	602	VOID\r
	603	EFIAPI\r
	604	ArmUnsetCpuActlrBit (\r
	605	IN UINTN Bits\r
	606	);\r
	607	\r
734bd6cc AB	608	//\r
	609	// Accessors for the architected generic timer registers\r
	610	//\r
	611	\r
	612	#define ARM_ARCH_TIMER_ENABLE (1 << 0)\r
	613	#define ARM_ARCH_TIMER_IMASK (1 << 1)\r
	614	#define ARM_ARCH_TIMER_ISTATUS (1 << 2)\r
	615	\r
	616	UINTN\r
	617	EFIAPI\r
	618	ArmReadCntFrq (\r
	619	VOID\r
	620	);\r
	621	\r
	622	VOID\r
	623	EFIAPI\r
	624	ArmWriteCntFrq (\r
	625	UINTN FreqInHz\r
	626	);\r
	627	\r
	628	UINT64\r
	629	EFIAPI\r
	630	ArmReadCntPct (\r
	631	VOID\r
	632	);\r
	633	\r
	634	UINTN\r
	635	EFIAPI\r
	636	ArmReadCntkCtl (\r
	637	VOID\r
	638	);\r
	639	\r
	640	VOID\r
	641	EFIAPI\r
	642	ArmWriteCntkCtl (\r
	643	UINTN Val\r
	644	);\r
	645	\r
	646	UINTN\r
	647	EFIAPI\r
	648	ArmReadCntpTval (\r
	649	VOID\r
	650	);\r
	651	\r
	652	VOID\r
	653	EFIAPI\r
	654	ArmWriteCntpTval (\r
	655	UINTN Val\r
	656	);\r
	657	\r
	658	UINTN\r
	659	EFIAPI\r
	660	ArmReadCntpCtl (\r
	661	VOID\r
	662	);\r
	663	\r
	664	VOID\r
	665	EFIAPI\r
	666	ArmWriteCntpCtl (\r
	667	UINTN Val\r
	668	);\r
	669	\r
	670	UINTN\r
	671	EFIAPI\r
672	ArmReadCntvTval (\r
673	VOID\r
674	);\r
675	\r
676	VOID\r
677	EFIAPI\r
678	ArmWriteCntvTval (\r
679	UINTN Val\r
680	);\r
681	\r
682	UINTN\r
683	EFIAPI\r
684	ArmReadCntvCtl (\r
685	VOID\r
686	);\r
687	\r
688	VOID\r
689	EFIAPI\r
690	ArmWriteCntvCtl (\r
691	UINTN Val\r
692	);\r
693	\r
694	UINT64\r
695	EFIAPI\r
696	ArmReadCntvCt (\r
697	VOID\r
698	);\r
699	\r
700	UINT64\r
701	EFIAPI\r
702	ArmReadCntpCval (\r
703	VOID\r
704	);\r
705	\r
706	VOID\r
707	EFIAPI\r
708	ArmWriteCntpCval (\r
709	UINT64 Val\r
710	);\r
711	\r
712	UINT64\r
713	EFIAPI\r
714	ArmReadCntvCval (\r
715	VOID\r
716	);\r
717	\r
718	VOID\r
719	EFIAPI\r
720	ArmWriteCntvCval (\r
721	UINT64 Val\r
722	);\r
723	\r
724	UINT64\r
725	EFIAPI\r
726	ArmReadCntvOff (\r
727	VOID\r
728	);\r
729	\r
730	VOID\r
731	EFIAPI\r
732	ArmWriteCntvOff (\r
733	UINT64 Val\r
734	);\r
735	\r
95d04ebc AB	736	UINTN\r
	737	EFIAPI\r
	738	ArmGetPhysicalAddressBits (\r
	739	VOID\r
	740	);\r
	741	\r
1e57a462	742	#endif // __ARM_LIB__\r