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1e57a462 | 1 | /** @file\r |
2 | \r | |
3 | Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r | |
ff1f27c0 | 4 | Copyright (c) 2011 - 2016, ARM Ltd. All rights reserved.<BR>\r |
a63914d3 | 5 | Copyright (c) 2020 - 2021, NUVIA Inc. All rights reserved.<BR>\r |
1e57a462 | 6 | \r |
4059386c | 7 | SPDX-License-Identifier: BSD-2-Clause-Patent\r |
1e57a462 | 8 | \r |
9 | **/\r | |
10 | \r | |
cc15a619 PG |
11 | #ifndef ARM_LIB_H_\r |
12 | #define ARM_LIB_H_\r | |
1e57a462 | 13 | \r |
14 | #include <Uefi/UefiBaseType.h>\r | |
15 | \r | |
25402f5d | 16 | #ifdef MDE_CPU_ARM\r |
70119d27 | 17 | #include <Chipset/ArmV7.h>\r |
429309e0 | 18 | #elif defined (MDE_CPU_AARCH64)\r |
25402f5d | 19 | #include <Chipset/AArch64.h>\r |
1e57a462 | 20 | #else\r |
429309e0 | 21 | #error "Unknown chipset."\r |
1e57a462 | 22 | #endif\r |
23 | \r | |
429309e0 | 24 | #define EFI_MEMORY_CACHETYPE_MASK (EFI_MEMORY_UC | EFI_MEMORY_WC | \\r |
e0307a7d AB |
25 | EFI_MEMORY_WT | EFI_MEMORY_WB | \\r |
26 | EFI_MEMORY_UCE)\r | |
27 | \r | |
1e57a462 | 28 | /**\r |
29 | * The UEFI firmware must not use the ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_* attributes.\r | |
30 | *\r | |
31 | * The Non Secure memory attribute (ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_*) should only\r | |
32 | * be used in Secure World to distinguished Secure to Non-Secure memory.\r | |
33 | */\r | |
34 | typedef enum {\r | |
35 | ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED = 0,\r | |
36 | ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_UNCACHED_UNBUFFERED,\r | |
37 | ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK,\r | |
38 | ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK,\r | |
829633e3 PL |
39 | \r |
40 | // On some platforms, memory mapped flash region is designed as not supporting\r | |
41 | // shareable attribute, so WRITE_BACK_NONSHAREABLE is added for such special\r | |
42 | // need.\r | |
43 | // Do NOT use below two attributes if you are not sure.\r | |
44 | ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK_NONSHAREABLE,\r | |
45 | ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK_NONSHAREABLE,\r | |
46 | \r | |
1e57a462 | 47 | ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH,\r |
48 | ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_THROUGH,\r | |
49 | ARM_MEMORY_REGION_ATTRIBUTE_DEVICE,\r | |
50 | ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_DEVICE\r | |
51 | } ARM_MEMORY_REGION_ATTRIBUTES;\r | |
52 | \r | |
429309e0 | 53 | #define IS_ARM_MEMORY_REGION_ATTRIBUTES_SECURE(attr) ((UINT32)(attr) & 1)\r |
1e57a462 | 54 | \r |
55 | typedef struct {\r | |
429309e0 MK |
56 | EFI_PHYSICAL_ADDRESS PhysicalBase;\r |
57 | EFI_VIRTUAL_ADDRESS VirtualBase;\r | |
58 | UINT64 Length;\r | |
59 | ARM_MEMORY_REGION_ATTRIBUTES Attributes;\r | |
1e57a462 | 60 | } ARM_MEMORY_REGION_DESCRIPTOR;\r |
61 | \r | |
429309e0 MK |
62 | typedef VOID (*CACHE_OPERATION)(\r |
63 | VOID\r | |
64 | );\r | |
65 | typedef VOID (*LINE_OPERATION)(\r | |
66 | UINTN\r | |
67 | );\r | |
1e57a462 | 68 | \r |
69 | //\r | |
70 | // ARM Processor Mode\r | |
71 | //\r | |
72 | typedef enum {\r | |
73 | ARM_PROCESSOR_MODE_USER = 0x10,\r | |
74 | ARM_PROCESSOR_MODE_FIQ = 0x11,\r | |
75 | ARM_PROCESSOR_MODE_IRQ = 0x12,\r | |
76 | ARM_PROCESSOR_MODE_SUPERVISOR = 0x13,\r | |
77 | ARM_PROCESSOR_MODE_ABORT = 0x17,\r | |
78 | ARM_PROCESSOR_MODE_HYP = 0x1A,\r | |
79 | ARM_PROCESSOR_MODE_UNDEFINED = 0x1B,\r | |
80 | ARM_PROCESSOR_MODE_SYSTEM = 0x1F,\r | |
81 | ARM_PROCESSOR_MODE_MASK = 0x1F\r | |
82 | } ARM_PROCESSOR_MODE;\r | |
83 | \r | |
84 | //\r | |
85 | // ARM Cpu IDs\r | |
86 | //\r | |
429309e0 MK |
87 | #define ARM_CPU_IMPLEMENTER_MASK (0xFFU << 24)\r |
88 | #define ARM_CPU_IMPLEMENTER_ARMLTD (0x41U << 24)\r | |
89 | #define ARM_CPU_IMPLEMENTER_DEC (0x44U << 24)\r | |
90 | #define ARM_CPU_IMPLEMENTER_MOT (0x4DU << 24)\r | |
91 | #define ARM_CPU_IMPLEMENTER_QUALCOMM (0x51U << 24)\r | |
92 | #define ARM_CPU_IMPLEMENTER_MARVELL (0x56U << 24)\r | |
93 | \r | |
94 | #define ARM_CPU_PRIMARY_PART_MASK (0xFFF << 4)\r | |
95 | #define ARM_CPU_PRIMARY_PART_CORTEXA5 (0xC05 << 4)\r | |
96 | #define ARM_CPU_PRIMARY_PART_CORTEXA7 (0xC07 << 4)\r | |
97 | #define ARM_CPU_PRIMARY_PART_CORTEXA8 (0xC08 << 4)\r | |
98 | #define ARM_CPU_PRIMARY_PART_CORTEXA9 (0xC09 << 4)\r | |
99 | #define ARM_CPU_PRIMARY_PART_CORTEXA15 (0xC0F << 4)\r | |
1e57a462 | 100 | \r |
101 | //\r | |
102 | // ARM MP Core IDs\r | |
103 | //\r | |
429309e0 MK |
104 | #define ARM_CORE_AFF0 0xFF\r |
105 | #define ARM_CORE_AFF1 (0xFF << 8)\r | |
106 | #define ARM_CORE_AFF2 (0xFF << 16)\r | |
107 | #define ARM_CORE_AFF3 (0xFFULL << 32)\r | |
108 | \r | |
109 | #define ARM_CORE_MASK ARM_CORE_AFF0\r | |
110 | #define ARM_CLUSTER_MASK ARM_CORE_AFF1\r | |
111 | #define GET_CORE_ID(MpId) ((MpId) & ARM_CORE_MASK)\r | |
112 | #define GET_CLUSTER_ID(MpId) (((MpId) & ARM_CLUSTER_MASK) >> 8)\r | |
113 | #define GET_MPID(ClusterId, CoreId) (((ClusterId) << 8) | (CoreId))\r | |
103fa647 RC |
114 | #define GET_MPIDR_AFF0(MpId) ((MpId) & ARM_CORE_AFF0)\r |
115 | #define GET_MPIDR_AFF1(MpId) (((MpId) & ARM_CORE_AFF1) >> 8)\r | |
116 | #define GET_MPIDR_AFF2(MpId) (((MpId) & ARM_CORE_AFF2) >> 16)\r | |
117 | #define GET_MPIDR_AFF3(MpId) (((MpId) & ARM_CORE_AFF3) >> 32)\r | |
429309e0 | 118 | #define PRIMARY_CORE_ID (PcdGet32(PcdArmPrimaryCore) & ARM_CORE_MASK)\r |
1e57a462 | 119 | \r |
a63914d3 RC |
120 | /** Reads the CCSIDR register for the specified cache.\r |
121 | \r | |
122 | @param CSSELR The CSSELR cache selection register value.\r | |
123 | \r | |
124 | @return The contents of the CCSIDR_EL1 register for the specified cache, when in AARCH64 mode.\r | |
125 | Returns the contents of the CCSIDR register in AARCH32 mode.\r | |
126 | **/\r | |
127 | UINTN\r | |
128 | ReadCCSIDR (\r | |
429309e0 | 129 | IN UINT32 CSSELR\r |
a63914d3 RC |
130 | );\r |
131 | \r | |
132 | /** Reads the CCSIDR2 for the specified cache.\r | |
133 | \r | |
134 | @param CSSELR The CSSELR cache selection register value\r | |
135 | \r | |
136 | @return The contents of the CCSIDR2 register for the specified cache.\r | |
137 | **/\r | |
138 | UINT32\r | |
139 | ReadCCSIDR2 (\r | |
429309e0 | 140 | IN UINT32 CSSELR\r |
a63914d3 RC |
141 | );\r |
142 | \r | |
143 | /** Reads the Cache Level ID (CLIDR) register.\r | |
144 | \r | |
145 | @return The contents of the CLIDR_EL1 register.\r | |
146 | **/\r | |
147 | UINT32\r | |
148 | ReadCLIDR (\r | |
149 | VOID\r | |
150 | );\r | |
4f92cfa4 | 151 | \r |
1e57a462 | 152 | UINTN\r |
153 | EFIAPI\r | |
154 | ArmDataCacheLineLength (\r | |
155 | VOID\r | |
156 | );\r | |
3402aac7 | 157 | \r |
1e57a462 | 158 | UINTN\r |
159 | EFIAPI\r | |
160 | ArmInstructionCacheLineLength (\r | |
161 | VOID\r | |
162 | );\r | |
168d7245 | 163 | \r |
c653fc2a AB |
164 | UINTN\r |
165 | EFIAPI\r | |
166 | ArmCacheWritebackGranule (\r | |
167 | VOID\r | |
168 | );\r | |
169 | \r | |
168d7245 OM |
170 | UINTN\r |
171 | EFIAPI\r | |
172 | ArmIsArchTimerImplemented (\r | |
173 | VOID\r | |
174 | );\r | |
175 | \r | |
64751727 | 176 | UINTN\r |
1e57a462 | 177 | EFIAPI\r |
64751727 | 178 | ArmCacheInfo (\r |
1e57a462 | 179 | VOID\r |
180 | );\r | |
181 | \r | |
182 | BOOLEAN\r | |
183 | EFIAPI\r | |
184 | ArmIsMpCore (\r | |
185 | VOID\r | |
186 | );\r | |
187 | \r | |
188 | VOID\r | |
189 | EFIAPI\r | |
190 | ArmInvalidateDataCache (\r | |
191 | VOID\r | |
192 | );\r | |
193 | \r | |
1e57a462 | 194 | VOID\r |
195 | EFIAPI\r | |
196 | ArmCleanInvalidateDataCache (\r | |
197 | VOID\r | |
198 | );\r | |
199 | \r | |
200 | VOID\r | |
201 | EFIAPI\r | |
202 | ArmCleanDataCache (\r | |
203 | VOID\r | |
204 | );\r | |
205 | \r | |
1e57a462 | 206 | VOID\r |
207 | EFIAPI\r | |
208 | ArmInvalidateInstructionCache (\r | |
209 | VOID\r | |
210 | );\r | |
211 | \r | |
212 | VOID\r | |
213 | EFIAPI\r | |
214 | ArmInvalidateDataCacheEntryByMVA (\r | |
429309e0 | 215 | IN UINTN Address\r |
1e57a462 | 216 | );\r |
217 | \r | |
218 | VOID\r | |
219 | EFIAPI\r | |
cf580da1 | 220 | ArmCleanDataCacheEntryToPoUByMVA (\r |
429309e0 | 221 | IN UINTN Address\r |
1e57a462 | 222 | );\r |
223 | \r | |
b7de7e3c EC |
224 | VOID\r |
225 | EFIAPI\r | |
cf580da1 | 226 | ArmInvalidateInstructionCacheEntryToPoUByMVA (\r |
429309e0 | 227 | IN UINTN Address\r |
cf580da1 AB |
228 | );\r |
229 | \r | |
230 | VOID\r | |
231 | EFIAPI\r | |
232 | ArmCleanDataCacheEntryByMVA (\r | |
429309e0 MK |
233 | IN UINTN Address\r |
234 | );\r | |
b7de7e3c | 235 | \r |
1e57a462 | 236 | VOID\r |
237 | EFIAPI\r | |
238 | ArmCleanInvalidateDataCacheEntryByMVA (\r | |
429309e0 | 239 | IN UINTN Address\r |
1e57a462 | 240 | );\r |
241 | \r | |
242 | VOID\r | |
243 | EFIAPI\r | |
244 | ArmEnableDataCache (\r | |
245 | VOID\r | |
246 | );\r | |
247 | \r | |
248 | VOID\r | |
249 | EFIAPI\r | |
250 | ArmDisableDataCache (\r | |
251 | VOID\r | |
252 | );\r | |
253 | \r | |
254 | VOID\r | |
255 | EFIAPI\r | |
256 | ArmEnableInstructionCache (\r | |
257 | VOID\r | |
258 | );\r | |
259 | \r | |
260 | VOID\r | |
261 | EFIAPI\r | |
262 | ArmDisableInstructionCache (\r | |
263 | VOID\r | |
264 | );\r | |
3402aac7 | 265 | \r |
1e57a462 | 266 | VOID\r |
267 | EFIAPI\r | |
268 | ArmEnableMmu (\r | |
269 | VOID\r | |
270 | );\r | |
271 | \r | |
272 | VOID\r | |
273 | EFIAPI\r | |
274 | ArmDisableMmu (\r | |
275 | VOID\r | |
276 | );\r | |
277 | \r | |
0ff0e414 OM |
278 | VOID\r |
279 | EFIAPI\r | |
280 | ArmEnableCachesAndMmu (\r | |
281 | VOID\r | |
282 | );\r | |
283 | \r | |
1e57a462 | 284 | VOID\r |
285 | EFIAPI\r | |
286 | ArmDisableCachesAndMmu (\r | |
287 | VOID\r | |
288 | );\r | |
289 | \r | |
1e57a462 | 290 | VOID\r |
291 | EFIAPI\r | |
292 | ArmEnableInterrupts (\r | |
293 | VOID\r | |
294 | );\r | |
295 | \r | |
296 | UINTN\r | |
297 | EFIAPI\r | |
298 | ArmDisableInterrupts (\r | |
299 | VOID\r | |
300 | );\r | |
47585ed5 | 301 | \r |
1e57a462 | 302 | BOOLEAN\r |
303 | EFIAPI\r | |
304 | ArmGetInterruptState (\r | |
305 | VOID\r | |
306 | );\r | |
307 | \r | |
0ff0e414 OM |
308 | VOID\r |
309 | EFIAPI\r | |
310 | ArmEnableAsynchronousAbort (\r | |
311 | VOID\r | |
312 | );\r | |
313 | \r | |
47585ed5 | 314 | UINTN\r |
315 | EFIAPI\r | |
0ff0e414 | 316 | ArmDisableAsynchronousAbort (\r |
47585ed5 | 317 | VOID\r |
318 | );\r | |
319 | \r | |
320 | VOID\r | |
321 | EFIAPI\r | |
322 | ArmEnableIrq (\r | |
323 | VOID\r | |
324 | );\r | |
325 | \r | |
0ff0e414 OM |
326 | UINTN\r |
327 | EFIAPI\r | |
328 | ArmDisableIrq (\r | |
329 | VOID\r | |
330 | );\r | |
331 | \r | |
1e57a462 | 332 | VOID\r |
333 | EFIAPI\r | |
334 | ArmEnableFiq (\r | |
335 | VOID\r | |
336 | );\r | |
337 | \r | |
338 | UINTN\r | |
339 | EFIAPI\r | |
340 | ArmDisableFiq (\r | |
341 | VOID\r | |
342 | );\r | |
3402aac7 | 343 | \r |
1e57a462 | 344 | BOOLEAN\r |
345 | EFIAPI\r | |
346 | ArmGetFiqState (\r | |
347 | VOID\r | |
348 | );\r | |
349 | \r | |
8dd618d2 OM |
350 | /**\r |
351 | * Invalidate Data and Instruction TLBs\r | |
352 | */\r | |
1e57a462 | 353 | VOID\r |
354 | EFIAPI\r | |
355 | ArmInvalidateTlb (\r | |
356 | VOID\r | |
357 | );\r | |
3402aac7 | 358 | \r |
1e57a462 | 359 | VOID\r |
360 | EFIAPI\r | |
361 | ArmUpdateTranslationTableEntry (\r | |
429309e0 MK |
362 | IN VOID *TranslationTableEntry,\r |
363 | IN VOID *Mva\r | |
1e57a462 | 364 | );\r |
3402aac7 | 365 | \r |
1e57a462 | 366 | VOID\r |
367 | EFIAPI\r | |
368 | ArmSetDomainAccessControl (\r | |
369 | IN UINT32 Domain\r | |
370 | );\r | |
371 | \r | |
372 | VOID\r | |
373 | EFIAPI\r | |
374 | ArmSetTTBR0 (\r | |
375 | IN VOID *TranslationTableBase\r | |
376 | );\r | |
377 | \r | |
ff1f27c0 EL |
378 | VOID\r |
379 | EFIAPI\r | |
380 | ArmSetTTBCR (\r | |
429309e0 | 381 | IN UINT32 Bits\r |
ff1f27c0 EL |
382 | );\r |
383 | \r | |
1e57a462 | 384 | VOID *\r |
385 | EFIAPI\r | |
386 | ArmGetTTBR0BaseAddress (\r | |
387 | VOID\r | |
388 | );\r | |
389 | \r | |
1e57a462 | 390 | BOOLEAN\r |
391 | EFIAPI\r | |
392 | ArmMmuEnabled (\r | |
393 | VOID\r | |
394 | );\r | |
3402aac7 | 395 | \r |
1e57a462 | 396 | VOID\r |
397 | EFIAPI\r | |
398 | ArmEnableBranchPrediction (\r | |
399 | VOID\r | |
400 | );\r | |
401 | \r | |
402 | VOID\r | |
403 | EFIAPI\r | |
404 | ArmDisableBranchPrediction (\r | |
405 | VOID\r | |
406 | );\r | |
407 | \r | |
408 | VOID\r | |
409 | EFIAPI\r | |
410 | ArmSetLowVectors (\r | |
411 | VOID\r | |
412 | );\r | |
413 | \r | |
414 | VOID\r | |
415 | EFIAPI\r | |
416 | ArmSetHighVectors (\r | |
417 | VOID\r | |
418 | );\r | |
419 | \r | |
420 | VOID\r | |
421 | EFIAPI\r | |
422 | ArmDataMemoryBarrier (\r | |
423 | VOID\r | |
424 | );\r | |
3402aac7 | 425 | \r |
1e57a462 | 426 | VOID\r |
427 | EFIAPI\r | |
cf93a378 | 428 | ArmDataSynchronizationBarrier (\r |
1e57a462 | 429 | VOID\r |
430 | );\r | |
3402aac7 | 431 | \r |
1e57a462 | 432 | VOID\r |
433 | EFIAPI\r | |
434 | ArmInstructionSynchronizationBarrier (\r | |
435 | VOID\r | |
436 | );\r | |
437 | \r | |
438 | VOID\r | |
439 | EFIAPI\r | |
440 | ArmWriteVBar (\r | |
429309e0 | 441 | IN UINTN VectorBase\r |
1e57a462 | 442 | );\r |
443 | \r | |
4e57d6d7 | 444 | UINTN\r |
1e57a462 | 445 | EFIAPI\r |
446 | ArmReadVBar (\r | |
447 | VOID\r | |
448 | );\r | |
449 | \r | |
450 | VOID\r | |
451 | EFIAPI\r | |
452 | ArmWriteAuxCr (\r | |
429309e0 | 453 | IN UINT32 Bit\r |
1e57a462 | 454 | );\r |
455 | \r | |
456 | UINT32\r | |
457 | EFIAPI\r | |
458 | ArmReadAuxCr (\r | |
459 | VOID\r | |
460 | );\r | |
461 | \r | |
462 | VOID\r | |
463 | EFIAPI\r | |
464 | ArmSetAuxCrBit (\r | |
429309e0 | 465 | IN UINT32 Bits\r |
1e57a462 | 466 | );\r |
467 | \r | |
468 | VOID\r | |
469 | EFIAPI\r | |
470 | ArmUnsetAuxCrBit (\r | |
429309e0 | 471 | IN UINT32 Bits\r |
1e57a462 | 472 | );\r |
473 | \r | |
474 | VOID\r | |
475 | EFIAPI\r | |
476 | ArmCallSEV (\r | |
477 | VOID\r | |
478 | );\r | |
479 | \r | |
480 | VOID\r | |
481 | EFIAPI\r | |
482 | ArmCallWFE (\r | |
483 | VOID\r | |
484 | );\r | |
485 | \r | |
486 | VOID\r | |
487 | EFIAPI\r | |
488 | ArmCallWFI (\r | |
25402f5d | 489 | \r |
1e57a462 | 490 | VOID\r |
491 | );\r | |
492 | \r | |
493 | UINTN\r | |
494 | EFIAPI\r | |
495 | ArmReadMpidr (\r | |
496 | VOID\r | |
497 | );\r | |
498 | \r | |
9401d6f4 OM |
499 | UINTN\r |
500 | EFIAPI\r | |
501 | ArmReadMidr (\r | |
502 | VOID\r | |
503 | );\r | |
504 | \r | |
1e57a462 | 505 | UINT32\r |
506 | EFIAPI\r | |
507 | ArmReadCpacr (\r | |
508 | VOID\r | |
509 | );\r | |
510 | \r | |
511 | VOID\r | |
512 | EFIAPI\r | |
513 | ArmWriteCpacr (\r | |
429309e0 | 514 | IN UINT32 Access\r |
1e57a462 | 515 | );\r |
516 | \r | |
517 | VOID\r | |
518 | EFIAPI\r | |
519 | ArmEnableVFP (\r | |
520 | VOID\r | |
521 | );\r | |
522 | \r | |
46d4d75c OM |
523 | /**\r |
524 | Get the Secure Configuration Register value\r | |
525 | \r | |
526 | @return Value read from the Secure Configuration Register\r | |
527 | \r | |
528 | **/\r | |
1e57a462 | 529 | UINT32\r |
530 | EFIAPI\r | |
531 | ArmReadScr (\r | |
532 | VOID\r | |
533 | );\r | |
534 | \r | |
46d4d75c OM |
535 | /**\r |
536 | Set the Secure Configuration Register\r | |
537 | \r | |
538 | @param Value Value to write to the Secure Configuration Register\r | |
539 | \r | |
540 | **/\r | |
1e57a462 | 541 | VOID\r |
542 | EFIAPI\r | |
543 | ArmWriteScr (\r | |
429309e0 | 544 | IN UINT32 Value\r |
1e57a462 | 545 | );\r |
546 | \r | |
547 | UINT32\r | |
548 | EFIAPI\r | |
549 | ArmReadMVBar (\r | |
550 | VOID\r | |
551 | );\r | |
552 | \r | |
553 | VOID\r | |
554 | EFIAPI\r | |
555 | ArmWriteMVBar (\r | |
429309e0 | 556 | IN UINT32 VectorMonitorBase\r |
1e57a462 | 557 | );\r |
558 | \r | |
559 | UINT32\r | |
560 | EFIAPI\r | |
561 | ArmReadSctlr (\r | |
562 | VOID\r | |
563 | );\r | |
564 | \r | |
1e1d1697 MZ |
565 | VOID\r |
566 | EFIAPI\r | |
567 | ArmWriteSctlr (\r | |
429309e0 | 568 | IN UINT32 Value\r |
1e1d1697 MZ |
569 | );\r |
570 | \r | |
5ea2c2d3 | 571 | UINTN\r |
572 | EFIAPI\r | |
573 | ArmReadHVBar (\r | |
574 | VOID\r | |
575 | );\r | |
576 | \r | |
577 | VOID\r | |
578 | EFIAPI\r | |
579 | ArmWriteHVBar (\r | |
429309e0 | 580 | IN UINTN HypModeVectorBase\r |
5ea2c2d3 | 581 | );\r |
582 | \r | |
52d44f77 OM |
583 | //\r |
584 | // Helper functions for accessing CPU ACTLR\r | |
585 | //\r | |
586 | \r | |
587 | UINTN\r | |
588 | EFIAPI\r | |
589 | ArmReadCpuActlr (\r | |
590 | VOID\r | |
591 | );\r | |
592 | \r | |
593 | VOID\r | |
594 | EFIAPI\r | |
595 | ArmWriteCpuActlr (\r | |
429309e0 | 596 | IN UINTN Val\r |
52d44f77 OM |
597 | );\r |
598 | \r | |
599 | VOID\r | |
600 | EFIAPI\r | |
601 | ArmSetCpuActlrBit (\r | |
429309e0 | 602 | IN UINTN Bits\r |
52d44f77 OM |
603 | );\r |
604 | \r | |
605 | VOID\r | |
606 | EFIAPI\r | |
607 | ArmUnsetCpuActlrBit (\r | |
429309e0 | 608 | IN UINTN Bits\r |
52d44f77 OM |
609 | );\r |
610 | \r | |
734bd6cc AB |
611 | //\r |
612 | // Accessors for the architected generic timer registers\r | |
613 | //\r | |
614 | \r | |
429309e0 MK |
615 | #define ARM_ARCH_TIMER_ENABLE (1 << 0)\r |
616 | #define ARM_ARCH_TIMER_IMASK (1 << 1)\r | |
617 | #define ARM_ARCH_TIMER_ISTATUS (1 << 2)\r | |
734bd6cc AB |
618 | \r |
619 | UINTN\r | |
620 | EFIAPI\r | |
621 | ArmReadCntFrq (\r | |
622 | VOID\r | |
623 | );\r | |
624 | \r | |
625 | VOID\r | |
626 | EFIAPI\r | |
627 | ArmWriteCntFrq (\r | |
429309e0 | 628 | UINTN FreqInHz\r |
734bd6cc AB |
629 | );\r |
630 | \r | |
631 | UINT64\r | |
632 | EFIAPI\r | |
633 | ArmReadCntPct (\r | |
634 | VOID\r | |
635 | );\r | |
636 | \r | |
637 | UINTN\r | |
638 | EFIAPI\r | |
639 | ArmReadCntkCtl (\r | |
640 | VOID\r | |
641 | );\r | |
642 | \r | |
643 | VOID\r | |
644 | EFIAPI\r | |
645 | ArmWriteCntkCtl (\r | |
429309e0 | 646 | UINTN Val\r |
734bd6cc AB |
647 | );\r |
648 | \r | |
649 | UINTN\r | |
650 | EFIAPI\r | |
651 | ArmReadCntpTval (\r | |
652 | VOID\r | |
653 | );\r | |
654 | \r | |
655 | VOID\r | |
656 | EFIAPI\r | |
657 | ArmWriteCntpTval (\r | |
429309e0 | 658 | UINTN Val\r |
734bd6cc AB |
659 | );\r |
660 | \r | |
661 | UINTN\r | |
662 | EFIAPI\r | |
663 | ArmReadCntpCtl (\r | |
664 | VOID\r | |
665 | );\r | |
666 | \r | |
667 | VOID\r | |
668 | EFIAPI\r | |
669 | ArmWriteCntpCtl (\r | |
429309e0 | 670 | UINTN Val\r |
734bd6cc AB |
671 | );\r |
672 | \r | |
673 | UINTN\r | |
674 | EFIAPI\r | |
675 | ArmReadCntvTval (\r | |
676 | VOID\r | |
677 | );\r | |
678 | \r | |
679 | VOID\r | |
680 | EFIAPI\r | |
681 | ArmWriteCntvTval (\r | |
429309e0 | 682 | UINTN Val\r |
734bd6cc AB |
683 | );\r |
684 | \r | |
685 | UINTN\r | |
686 | EFIAPI\r | |
687 | ArmReadCntvCtl (\r | |
688 | VOID\r | |
689 | );\r | |
690 | \r | |
691 | VOID\r | |
692 | EFIAPI\r | |
693 | ArmWriteCntvCtl (\r | |
429309e0 | 694 | UINTN Val\r |
734bd6cc AB |
695 | );\r |
696 | \r | |
697 | UINT64\r | |
698 | EFIAPI\r | |
699 | ArmReadCntvCt (\r | |
700 | VOID\r | |
701 | );\r | |
702 | \r | |
703 | UINT64\r | |
704 | EFIAPI\r | |
705 | ArmReadCntpCval (\r | |
706 | VOID\r | |
707 | );\r | |
708 | \r | |
709 | VOID\r | |
710 | EFIAPI\r | |
711 | ArmWriteCntpCval (\r | |
429309e0 | 712 | UINT64 Val\r |
734bd6cc AB |
713 | );\r |
714 | \r | |
715 | UINT64\r | |
716 | EFIAPI\r | |
717 | ArmReadCntvCval (\r | |
718 | VOID\r | |
719 | );\r | |
720 | \r | |
721 | VOID\r | |
722 | EFIAPI\r | |
723 | ArmWriteCntvCval (\r | |
429309e0 | 724 | UINT64 Val\r |
734bd6cc AB |
725 | );\r |
726 | \r | |
727 | UINT64\r | |
728 | EFIAPI\r | |
729 | ArmReadCntvOff (\r | |
730 | VOID\r | |
731 | );\r | |
732 | \r | |
733 | VOID\r | |
734 | EFIAPI\r | |
735 | ArmWriteCntvOff (\r | |
429309e0 | 736 | UINT64 Val\r |
734bd6cc AB |
737 | );\r |
738 | \r | |
95d04ebc AB |
739 | UINTN\r |
740 | EFIAPI\r | |
741 | ArmGetPhysicalAddressBits (\r | |
742 | VOID\r | |
743 | );\r | |
744 | \r | |
5cc25cff LL |
745 | ///\r |
746 | /// ID Register Helper functions\r | |
747 | ///\r | |
748 | \r | |
749 | /**\r | |
750 | Check whether the CPU supports the GIC system register interface (any version)\r | |
751 | \r | |
752 | @return Whether GIC System Register Interface is supported\r | |
753 | \r | |
754 | **/\r | |
755 | BOOLEAN\r | |
756 | EFIAPI\r | |
757 | ArmHasGicSystemRegisters (\r | |
758 | VOID\r | |
759 | );\r | |
760 | \r | |
6e131aff RC |
761 | /** Checks if CCIDX is implemented.\r |
762 | \r | |
763 | @retval TRUE CCIDX is implemented.\r | |
764 | @retval FALSE CCIDX is not implemented.\r | |
765 | **/\r | |
766 | BOOLEAN\r | |
767 | EFIAPI\r | |
768 | ArmHasCcidx (\r | |
769 | VOID\r | |
770 | );\r | |
771 | \r | |
740b870d LL |
772 | #ifdef MDE_CPU_ARM\r |
773 | ///\r | |
774 | /// AArch32-only ID Register Helper functions\r | |
775 | ///\r | |
429309e0 | 776 | \r |
740b870d LL |
777 | /**\r |
778 | Check whether the CPU supports the Security extensions\r | |
779 | \r | |
780 | @return Whether the Security extensions are implemented\r | |
781 | \r | |
782 | **/\r | |
783 | BOOLEAN\r | |
784 | EFIAPI\r | |
785 | ArmHasSecurityExtensions (\r | |
786 | VOID\r | |
787 | );\r | |
429309e0 | 788 | \r |
740b870d LL |
789 | #endif // MDE_CPU_ARM\r |
790 | \r | |
cc15a619 | 791 | #endif // ARM_LIB_H_\r |