[mirror_edk2.git] / ArmPkg / Include / Library / ArmLib.h

/** @file\r
\r
  Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
  Copyright (c) 2011 - 2016, ARM Ltd. All rights reserved.<BR>\r
\r
  SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
**/\r
\r
#ifndef __ARM_LIB__\r
#define __ARM_LIB__\r
\r
#include <Uefi/UefiBaseType.h>\r
\r
#ifdef MDE_CPU_ARM\r
  #include <Chipset/ArmV7.h>\r
#elif defined(MDE_CPU_AARCH64)\r
  #include <Chipset/AArch64.h>\r
#else\r
 #error "Unknown chipset."\r
#endif\r
\r
#define EFI_MEMORY_CACHETYPE_MASK   (EFI_MEMORY_UC | EFI_MEMORY_WC | \\r
                                     EFI_MEMORY_WT | EFI_MEMORY_WB | \\r
                                     EFI_MEMORY_UCE)\r
\r
/**\r
 * The UEFI firmware must not use the ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_* attributes.\r
 *\r
 * The Non Secure memory attribute (ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_*) should only\r
 * be used in Secure World to distinguished Secure to Non-Secure memory.\r
 */\r
typedef enum {\r
  ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED = 0,\r
  ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_UNCACHED_UNBUFFERED,\r
  ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK,\r
  ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK,\r
\r
  // On some platforms, memory mapped flash region is designed as not supporting\r
  // shareable attribute, so WRITE_BACK_NONSHAREABLE is added for such special\r
  // need.\r
  // Do NOT use below two attributes if you are not sure.\r
  ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK_NONSHAREABLE,\r
  ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK_NONSHAREABLE,\r
\r
  ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH,\r
  ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_THROUGH,\r
  ARM_MEMORY_REGION_ATTRIBUTE_DEVICE,\r
  ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_DEVICE\r
} ARM_MEMORY_REGION_ATTRIBUTES;\r
\r
#define IS_ARM_MEMORY_REGION_ATTRIBUTES_SECURE(attr) ((UINT32)(attr) & 1)\r
\r
typedef struct {\r
  EFI_PHYSICAL_ADDRESS          PhysicalBase;\r
  EFI_VIRTUAL_ADDRESS           VirtualBase;\r
  UINT64                        Length;\r
  ARM_MEMORY_REGION_ATTRIBUTES  Attributes;\r
} ARM_MEMORY_REGION_DESCRIPTOR;\r
\r
typedef VOID (*CACHE_OPERATION)(VOID);\r
typedef VOID (*LINE_OPERATION)(UINTN);\r
\r
//\r
// ARM Processor Mode\r
//\r
typedef enum {\r
  ARM_PROCESSOR_MODE_USER       = 0x10,\r
  ARM_PROCESSOR_MODE_FIQ        = 0x11,\r
  ARM_PROCESSOR_MODE_IRQ        = 0x12,\r
  ARM_PROCESSOR_MODE_SUPERVISOR = 0x13,\r
  ARM_PROCESSOR_MODE_ABORT      = 0x17,\r
  ARM_PROCESSOR_MODE_HYP        = 0x1A,\r
  ARM_PROCESSOR_MODE_UNDEFINED  = 0x1B,\r
  ARM_PROCESSOR_MODE_SYSTEM     = 0x1F,\r
  ARM_PROCESSOR_MODE_MASK       = 0x1F\r
} ARM_PROCESSOR_MODE;\r
\r
//\r
// ARM Cpu IDs\r
//\r
#define ARM_CPU_IMPLEMENTER_MASK          (0xFFU << 24)\r
#define ARM_CPU_IMPLEMENTER_ARMLTD        (0x41U << 24)\r
#define ARM_CPU_IMPLEMENTER_DEC           (0x44U << 24)\r
#define ARM_CPU_IMPLEMENTER_MOT           (0x4DU << 24)\r
#define ARM_CPU_IMPLEMENTER_QUALCOMM      (0x51U << 24)\r
#define ARM_CPU_IMPLEMENTER_MARVELL       (0x56U << 24)\r
\r
#define ARM_CPU_PRIMARY_PART_MASK         (0xFFF << 4)\r
#define ARM_CPU_PRIMARY_PART_CORTEXA5     (0xC05 << 4)\r
#define ARM_CPU_PRIMARY_PART_CORTEXA7     (0xC07 << 4)\r
#define ARM_CPU_PRIMARY_PART_CORTEXA8     (0xC08 << 4)\r
#define ARM_CPU_PRIMARY_PART_CORTEXA9     (0xC09 << 4)\r
#define ARM_CPU_PRIMARY_PART_CORTEXA15    (0xC0F << 4)\r
\r
//\r
// ARM MP Core IDs\r
//\r
#define ARM_CORE_AFF0         0xFF\r
#define ARM_CORE_AFF1         (0xFF << 8)\r
#define ARM_CORE_AFF2         (0xFF << 16)\r
#define ARM_CORE_AFF3         (0xFFULL << 32)\r
\r
#define ARM_CORE_MASK         ARM_CORE_AFF0\r
#define ARM_CLUSTER_MASK      ARM_CORE_AFF1\r
#define GET_CORE_ID(MpId)     ((MpId) & ARM_CORE_MASK)\r
#define GET_CLUSTER_ID(MpId)  (((MpId) & ARM_CLUSTER_MASK) >> 8)\r
#define GET_MPID(ClusterId, CoreId)   (((ClusterId) << 8) | (CoreId))\r
#define PRIMARY_CORE_ID       (PcdGet32(PcdArmPrimaryCore) & ARM_CORE_MASK)\r
\r
UINTN\r
EFIAPI\r
ArmDataCacheLineLength (\r
  VOID\r
  );\r
\r
UINTN\r
EFIAPI\r
ArmInstructionCacheLineLength (\r
  VOID\r
  );\r
\r
UINTN\r
EFIAPI\r
ArmCacheWritebackGranule (\r
  VOID\r
  );\r
\r
UINTN\r
EFIAPI\r
ArmIsArchTimerImplemented (\r
  VOID\r
  );\r
\r
UINTN\r
EFIAPI\r
ArmReadIdPfr0 (\r
  VOID\r
  );\r
\r
UINTN\r
EFIAPI\r
ArmReadIdPfr1 (\r
  VOID\r
  );\r
\r
UINTN\r
EFIAPI\r
ArmCacheInfo (\r
  VOID\r
  );\r
\r
BOOLEAN\r
EFIAPI\r
ArmIsMpCore (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmInvalidateDataCache (\r
  VOID\r
  );\r
\r
\r
VOID\r
EFIAPI\r
ArmCleanInvalidateDataCache (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmCleanDataCache (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmInvalidateInstructionCache (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmInvalidateDataCacheEntryByMVA (\r
  IN  UINTN   Address\r
  );\r
\r
VOID\r
EFIAPI\r
ArmCleanDataCacheEntryToPoUByMVA (\r
  IN  UINTN   Address\r
  );\r
\r
VOID\r
EFIAPI\r
ArmInvalidateInstructionCacheEntryToPoUByMVA (\r
  IN  UINTN   Address\r
  );\r
\r
VOID\r
EFIAPI\r
ArmCleanDataCacheEntryByMVA (\r
IN  UINTN   Address\r
);\r
\r
VOID\r
EFIAPI\r
ArmCleanInvalidateDataCacheEntryByMVA (\r
  IN  UINTN   Address\r
  );\r
\r
VOID\r
EFIAPI\r
ArmInvalidateDataCacheEntryBySetWay (\r
  IN  UINTN  SetWayFormat\r
  );\r
\r
VOID\r
EFIAPI\r
ArmCleanDataCacheEntryBySetWay (\r
  IN  UINTN  SetWayFormat\r
  );\r
\r
VOID\r
EFIAPI\r
ArmCleanInvalidateDataCacheEntryBySetWay (\r
  IN  UINTN   SetWayFormat\r
  );\r
\r
VOID\r
EFIAPI\r
ArmEnableDataCache (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmDisableDataCache (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmEnableInstructionCache (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmDisableInstructionCache (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmEnableMmu (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmDisableMmu (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmEnableCachesAndMmu (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmDisableCachesAndMmu (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmEnableInterrupts (\r
  VOID\r
  );\r
\r
UINTN\r
EFIAPI\r
ArmDisableInterrupts (\r
  VOID\r
  );\r
\r
BOOLEAN\r
EFIAPI\r
ArmGetInterruptState (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmEnableAsynchronousAbort (\r
  VOID\r
  );\r
\r
UINTN\r
EFIAPI\r
ArmDisableAsynchronousAbort (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmEnableIrq (\r
  VOID\r
  );\r
\r
UINTN\r
EFIAPI\r
ArmDisableIrq (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmEnableFiq (\r
  VOID\r
  );\r
\r
UINTN\r
EFIAPI\r
ArmDisableFiq (\r
  VOID\r
  );\r
\r
BOOLEAN\r
EFIAPI\r
ArmGetFiqState (\r
  VOID\r
  );\r
\r
/**\r
 * Invalidate Data and Instruction TLBs\r
 */\r
VOID\r
EFIAPI\r
ArmInvalidateTlb (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmUpdateTranslationTableEntry (\r
  IN  VOID     *TranslationTableEntry,\r
  IN  VOID     *Mva\r
  );\r
\r
VOID\r
EFIAPI\r
ArmSetDomainAccessControl (\r
  IN  UINT32  Domain\r
  );\r
\r
VOID\r
EFIAPI\r
ArmSetTTBR0 (\r
  IN  VOID  *TranslationTableBase\r
  );\r
\r
VOID\r
EFIAPI\r
ArmSetTTBCR (\r
  IN  UINT32 Bits\r
  );\r
\r
VOID *\r
EFIAPI\r
ArmGetTTBR0BaseAddress (\r
  VOID\r
  );\r
\r
BOOLEAN\r
EFIAPI\r
ArmMmuEnabled (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmEnableBranchPrediction (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmDisableBranchPrediction (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmSetLowVectors (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmSetHighVectors (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmDataMemoryBarrier (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmDataSynchronizationBarrier (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmInstructionSynchronizationBarrier (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmWriteVBar (\r
  IN  UINTN   VectorBase\r
  );\r
\r
UINTN\r
EFIAPI\r
ArmReadVBar (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmWriteAuxCr (\r
  IN  UINT32    Bit\r
  );\r
\r
UINT32\r
EFIAPI\r
ArmReadAuxCr (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmSetAuxCrBit (\r
  IN  UINT32    Bits\r
  );\r
\r
VOID\r
EFIAPI\r
ArmUnsetAuxCrBit (\r
  IN  UINT32    Bits\r
  );\r
\r
VOID\r
EFIAPI\r
ArmCallSEV (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmCallWFE (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmCallWFI (\r
\r
  VOID\r
  );\r
\r
UINTN\r
EFIAPI\r
ArmReadMpidr (\r
  VOID\r
  );\r
\r
UINTN\r
EFIAPI\r
ArmReadMidr (\r
  VOID\r
  );\r
\r
UINT32\r
EFIAPI\r
ArmReadCpacr (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmWriteCpacr (\r
  IN  UINT32   Access\r
  );\r
\r
VOID\r
EFIAPI\r
ArmEnableVFP (\r
  VOID\r
  );\r
\r
/**\r
  Get the Secure Configuration Register value\r
\r
  @return   Value read from the Secure Configuration Register\r
\r
**/\r
UINT32\r
EFIAPI\r
ArmReadScr (\r
  VOID\r
  );\r
\r
/**\r
  Set the Secure Configuration Register\r
\r
  @param Value   Value to write to the Secure Configuration Register\r
\r
**/\r
VOID\r
EFIAPI\r
ArmWriteScr (\r
  IN  UINT32   Value\r
  );\r
\r
UINT32\r
EFIAPI\r
ArmReadMVBar (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmWriteMVBar (\r
  IN  UINT32   VectorMonitorBase\r
  );\r
\r
UINT32\r
EFIAPI\r
ArmReadSctlr (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmWriteSctlr (\r
  IN  UINT32   Value\r
  );\r
\r
UINTN\r
EFIAPI\r
ArmReadHVBar (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmWriteHVBar (\r
  IN  UINTN   HypModeVectorBase\r
  );\r
\r
\r
//\r
// Helper functions for accessing CPU ACTLR\r
//\r
\r
UINTN\r
EFIAPI\r
ArmReadCpuActlr (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmWriteCpuActlr (\r
  IN  UINTN Val\r
  );\r
\r
VOID\r
EFIAPI\r
ArmSetCpuActlrBit (\r
  IN  UINTN    Bits\r
  );\r
\r
VOID\r
EFIAPI\r
ArmUnsetCpuActlrBit (\r
  IN  UINTN    Bits\r
  );\r
\r
//\r
// Accessors for the architected generic timer registers\r
//\r
\r
#define ARM_ARCH_TIMER_ENABLE           (1 << 0)\r
#define ARM_ARCH_TIMER_IMASK            (1 << 1)\r
#define ARM_ARCH_TIMER_ISTATUS          (1 << 2)\r
\r
UINTN\r
EFIAPI\r
ArmReadCntFrq (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmWriteCntFrq (\r
  UINTN   FreqInHz\r
  );\r
\r
UINT64\r
EFIAPI\r
ArmReadCntPct (\r
  VOID\r
  );\r
\r
UINTN\r
EFIAPI\r
ArmReadCntkCtl (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmWriteCntkCtl (\r
  UINTN   Val\r
  );\r
\r
UINTN\r
EFIAPI\r
ArmReadCntpTval (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmWriteCntpTval (\r
  UINTN   Val\r
  );\r
\r
UINTN\r
EFIAPI\r
ArmReadCntpCtl (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmWriteCntpCtl (\r
  UINTN   Val\r
  );\r
\r
UINTN\r
EFIAPI\r
ArmReadCntvTval (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmWriteCntvTval (\r
  UINTN   Val\r
  );\r
\r
UINTN\r
EFIAPI\r
ArmReadCntvCtl (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmWriteCntvCtl (\r
  UINTN   Val\r
  );\r
\r
UINT64\r
EFIAPI\r
ArmReadCntvCt (\r
  VOID\r
  );\r
\r
UINT64\r
EFIAPI\r
ArmReadCntpCval (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmWriteCntpCval (\r
  UINT64   Val\r
  );\r
\r
UINT64\r
EFIAPI\r
ArmReadCntvCval (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmWriteCntvCval (\r
  UINT64   Val\r
  );\r
\r
UINT64\r
EFIAPI\r
ArmReadCntvOff (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmWriteCntvOff (\r
  UINT64   Val\r
  );\r
\r
UINTN\r
EFIAPI\r
ArmGetPhysicalAddressBits (\r
  VOID\r
  );\r
\r
#endif // __ARM_LIB__\r
Commit	Line	Data
1e57a462	1	/** @file\r
	2	\r
	3	Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
ff1f27c0	4	Copyright (c) 2011 - 2016, ARM Ltd. All rights reserved.<BR>\r
1e57a462	5	\r
4059386c	6	SPDX-License-Identifier: BSD-2-Clause-Patent\r
1e57a462	7	\r
	8	**/\r
	9	\r
	10	#ifndef __ARM_LIB__\r
	11	#define __ARM_LIB__\r
	12	\r
	13	#include <Uefi/UefiBaseType.h>\r
	14	\r
25402f5d	15	#ifdef MDE_CPU_ARM\r
70119d27	16	#include <Chipset/ArmV7.h>\r
25402f5d HL	17	#elif defined(MDE_CPU_AARCH64)\r
25402f5d HL	18	#include <Chipset/AArch64.h>\r
1e57a462	19	#else\r
25402f5d	20	#error "Unknown chipset."\r
1e57a462	21	#endif\r
1e57a462	22	\r
e0307a7d AB	23	#define EFI_MEMORY_CACHETYPE_MASK (EFI_MEMORY_UC \| EFI_MEMORY_WC \| \\r
	24	EFI_MEMORY_WT \| EFI_MEMORY_WB \| \\r
	25	EFI_MEMORY_UCE)\r
	26	\r
1e57a462	27	/**\r
	28	* The UEFI firmware must not use the ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_* attributes.\r
	29	*\r
	30	* The Non Secure memory attribute (ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_*) should only\r
	31	* be used in Secure World to distinguished Secure to Non-Secure memory.\r
	32	*/\r
	33	typedef enum {\r
	34	ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED = 0,\r
	35	ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_UNCACHED_UNBUFFERED,\r
	36	ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK,\r
	37	ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK,\r
829633e3 PL	38	\r
	39	// On some platforms, memory mapped flash region is designed as not supporting\r
	40	// shareable attribute, so WRITE_BACK_NONSHAREABLE is added for such special\r
	41	// need.\r
	42	// Do NOT use below two attributes if you are not sure.\r
	43	ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK_NONSHAREABLE,\r
	44	ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK_NONSHAREABLE,\r
	45	\r
1e57a462	46	ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH,\r
	47	ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_THROUGH,\r
	48	ARM_MEMORY_REGION_ATTRIBUTE_DEVICE,\r
	49	ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_DEVICE\r
	50	} ARM_MEMORY_REGION_ATTRIBUTES;\r
	51	\r
	52	#define IS_ARM_MEMORY_REGION_ATTRIBUTES_SECURE(attr) ((UINT32)(attr) & 1)\r
	53	\r
	54	typedef struct {\r
	55	EFI_PHYSICAL_ADDRESS PhysicalBase;\r
	56	EFI_VIRTUAL_ADDRESS VirtualBase;\r
c357fd6a	57	UINT64 Length;\r
1e57a462	58	ARM_MEMORY_REGION_ATTRIBUTES Attributes;\r
	59	} ARM_MEMORY_REGION_DESCRIPTOR;\r
	60	\r
	61	typedef VOID (*CACHE_OPERATION)(VOID);\r
	62	typedef VOID (*LINE_OPERATION)(UINTN);\r
	63	\r
	64	//\r
	65	// ARM Processor Mode\r
	66	//\r
	67	typedef enum {\r
	68	ARM_PROCESSOR_MODE_USER = 0x10,\r
	69	ARM_PROCESSOR_MODE_FIQ = 0x11,\r
	70	ARM_PROCESSOR_MODE_IRQ = 0x12,\r
	71	ARM_PROCESSOR_MODE_SUPERVISOR = 0x13,\r
	72	ARM_PROCESSOR_MODE_ABORT = 0x17,\r
	73	ARM_PROCESSOR_MODE_HYP = 0x1A,\r
	74	ARM_PROCESSOR_MODE_UNDEFINED = 0x1B,\r
	75	ARM_PROCESSOR_MODE_SYSTEM = 0x1F,\r
	76	ARM_PROCESSOR_MODE_MASK = 0x1F\r
	77	} ARM_PROCESSOR_MODE;\r
	78	\r
	79	//\r
	80	// ARM Cpu IDs\r
	81	//\r
	82	#define ARM_CPU_IMPLEMENTER_MASK (0xFFU << 24)\r
	83	#define ARM_CPU_IMPLEMENTER_ARMLTD (0x41U << 24)\r
	84	#define ARM_CPU_IMPLEMENTER_DEC (0x44U << 24)\r
	85	#define ARM_CPU_IMPLEMENTER_MOT (0x4DU << 24)\r
	86	#define ARM_CPU_IMPLEMENTER_QUALCOMM (0x51U << 24)\r
	87	#define ARM_CPU_IMPLEMENTER_MARVELL (0x56U << 24)\r
	88	\r
	89	#define ARM_CPU_PRIMARY_PART_MASK (0xFFF << 4)\r
	90	#define ARM_CPU_PRIMARY_PART_CORTEXA5 (0xC05 << 4)\r
	91	#define ARM_CPU_PRIMARY_PART_CORTEXA7 (0xC07 << 4)\r
	92	#define ARM_CPU_PRIMARY_PART_CORTEXA8 (0xC08 << 4)\r
	93	#define ARM_CPU_PRIMARY_PART_CORTEXA9 (0xC09 << 4)\r
	94	#define ARM_CPU_PRIMARY_PART_CORTEXA15 (0xC0F << 4)\r
	95	\r
	96	//\r
	97	// ARM MP Core IDs\r
	98	//\r
90ed18ca OM	99	#define ARM_CORE_AFF0 0xFF\r
	100	#define ARM_CORE_AFF1 (0xFF << 8)\r
	101	#define ARM_CORE_AFF2 (0xFF << 16)\r
	102	#define ARM_CORE_AFF3 (0xFFULL << 32)\r
	103	\r
	104	#define ARM_CORE_MASK ARM_CORE_AFF0\r
	105	#define ARM_CLUSTER_MASK ARM_CORE_AFF1\r
1e57a462	106	#define GET_CORE_ID(MpId) ((MpId) & ARM_CORE_MASK)\r
1e57a462	107	#define GET_CLUSTER_ID(MpId) (((MpId) & ARM_CLUSTER_MASK) >> 8)\r
e359565e	108	#define GET_MPID(ClusterId, CoreId) (((ClusterId) << 8) \| (CoreId))\r
1e57a462	109	#define PRIMARY_CORE_ID (PcdGet32(PcdArmPrimaryCore) & ARM_CORE_MASK)\r
1e57a462	110	\r
1e57a462	111	UINTN\r
	112	EFIAPI\r
	113	ArmDataCacheLineLength (\r
	114	VOID\r
	115	);\r
3402aac7	116	\r
1e57a462	117	UINTN\r
	118	EFIAPI\r
	119	ArmInstructionCacheLineLength (\r
	120	VOID\r
	121	);\r
168d7245	122	\r
c653fc2a AB	123	UINTN\r
	124	EFIAPI\r
	125	ArmCacheWritebackGranule (\r
	126	VOID\r
	127	);\r
	128	\r
168d7245 OM	129	UINTN\r
	130	EFIAPI\r
	131	ArmIsArchTimerImplemented (\r
	132	VOID\r
	133	);\r
	134	\r
	135	UINTN\r
	136	EFIAPI\r
	137	ArmReadIdPfr0 (\r
	138	VOID\r
	139	);\r
	140	\r
	141	UINTN\r
	142	EFIAPI\r
	143	ArmReadIdPfr1 (\r
	144	VOID\r
	145	);\r
	146	\r
64751727	147	UINTN\r
1e57a462	148	EFIAPI\r
64751727	149	ArmCacheInfo (\r
1e57a462	150	VOID\r
	151	);\r
	152	\r
	153	BOOLEAN\r
	154	EFIAPI\r
	155	ArmIsMpCore (\r
	156	VOID\r
	157	);\r
	158	\r
	159	VOID\r
	160	EFIAPI\r
	161	ArmInvalidateDataCache (\r
	162	VOID\r
	163	);\r
	164	\r
	165	\r
	166	VOID\r
	167	EFIAPI\r
	168	ArmCleanInvalidateDataCache (\r
	169	VOID\r
	170	);\r
	171	\r
	172	VOID\r
	173	EFIAPI\r
	174	ArmCleanDataCache (\r
	175	VOID\r
	176	);\r
	177	\r
1e57a462	178	VOID\r
	179	EFIAPI\r
	180	ArmInvalidateInstructionCache (\r
	181	VOID\r
	182	);\r
	183	\r
	184	VOID\r
	185	EFIAPI\r
	186	ArmInvalidateDataCacheEntryByMVA (\r
	187	IN UINTN Address\r
	188	);\r
	189	\r
	190	VOID\r
	191	EFIAPI\r
cf580da1	192	ArmCleanDataCacheEntryToPoUByMVA (\r
1e57a462	193	IN UINTN Address\r
	194	);\r
	195	\r
b7de7e3c EC	196	VOID\r
b7de7e3c EC	197	EFIAPI\r
cf580da1 AB	198	ArmInvalidateInstructionCacheEntryToPoUByMVA (\r
	199	IN UINTN Address\r
	200	);\r
	201	\r
	202	VOID\r
	203	EFIAPI\r
	204	ArmCleanDataCacheEntryByMVA (\r
b7de7e3c EC	205	IN UINTN Address\r
	206	);\r
	207	\r
1e57a462	208	VOID\r
	209	EFIAPI\r
	210	ArmCleanInvalidateDataCacheEntryByMVA (\r
	211	IN UINTN Address\r
	212	);\r
	213	\r
0ff0e414 OM	214	VOID\r
	215	EFIAPI\r
	216	ArmInvalidateDataCacheEntryBySetWay (\r
	217	IN UINTN SetWayFormat\r
	218	);\r
	219	\r
	220	VOID\r
	221	EFIAPI\r
	222	ArmCleanDataCacheEntryBySetWay (\r
	223	IN UINTN SetWayFormat\r
	224	);\r
	225	\r
	226	VOID\r
	227	EFIAPI\r
	228	ArmCleanInvalidateDataCacheEntryBySetWay (\r
	229	IN UINTN SetWayFormat\r
	230	);\r
	231	\r
1e57a462	232	VOID\r
	233	EFIAPI\r
	234	ArmEnableDataCache (\r
	235	VOID\r
	236	);\r
	237	\r
	238	VOID\r
	239	EFIAPI\r
	240	ArmDisableDataCache (\r
	241	VOID\r
	242	);\r
	243	\r
	244	VOID\r
	245	EFIAPI\r
	246	ArmEnableInstructionCache (\r
	247	VOID\r
	248	);\r
	249	\r
	250	VOID\r
	251	EFIAPI\r
	252	ArmDisableInstructionCache (\r
	253	VOID\r
	254	);\r
3402aac7	255	\r
1e57a462	256	VOID\r
	257	EFIAPI\r
	258	ArmEnableMmu (\r
	259	VOID\r
	260	);\r
	261	\r
	262	VOID\r
	263	EFIAPI\r
	264	ArmDisableMmu (\r
	265	VOID\r
	266	);\r
	267	\r
0ff0e414 OM	268	VOID\r
	269	EFIAPI\r
	270	ArmEnableCachesAndMmu (\r
	271	VOID\r
	272	);\r
	273	\r
1e57a462	274	VOID\r
	275	EFIAPI\r
	276	ArmDisableCachesAndMmu (\r
	277	VOID\r
	278	);\r
	279	\r
1e57a462	280	VOID\r
	281	EFIAPI\r
	282	ArmEnableInterrupts (\r
	283	VOID\r
	284	);\r
	285	\r
	286	UINTN\r
	287	EFIAPI\r
	288	ArmDisableInterrupts (\r
	289	VOID\r
	290	);\r
47585ed5	291	\r
1e57a462	292	BOOLEAN\r
	293	EFIAPI\r
	294	ArmGetInterruptState (\r
	295	VOID\r
	296	);\r
	297	\r
0ff0e414 OM	298	VOID\r
	299	EFIAPI\r
	300	ArmEnableAsynchronousAbort (\r
	301	VOID\r
	302	);\r
	303	\r
47585ed5	304	UINTN\r
47585ed5	305	EFIAPI\r
0ff0e414	306	ArmDisableAsynchronousAbort (\r
47585ed5	307	VOID\r
	308	);\r
	309	\r
	310	VOID\r
	311	EFIAPI\r
	312	ArmEnableIrq (\r
	313	VOID\r
	314	);\r
	315	\r
0ff0e414 OM	316	UINTN\r
	317	EFIAPI\r
	318	ArmDisableIrq (\r
	319	VOID\r
	320	);\r
	321	\r
1e57a462	322	VOID\r
	323	EFIAPI\r
	324	ArmEnableFiq (\r
	325	VOID\r
	326	);\r
	327	\r
	328	UINTN\r
	329	EFIAPI\r
	330	ArmDisableFiq (\r
	331	VOID\r
	332	);\r
3402aac7	333	\r
1e57a462	334	BOOLEAN\r
	335	EFIAPI\r
	336	ArmGetFiqState (\r
	337	VOID\r
	338	);\r
	339	\r
8dd618d2 OM	340	/**\r
	341	* Invalidate Data and Instruction TLBs\r
	342	*/\r
1e57a462	343	VOID\r
	344	EFIAPI\r
	345	ArmInvalidateTlb (\r
	346	VOID\r
	347	);\r
3402aac7	348	\r
1e57a462	349	VOID\r
	350	EFIAPI\r
	351	ArmUpdateTranslationTableEntry (\r
	352	IN VOID *TranslationTableEntry,\r
	353	IN VOID *Mva\r
	354	);\r
3402aac7	355	\r
1e57a462	356	VOID\r
	357	EFIAPI\r
	358	ArmSetDomainAccessControl (\r
	359	IN UINT32 Domain\r
	360	);\r
	361	\r
	362	VOID\r
	363	EFIAPI\r
	364	ArmSetTTBR0 (\r
	365	IN VOID *TranslationTableBase\r
	366	);\r
	367	\r
ff1f27c0 EL	368	VOID\r
	369	EFIAPI\r
	370	ArmSetTTBCR (\r
	371	IN UINT32 Bits\r
	372	);\r
	373	\r
1e57a462	374	VOID *\r
	375	EFIAPI\r
	376	ArmGetTTBR0BaseAddress (\r
	377	VOID\r
	378	);\r
	379	\r
1e57a462	380	BOOLEAN\r
	381	EFIAPI\r
	382	ArmMmuEnabled (\r
	383	VOID\r
	384	);\r
3402aac7	385	\r
1e57a462	386	VOID\r
	387	EFIAPI\r
	388	ArmEnableBranchPrediction (\r
	389	VOID\r
	390	);\r
	391	\r
	392	VOID\r
	393	EFIAPI\r
	394	ArmDisableBranchPrediction (\r
	395	VOID\r
	396	);\r
	397	\r
	398	VOID\r
	399	EFIAPI\r
	400	ArmSetLowVectors (\r
	401	VOID\r
	402	);\r
	403	\r
	404	VOID\r
	405	EFIAPI\r
	406	ArmSetHighVectors (\r
	407	VOID\r
	408	);\r
	409	\r
	410	VOID\r
	411	EFIAPI\r
	412	ArmDataMemoryBarrier (\r
	413	VOID\r
	414	);\r
3402aac7	415	\r
1e57a462	416	VOID\r
1e57a462	417	EFIAPI\r
cf93a378	418	ArmDataSynchronizationBarrier (\r
1e57a462	419	VOID\r
1e57a462	420	);\r
3402aac7	421	\r
1e57a462	422	VOID\r
	423	EFIAPI\r
	424	ArmInstructionSynchronizationBarrier (\r
	425	VOID\r
	426	);\r
	427	\r
	428	VOID\r
	429	EFIAPI\r
	430	ArmWriteVBar (\r
4e57d6d7	431	IN UINTN VectorBase\r
1e57a462	432	);\r
1e57a462	433	\r
4e57d6d7	434	UINTN\r
1e57a462	435	EFIAPI\r
	436	ArmReadVBar (\r
	437	VOID\r
	438	);\r
	439	\r
	440	VOID\r
	441	EFIAPI\r
	442	ArmWriteAuxCr (\r
	443	IN UINT32 Bit\r
	444	);\r
	445	\r
	446	UINT32\r
	447	EFIAPI\r
	448	ArmReadAuxCr (\r
	449	VOID\r
	450	);\r
	451	\r
	452	VOID\r
	453	EFIAPI\r
	454	ArmSetAuxCrBit (\r
	455	IN UINT32 Bits\r
	456	);\r
	457	\r
	458	VOID\r
	459	EFIAPI\r
	460	ArmUnsetAuxCrBit (\r
	461	IN UINT32 Bits\r
	462	);\r
	463	\r
	464	VOID\r
	465	EFIAPI\r
	466	ArmCallSEV (\r
	467	VOID\r
	468	);\r
	469	\r
	470	VOID\r
	471	EFIAPI\r
	472	ArmCallWFE (\r
	473	VOID\r
	474	);\r
	475	\r
	476	VOID\r
	477	EFIAPI\r
	478	ArmCallWFI (\r
25402f5d	479	\r
1e57a462	480	VOID\r
	481	);\r
	482	\r
	483	UINTN\r
	484	EFIAPI\r
	485	ArmReadMpidr (\r
	486	VOID\r
	487	);\r
	488	\r
9401d6f4 OM	489	UINTN\r
	490	EFIAPI\r
	491	ArmReadMidr (\r
	492	VOID\r
	493	);\r
	494	\r
1e57a462	495	UINT32\r
	496	EFIAPI\r
	497	ArmReadCpacr (\r
	498	VOID\r
	499	);\r
	500	\r
	501	VOID\r
	502	EFIAPI\r
	503	ArmWriteCpacr (\r
	504	IN UINT32 Access\r
	505	);\r
	506	\r
	507	VOID\r
	508	EFIAPI\r
	509	ArmEnableVFP (\r
	510	VOID\r
	511	);\r
	512	\r
46d4d75c OM	513	/**\r
	514	Get the Secure Configuration Register value\r
	515	\r
	516	@return Value read from the Secure Configuration Register\r
	517	\r
	518	**/\r
1e57a462	519	UINT32\r
	520	EFIAPI\r
	521	ArmReadScr (\r
	522	VOID\r
	523	);\r
	524	\r
46d4d75c OM	525	/**\r
	526	Set the Secure Configuration Register\r
	527	\r
	528	@param Value Value to write to the Secure Configuration Register\r
	529	\r
	530	**/\r
1e57a462	531	VOID\r
	532	EFIAPI\r
	533	ArmWriteScr (\r
46d4d75c	534	IN UINT32 Value\r
1e57a462	535	);\r
	536	\r
	537	UINT32\r
	538	EFIAPI\r
	539	ArmReadMVBar (\r
	540	VOID\r
	541	);\r
	542	\r
	543	VOID\r
	544	EFIAPI\r
	545	ArmWriteMVBar (\r
	546	IN UINT32 VectorMonitorBase\r
	547	);\r
	548	\r
	549	UINT32\r
	550	EFIAPI\r
	551	ArmReadSctlr (\r
	552	VOID\r
	553	);\r
	554	\r
1e1d1697 MZ	555	VOID\r
	556	EFIAPI\r
	557	ArmWriteSctlr (\r
	558	IN UINT32 Value\r
	559	);\r
	560	\r
5ea2c2d3	561	UINTN\r
	562	EFIAPI\r
	563	ArmReadHVBar (\r
	564	VOID\r
	565	);\r
	566	\r
	567	VOID\r
	568	EFIAPI\r
	569	ArmWriteHVBar (\r
	570	IN UINTN HypModeVectorBase\r
	571	);\r
	572	\r
52d44f77 OM	573	\r
	574	//\r
	575	// Helper functions for accessing CPU ACTLR\r
	576	//\r
	577	\r
	578	UINTN\r
	579	EFIAPI\r
	580	ArmReadCpuActlr (\r
	581	VOID\r
	582	);\r
	583	\r
	584	VOID\r
	585	EFIAPI\r
	586	ArmWriteCpuActlr (\r
	587	IN UINTN Val\r
	588	);\r
	589	\r
	590	VOID\r
	591	EFIAPI\r
	592	ArmSetCpuActlrBit (\r
	593	IN UINTN Bits\r
	594	);\r
	595	\r
	596	VOID\r
	597	EFIAPI\r
	598	ArmUnsetCpuActlrBit (\r
	599	IN UINTN Bits\r
	600	);\r
	601	\r
734bd6cc AB	602	//\r
	603	// Accessors for the architected generic timer registers\r
	604	//\r
	605	\r
	606	#define ARM_ARCH_TIMER_ENABLE (1 << 0)\r
	607	#define ARM_ARCH_TIMER_IMASK (1 << 1)\r
	608	#define ARM_ARCH_TIMER_ISTATUS (1 << 2)\r
	609	\r
	610	UINTN\r
	611	EFIAPI\r
	612	ArmReadCntFrq (\r
	613	VOID\r
	614	);\r
	615	\r
	616	VOID\r
	617	EFIAPI\r
	618	ArmWriteCntFrq (\r
	619	UINTN FreqInHz\r
	620	);\r
	621	\r
	622	UINT64\r
	623	EFIAPI\r
	624	ArmReadCntPct (\r
	625	VOID\r
	626	);\r
	627	\r
	628	UINTN\r
	629	EFIAPI\r
	630	ArmReadCntkCtl (\r
	631	VOID\r
	632	);\r
	633	\r
	634	VOID\r
	635	EFIAPI\r
	636	ArmWriteCntkCtl (\r
	637	UINTN Val\r
	638	);\r
	639	\r
	640	UINTN\r
	641	EFIAPI\r
	642	ArmReadCntpTval (\r
	643	VOID\r
	644	);\r
	645	\r
	646	VOID\r
	647	EFIAPI\r
	648	ArmWriteCntpTval (\r
	649	UINTN Val\r
	650	);\r
	651	\r
	652	UINTN\r
	653	EFIAPI\r
	654	ArmReadCntpCtl (\r
	655	VOID\r
	656	);\r
	657	\r
	658	VOID\r
	659	EFIAPI\r
	660	ArmWriteCntpCtl (\r
	661	UINTN Val\r
	662	);\r
	663	\r
	664	UINTN\r
	665	EFIAPI\r
666	ArmReadCntvTval (\r
667	VOID\r
668	);\r
669	\r
670	VOID\r
671	EFIAPI\r
672	ArmWriteCntvTval (\r
673	UINTN Val\r
674	);\r
675	\r
676	UINTN\r
677	EFIAPI\r
678	ArmReadCntvCtl (\r
679	VOID\r
680	);\r
681	\r
682	VOID\r
683	EFIAPI\r
684	ArmWriteCntvCtl (\r
685	UINTN Val\r
686	);\r
687	\r
688	UINT64\r
689	EFIAPI\r
690	ArmReadCntvCt (\r
691	VOID\r
692	);\r
693	\r
694	UINT64\r
695	EFIAPI\r
696	ArmReadCntpCval (\r
697	VOID\r
698	);\r
699	\r
700	VOID\r
701	EFIAPI\r
702	ArmWriteCntpCval (\r
703	UINT64 Val\r
704	);\r
705	\r
706	UINT64\r
707	EFIAPI\r
708	ArmReadCntvCval (\r
709	VOID\r
710	);\r
711	\r
712	VOID\r
713	EFIAPI\r
714	ArmWriteCntvCval (\r
715	UINT64 Val\r
716	);\r
717	\r
718	UINT64\r
719	EFIAPI\r
720	ArmReadCntvOff (\r
721	VOID\r
722	);\r
723	\r
724	VOID\r
725	EFIAPI\r
726	ArmWriteCntvOff (\r
727	UINT64 Val\r
728	);\r
729	\r
95d04ebc AB	730	UINTN\r
	731	EFIAPI\r
	732	ArmGetPhysicalAddressBits (\r
	733	VOID\r
	734	);\r
	735	\r
1e57a462	736	#endif // __ARM_LIB__\r