[mirror_edk2.git] / ArmPkg / Include / Library / ArmLib.h

/** @file\r
\r
  Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
  Copyright (c) 2011 - 2016, ARM Ltd. All rights reserved.<BR>\r
\r
  This program and the accompanying materials\r
  are licensed and made available under the terms and conditions of the BSD License\r
  which accompanies this distribution.  The full text of the license may be found at\r
  http://opensource.org/licenses/bsd-license.php\r
\r
  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
**/\r
\r
#ifndef __ARM_LIB__\r
#define __ARM_LIB__\r
\r
#include <Uefi/UefiBaseType.h>\r
\r
#ifdef MDE_CPU_ARM\r
  #include <Chipset/ArmV7.h>\r
#elif defined(MDE_CPU_AARCH64)\r
  #include <Chipset/AArch64.h>\r
#else\r
 #error "Unknown chipset."\r
#endif\r
\r
/**\r
 * The UEFI firmware must not use the ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_* attributes.\r
 *\r
 * The Non Secure memory attribute (ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_*) should only\r
 * be used in Secure World to distinguished Secure to Non-Secure memory.\r
 */\r
typedef enum {\r
  ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED = 0,\r
  ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_UNCACHED_UNBUFFERED,\r
  ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK,\r
  ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK,\r
  ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH,\r
  ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_THROUGH,\r
  ARM_MEMORY_REGION_ATTRIBUTE_DEVICE,\r
  ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_DEVICE\r
} ARM_MEMORY_REGION_ATTRIBUTES;\r
\r
#define IS_ARM_MEMORY_REGION_ATTRIBUTES_SECURE(attr) ((UINT32)(attr) & 1)\r
\r
typedef struct {\r
  EFI_PHYSICAL_ADDRESS          PhysicalBase;\r
  EFI_VIRTUAL_ADDRESS           VirtualBase;\r
  UINT64                        Length;\r
  ARM_MEMORY_REGION_ATTRIBUTES  Attributes;\r
} ARM_MEMORY_REGION_DESCRIPTOR;\r
\r
typedef VOID (*CACHE_OPERATION)(VOID);\r
typedef VOID (*LINE_OPERATION)(UINTN);\r
\r
//\r
// ARM Processor Mode\r
//\r
typedef enum {\r
  ARM_PROCESSOR_MODE_USER       = 0x10,\r
  ARM_PROCESSOR_MODE_FIQ        = 0x11,\r
  ARM_PROCESSOR_MODE_IRQ        = 0x12,\r
  ARM_PROCESSOR_MODE_SUPERVISOR = 0x13,\r
  ARM_PROCESSOR_MODE_ABORT      = 0x17,\r
  ARM_PROCESSOR_MODE_HYP        = 0x1A,\r
  ARM_PROCESSOR_MODE_UNDEFINED  = 0x1B,\r
  ARM_PROCESSOR_MODE_SYSTEM     = 0x1F,\r
  ARM_PROCESSOR_MODE_MASK       = 0x1F\r
} ARM_PROCESSOR_MODE;\r
\r
//\r
// ARM Cpu IDs\r
//\r
#define ARM_CPU_IMPLEMENTER_MASK          (0xFFU << 24)\r
#define ARM_CPU_IMPLEMENTER_ARMLTD        (0x41U << 24)\r
#define ARM_CPU_IMPLEMENTER_DEC           (0x44U << 24)\r
#define ARM_CPU_IMPLEMENTER_MOT           (0x4DU << 24)\r
#define ARM_CPU_IMPLEMENTER_QUALCOMM      (0x51U << 24)\r
#define ARM_CPU_IMPLEMENTER_MARVELL       (0x56U << 24)\r
\r
#define ARM_CPU_PRIMARY_PART_MASK         (0xFFF << 4)\r
#define ARM_CPU_PRIMARY_PART_CORTEXA5     (0xC05 << 4)\r
#define ARM_CPU_PRIMARY_PART_CORTEXA7     (0xC07 << 4)\r
#define ARM_CPU_PRIMARY_PART_CORTEXA8     (0xC08 << 4)\r
#define ARM_CPU_PRIMARY_PART_CORTEXA9     (0xC09 << 4)\r
#define ARM_CPU_PRIMARY_PART_CORTEXA15    (0xC0F << 4)\r
\r
//\r
// ARM MP Core IDs\r
//\r
#define ARM_CORE_AFF0         0xFF\r
#define ARM_CORE_AFF1         (0xFF << 8)\r
#define ARM_CORE_AFF2         (0xFF << 16)\r
#define ARM_CORE_AFF3         (0xFFULL << 32)\r
\r
#define ARM_CORE_MASK         ARM_CORE_AFF0\r
#define ARM_CLUSTER_MASK      ARM_CORE_AFF1\r
#define GET_CORE_ID(MpId)     ((MpId) & ARM_CORE_MASK)\r
#define GET_CLUSTER_ID(MpId)  (((MpId) & ARM_CLUSTER_MASK) >> 8)\r
#define GET_MPID(ClusterId, CoreId)   (((ClusterId) << 8) | (CoreId))\r
#define PRIMARY_CORE_ID       (PcdGet32(PcdArmPrimaryCore) & ARM_CORE_MASK)\r
\r
UINTN\r
EFIAPI\r
ArmDataCacheLineLength (\r
  VOID\r
  );\r
\r
UINTN\r
EFIAPI\r
ArmInstructionCacheLineLength (\r
  VOID\r
  );\r
\r
UINTN\r
EFIAPI\r
ArmCacheWritebackGranule (\r
  VOID\r
  );\r
\r
UINTN\r
EFIAPI\r
ArmIsArchTimerImplemented (\r
  VOID\r
  );\r
\r
UINTN\r
EFIAPI\r
ArmReadIdPfr0 (\r
  VOID\r
  );\r
\r
UINTN\r
EFIAPI\r
ArmReadIdPfr1 (\r
  VOID\r
  );\r
\r
UINTN\r
EFIAPI\r
ArmCacheInfo (\r
  VOID\r
  );\r
\r
BOOLEAN\r
EFIAPI\r
ArmIsMpCore (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmInvalidateDataCache (\r
  VOID\r
  );\r
\r
\r
VOID\r
EFIAPI\r
ArmCleanInvalidateDataCache (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmCleanDataCache (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmInvalidateInstructionCache (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmInvalidateDataCacheEntryByMVA (\r
  IN  UINTN   Address\r
  );\r
\r
VOID\r
EFIAPI\r
ArmCleanDataCacheEntryToPoUByMVA (\r
  IN  UINTN   Address\r
  );\r
\r
VOID\r
EFIAPI\r
ArmInvalidateInstructionCacheEntryToPoUByMVA (\r
  IN  UINTN   Address\r
  );\r
\r
VOID\r
EFIAPI\r
ArmCleanDataCacheEntryByMVA (\r
IN  UINTN   Address\r
);\r
\r
VOID\r
EFIAPI\r
ArmCleanInvalidateDataCacheEntryByMVA (\r
  IN  UINTN   Address\r
  );\r
\r
VOID\r
EFIAPI\r
ArmInvalidateDataCacheEntryBySetWay (\r
  IN  UINTN  SetWayFormat\r
  );\r
\r
VOID\r
EFIAPI\r
ArmCleanDataCacheEntryBySetWay (\r
  IN  UINTN  SetWayFormat\r
  );\r
\r
VOID\r
EFIAPI\r
ArmCleanInvalidateDataCacheEntryBySetWay (\r
  IN  UINTN   SetWayFormat\r
  );\r
\r
VOID\r
EFIAPI\r
ArmEnableDataCache (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmDisableDataCache (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmEnableInstructionCache (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmDisableInstructionCache (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmEnableMmu (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmDisableMmu (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmEnableCachesAndMmu (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmDisableCachesAndMmu (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmEnableInterrupts (\r
  VOID\r
  );\r
\r
UINTN\r
EFIAPI\r
ArmDisableInterrupts (\r
  VOID\r
  );\r
\r
BOOLEAN\r
EFIAPI\r
ArmGetInterruptState (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmEnableAsynchronousAbort (\r
  VOID\r
  );\r
\r
UINTN\r
EFIAPI\r
ArmDisableAsynchronousAbort (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmEnableIrq (\r
  VOID\r
  );\r
\r
UINTN\r
EFIAPI\r
ArmDisableIrq (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmEnableFiq (\r
  VOID\r
  );\r
\r
UINTN\r
EFIAPI\r
ArmDisableFiq (\r
  VOID\r
  );\r
\r
BOOLEAN\r
EFIAPI\r
ArmGetFiqState (\r
  VOID\r
  );\r
\r
/**\r
 * Invalidate Data and Instruction TLBs\r
 */\r
VOID\r
EFIAPI\r
ArmInvalidateTlb (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmUpdateTranslationTableEntry (\r
  IN  VOID     *TranslationTableEntry,\r
  IN  VOID     *Mva\r
  );\r
\r
VOID\r
EFIAPI\r
ArmSetDomainAccessControl (\r
  IN  UINT32  Domain\r
  );\r
\r
VOID\r
EFIAPI\r
ArmSetTTBR0 (\r
  IN  VOID  *TranslationTableBase\r
  );\r
\r
VOID\r
EFIAPI\r
ArmSetTTBCR (\r
  IN  UINT32 Bits\r
  );\r
\r
VOID *\r
EFIAPI\r
ArmGetTTBR0BaseAddress (\r
  VOID\r
  );\r
\r
BOOLEAN\r
EFIAPI\r
ArmMmuEnabled (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmEnableBranchPrediction (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmDisableBranchPrediction (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmSetLowVectors (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmSetHighVectors (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmDataMemoryBarrier (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmDataSynchronizationBarrier (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmInstructionSynchronizationBarrier (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmWriteVBar (\r
  IN  UINTN   VectorBase\r
  );\r
\r
UINTN\r
EFIAPI\r
ArmReadVBar (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmWriteAuxCr (\r
  IN  UINT32    Bit\r
  );\r
\r
UINT32\r
EFIAPI\r
ArmReadAuxCr (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmSetAuxCrBit (\r
  IN  UINT32    Bits\r
  );\r
\r
VOID\r
EFIAPI\r
ArmUnsetAuxCrBit (\r
  IN  UINT32    Bits\r
  );\r
\r
VOID\r
EFIAPI\r
ArmCallSEV (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmCallWFE (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmCallWFI (\r
\r
  VOID\r
  );\r
\r
UINTN\r
EFIAPI\r
ArmReadMpidr (\r
  VOID\r
  );\r
\r
UINTN\r
EFIAPI\r
ArmReadMidr (\r
  VOID\r
  );\r
\r
UINT32\r
EFIAPI\r
ArmReadCpacr (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmWriteCpacr (\r
  IN  UINT32   Access\r
  );\r
\r
VOID\r
EFIAPI\r
ArmEnableVFP (\r
  VOID\r
  );\r
\r
/**\r
  Get the Secure Configuration Register value\r
\r
  @return   Value read from the Secure Configuration Register\r
\r
**/\r
UINT32\r
EFIAPI\r
ArmReadScr (\r
  VOID\r
  );\r
\r
/**\r
  Set the Secure Configuration Register\r
\r
  @param Value   Value to write to the Secure Configuration Register\r
\r
**/\r
VOID\r
EFIAPI\r
ArmWriteScr (\r
  IN  UINT32   Value\r
  );\r
\r
UINT32\r
EFIAPI\r
ArmReadMVBar (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmWriteMVBar (\r
  IN  UINT32   VectorMonitorBase\r
  );\r
\r
UINT32\r
EFIAPI\r
ArmReadSctlr (\r
  VOID\r
  );\r
\r
UINTN\r
EFIAPI\r
ArmReadHVBar (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmWriteHVBar (\r
  IN  UINTN   HypModeVectorBase\r
  );\r
\r
\r
//\r
// Helper functions for accessing CPU ACTLR\r
//\r
\r
UINTN\r
EFIAPI\r
ArmReadCpuActlr (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmWriteCpuActlr (\r
  IN  UINTN Val\r
  );\r
\r
VOID\r
EFIAPI\r
ArmSetCpuActlrBit (\r
  IN  UINTN    Bits\r
  );\r
\r
VOID\r
EFIAPI\r
ArmUnsetCpuActlrBit (\r
  IN  UINTN    Bits\r
  );\r
\r
#endif // __ARM_LIB__\r
Commit	Line	Data
1e57a462	1	/** @file\r
	2	\r
	3	Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
ff1f27c0	4	Copyright (c) 2011 - 2016, ARM Ltd. All rights reserved.<BR>\r
1e57a462	5	\r
	6	This program and the accompanying materials\r
	7	are licensed and made available under the terms and conditions of the BSD License\r
	8	which accompanies this distribution. The full text of the license may be found at\r
	9	http://opensource.org/licenses/bsd-license.php\r
	10	\r
	11	THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
	12	WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
	13	\r
	14	**/\r
	15	\r
	16	#ifndef __ARM_LIB__\r
	17	#define __ARM_LIB__\r
	18	\r
	19	#include <Uefi/UefiBaseType.h>\r
	20	\r
25402f5d	21	#ifdef MDE_CPU_ARM\r
70119d27	22	#include <Chipset/ArmV7.h>\r
25402f5d HL	23	#elif defined(MDE_CPU_AARCH64)\r
25402f5d HL	24	#include <Chipset/AArch64.h>\r
1e57a462	25	#else\r
25402f5d	26	#error "Unknown chipset."\r
1e57a462	27	#endif\r
1e57a462	28	\r
1e57a462	29	/**\r
	30	* The UEFI firmware must not use the ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_* attributes.\r
	31	*\r
	32	* The Non Secure memory attribute (ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_*) should only\r
	33	* be used in Secure World to distinguished Secure to Non-Secure memory.\r
	34	*/\r
	35	typedef enum {\r
	36	ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED = 0,\r
	37	ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_UNCACHED_UNBUFFERED,\r
	38	ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK,\r
	39	ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK,\r
	40	ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH,\r
	41	ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_THROUGH,\r
	42	ARM_MEMORY_REGION_ATTRIBUTE_DEVICE,\r
	43	ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_DEVICE\r
	44	} ARM_MEMORY_REGION_ATTRIBUTES;\r
	45	\r
	46	#define IS_ARM_MEMORY_REGION_ATTRIBUTES_SECURE(attr) ((UINT32)(attr) & 1)\r
	47	\r
	48	typedef struct {\r
	49	EFI_PHYSICAL_ADDRESS PhysicalBase;\r
	50	EFI_VIRTUAL_ADDRESS VirtualBase;\r
c357fd6a	51	UINT64 Length;\r
1e57a462	52	ARM_MEMORY_REGION_ATTRIBUTES Attributes;\r
	53	} ARM_MEMORY_REGION_DESCRIPTOR;\r
	54	\r
	55	typedef VOID (*CACHE_OPERATION)(VOID);\r
	56	typedef VOID (*LINE_OPERATION)(UINTN);\r
	57	\r
	58	//\r
	59	// ARM Processor Mode\r
	60	//\r
	61	typedef enum {\r
	62	ARM_PROCESSOR_MODE_USER = 0x10,\r
	63	ARM_PROCESSOR_MODE_FIQ = 0x11,\r
	64	ARM_PROCESSOR_MODE_IRQ = 0x12,\r
	65	ARM_PROCESSOR_MODE_SUPERVISOR = 0x13,\r
	66	ARM_PROCESSOR_MODE_ABORT = 0x17,\r
	67	ARM_PROCESSOR_MODE_HYP = 0x1A,\r
	68	ARM_PROCESSOR_MODE_UNDEFINED = 0x1B,\r
	69	ARM_PROCESSOR_MODE_SYSTEM = 0x1F,\r
	70	ARM_PROCESSOR_MODE_MASK = 0x1F\r
	71	} ARM_PROCESSOR_MODE;\r
	72	\r
	73	//\r
	74	// ARM Cpu IDs\r
	75	//\r
	76	#define ARM_CPU_IMPLEMENTER_MASK (0xFFU << 24)\r
	77	#define ARM_CPU_IMPLEMENTER_ARMLTD (0x41U << 24)\r
	78	#define ARM_CPU_IMPLEMENTER_DEC (0x44U << 24)\r
	79	#define ARM_CPU_IMPLEMENTER_MOT (0x4DU << 24)\r
	80	#define ARM_CPU_IMPLEMENTER_QUALCOMM (0x51U << 24)\r
	81	#define ARM_CPU_IMPLEMENTER_MARVELL (0x56U << 24)\r
	82	\r
	83	#define ARM_CPU_PRIMARY_PART_MASK (0xFFF << 4)\r
	84	#define ARM_CPU_PRIMARY_PART_CORTEXA5 (0xC05 << 4)\r
	85	#define ARM_CPU_PRIMARY_PART_CORTEXA7 (0xC07 << 4)\r
	86	#define ARM_CPU_PRIMARY_PART_CORTEXA8 (0xC08 << 4)\r
	87	#define ARM_CPU_PRIMARY_PART_CORTEXA9 (0xC09 << 4)\r
	88	#define ARM_CPU_PRIMARY_PART_CORTEXA15 (0xC0F << 4)\r
	89	\r
	90	//\r
	91	// ARM MP Core IDs\r
	92	//\r
90ed18ca OM	93	#define ARM_CORE_AFF0 0xFF\r
	94	#define ARM_CORE_AFF1 (0xFF << 8)\r
	95	#define ARM_CORE_AFF2 (0xFF << 16)\r
	96	#define ARM_CORE_AFF3 (0xFFULL << 32)\r
	97	\r
	98	#define ARM_CORE_MASK ARM_CORE_AFF0\r
	99	#define ARM_CLUSTER_MASK ARM_CORE_AFF1\r
1e57a462	100	#define GET_CORE_ID(MpId) ((MpId) & ARM_CORE_MASK)\r
1e57a462	101	#define GET_CLUSTER_ID(MpId) (((MpId) & ARM_CLUSTER_MASK) >> 8)\r
e359565e	102	#define GET_MPID(ClusterId, CoreId) (((ClusterId) << 8) \| (CoreId))\r
1e57a462	103	#define PRIMARY_CORE_ID (PcdGet32(PcdArmPrimaryCore) & ARM_CORE_MASK)\r
1e57a462	104	\r
1e57a462	105	UINTN\r
	106	EFIAPI\r
	107	ArmDataCacheLineLength (\r
	108	VOID\r
	109	);\r
3402aac7	110	\r
1e57a462	111	UINTN\r
	112	EFIAPI\r
	113	ArmInstructionCacheLineLength (\r
	114	VOID\r
	115	);\r
168d7245	116	\r
c653fc2a AB	117	UINTN\r
	118	EFIAPI\r
	119	ArmCacheWritebackGranule (\r
	120	VOID\r
	121	);\r
	122	\r
168d7245 OM	123	UINTN\r
	124	EFIAPI\r
	125	ArmIsArchTimerImplemented (\r
	126	VOID\r
	127	);\r
	128	\r
	129	UINTN\r
	130	EFIAPI\r
	131	ArmReadIdPfr0 (\r
	132	VOID\r
	133	);\r
	134	\r
	135	UINTN\r
	136	EFIAPI\r
	137	ArmReadIdPfr1 (\r
	138	VOID\r
	139	);\r
	140	\r
64751727	141	UINTN\r
1e57a462	142	EFIAPI\r
64751727	143	ArmCacheInfo (\r
1e57a462	144	VOID\r
	145	);\r
	146	\r
	147	BOOLEAN\r
	148	EFIAPI\r
	149	ArmIsMpCore (\r
	150	VOID\r
	151	);\r
	152	\r
	153	VOID\r
	154	EFIAPI\r
	155	ArmInvalidateDataCache (\r
	156	VOID\r
	157	);\r
	158	\r
	159	\r
	160	VOID\r
	161	EFIAPI\r
	162	ArmCleanInvalidateDataCache (\r
	163	VOID\r
	164	);\r
	165	\r
	166	VOID\r
	167	EFIAPI\r
	168	ArmCleanDataCache (\r
	169	VOID\r
	170	);\r
	171	\r
1e57a462	172	VOID\r
	173	EFIAPI\r
	174	ArmInvalidateInstructionCache (\r
	175	VOID\r
	176	);\r
	177	\r
	178	VOID\r
	179	EFIAPI\r
	180	ArmInvalidateDataCacheEntryByMVA (\r
	181	IN UINTN Address\r
	182	);\r
	183	\r
	184	VOID\r
	185	EFIAPI\r
cf580da1	186	ArmCleanDataCacheEntryToPoUByMVA (\r
1e57a462	187	IN UINTN Address\r
	188	);\r
	189	\r
b7de7e3c EC	190	VOID\r
b7de7e3c EC	191	EFIAPI\r
cf580da1 AB	192	ArmInvalidateInstructionCacheEntryToPoUByMVA (\r
	193	IN UINTN Address\r
	194	);\r
	195	\r
	196	VOID\r
	197	EFIAPI\r
	198	ArmCleanDataCacheEntryByMVA (\r
b7de7e3c EC	199	IN UINTN Address\r
	200	);\r
	201	\r
1e57a462	202	VOID\r
	203	EFIAPI\r
	204	ArmCleanInvalidateDataCacheEntryByMVA (\r
	205	IN UINTN Address\r
	206	);\r
	207	\r
0ff0e414 OM	208	VOID\r
	209	EFIAPI\r
	210	ArmInvalidateDataCacheEntryBySetWay (\r
	211	IN UINTN SetWayFormat\r
	212	);\r
	213	\r
	214	VOID\r
	215	EFIAPI\r
	216	ArmCleanDataCacheEntryBySetWay (\r
	217	IN UINTN SetWayFormat\r
	218	);\r
	219	\r
	220	VOID\r
	221	EFIAPI\r
	222	ArmCleanInvalidateDataCacheEntryBySetWay (\r
	223	IN UINTN SetWayFormat\r
	224	);\r
	225	\r
1e57a462	226	VOID\r
	227	EFIAPI\r
	228	ArmEnableDataCache (\r
	229	VOID\r
	230	);\r
	231	\r
	232	VOID\r
	233	EFIAPI\r
	234	ArmDisableDataCache (\r
	235	VOID\r
	236	);\r
	237	\r
	238	VOID\r
	239	EFIAPI\r
	240	ArmEnableInstructionCache (\r
	241	VOID\r
	242	);\r
	243	\r
	244	VOID\r
	245	EFIAPI\r
	246	ArmDisableInstructionCache (\r
	247	VOID\r
	248	);\r
3402aac7	249	\r
1e57a462	250	VOID\r
	251	EFIAPI\r
	252	ArmEnableMmu (\r
	253	VOID\r
	254	);\r
	255	\r
	256	VOID\r
	257	EFIAPI\r
	258	ArmDisableMmu (\r
	259	VOID\r
	260	);\r
	261	\r
0ff0e414 OM	262	VOID\r
	263	EFIAPI\r
	264	ArmEnableCachesAndMmu (\r
	265	VOID\r
	266	);\r
	267	\r
1e57a462	268	VOID\r
	269	EFIAPI\r
	270	ArmDisableCachesAndMmu (\r
	271	VOID\r
	272	);\r
	273	\r
1e57a462	274	VOID\r
	275	EFIAPI\r
	276	ArmEnableInterrupts (\r
	277	VOID\r
	278	);\r
	279	\r
	280	UINTN\r
	281	EFIAPI\r
	282	ArmDisableInterrupts (\r
	283	VOID\r
	284	);\r
47585ed5	285	\r
1e57a462	286	BOOLEAN\r
	287	EFIAPI\r
	288	ArmGetInterruptState (\r
	289	VOID\r
	290	);\r
	291	\r
0ff0e414 OM	292	VOID\r
	293	EFIAPI\r
	294	ArmEnableAsynchronousAbort (\r
	295	VOID\r
	296	);\r
	297	\r
47585ed5	298	UINTN\r
47585ed5	299	EFIAPI\r
0ff0e414	300	ArmDisableAsynchronousAbort (\r
47585ed5	301	VOID\r
	302	);\r
	303	\r
	304	VOID\r
	305	EFIAPI\r
	306	ArmEnableIrq (\r
	307	VOID\r
	308	);\r
	309	\r
0ff0e414 OM	310	UINTN\r
	311	EFIAPI\r
	312	ArmDisableIrq (\r
	313	VOID\r
	314	);\r
	315	\r
1e57a462	316	VOID\r
	317	EFIAPI\r
	318	ArmEnableFiq (\r
	319	VOID\r
	320	);\r
	321	\r
	322	UINTN\r
	323	EFIAPI\r
	324	ArmDisableFiq (\r
	325	VOID\r
	326	);\r
3402aac7	327	\r
1e57a462	328	BOOLEAN\r
	329	EFIAPI\r
	330	ArmGetFiqState (\r
	331	VOID\r
	332	);\r
	333	\r
8dd618d2 OM	334	/**\r
	335	* Invalidate Data and Instruction TLBs\r
	336	*/\r
1e57a462	337	VOID\r
	338	EFIAPI\r
	339	ArmInvalidateTlb (\r
	340	VOID\r
	341	);\r
3402aac7	342	\r
1e57a462	343	VOID\r
	344	EFIAPI\r
	345	ArmUpdateTranslationTableEntry (\r
	346	IN VOID *TranslationTableEntry,\r
	347	IN VOID *Mva\r
	348	);\r
3402aac7	349	\r
1e57a462	350	VOID\r
	351	EFIAPI\r
	352	ArmSetDomainAccessControl (\r
	353	IN UINT32 Domain\r
	354	);\r
	355	\r
	356	VOID\r
	357	EFIAPI\r
	358	ArmSetTTBR0 (\r
	359	IN VOID *TranslationTableBase\r
	360	);\r
	361	\r
ff1f27c0 EL	362	VOID\r
	363	EFIAPI\r
	364	ArmSetTTBCR (\r
	365	IN UINT32 Bits\r
	366	);\r
	367	\r
1e57a462	368	VOID *\r
	369	EFIAPI\r
	370	ArmGetTTBR0BaseAddress (\r
	371	VOID\r
	372	);\r
	373	\r
1e57a462	374	BOOLEAN\r
	375	EFIAPI\r
	376	ArmMmuEnabled (\r
	377	VOID\r
	378	);\r
3402aac7	379	\r
1e57a462	380	VOID\r
	381	EFIAPI\r
	382	ArmEnableBranchPrediction (\r
	383	VOID\r
	384	);\r
	385	\r
	386	VOID\r
	387	EFIAPI\r
	388	ArmDisableBranchPrediction (\r
	389	VOID\r
	390	);\r
	391	\r
	392	VOID\r
	393	EFIAPI\r
	394	ArmSetLowVectors (\r
	395	VOID\r
	396	);\r
	397	\r
	398	VOID\r
	399	EFIAPI\r
	400	ArmSetHighVectors (\r
	401	VOID\r
	402	);\r
	403	\r
	404	VOID\r
	405	EFIAPI\r
	406	ArmDataMemoryBarrier (\r
	407	VOID\r
	408	);\r
3402aac7	409	\r
1e57a462	410	VOID\r
1e57a462	411	EFIAPI\r
cf93a378	412	ArmDataSynchronizationBarrier (\r
1e57a462	413	VOID\r
1e57a462	414	);\r
3402aac7	415	\r
1e57a462	416	VOID\r
	417	EFIAPI\r
	418	ArmInstructionSynchronizationBarrier (\r
	419	VOID\r
	420	);\r
	421	\r
	422	VOID\r
	423	EFIAPI\r
	424	ArmWriteVBar (\r
4e57d6d7	425	IN UINTN VectorBase\r
1e57a462	426	);\r
1e57a462	427	\r
4e57d6d7	428	UINTN\r
1e57a462	429	EFIAPI\r
	430	ArmReadVBar (\r
	431	VOID\r
	432	);\r
	433	\r
	434	VOID\r
	435	EFIAPI\r
	436	ArmWriteAuxCr (\r
	437	IN UINT32 Bit\r
	438	);\r
	439	\r
	440	UINT32\r
	441	EFIAPI\r
	442	ArmReadAuxCr (\r
	443	VOID\r
	444	);\r
	445	\r
	446	VOID\r
	447	EFIAPI\r
	448	ArmSetAuxCrBit (\r
	449	IN UINT32 Bits\r
	450	);\r
	451	\r
	452	VOID\r
	453	EFIAPI\r
	454	ArmUnsetAuxCrBit (\r
	455	IN UINT32 Bits\r
	456	);\r
	457	\r
	458	VOID\r
	459	EFIAPI\r
	460	ArmCallSEV (\r
	461	VOID\r
	462	);\r
	463	\r
	464	VOID\r
	465	EFIAPI\r
	466	ArmCallWFE (\r
	467	VOID\r
	468	);\r
	469	\r
	470	VOID\r
	471	EFIAPI\r
	472	ArmCallWFI (\r
25402f5d	473	\r
1e57a462	474	VOID\r
	475	);\r
	476	\r
	477	UINTN\r
	478	EFIAPI\r
	479	ArmReadMpidr (\r
	480	VOID\r
	481	);\r
	482	\r
9401d6f4 OM	483	UINTN\r
	484	EFIAPI\r
	485	ArmReadMidr (\r
	486	VOID\r
	487	);\r
	488	\r
1e57a462	489	UINT32\r
	490	EFIAPI\r
	491	ArmReadCpacr (\r
	492	VOID\r
	493	);\r
	494	\r
	495	VOID\r
	496	EFIAPI\r
	497	ArmWriteCpacr (\r
	498	IN UINT32 Access\r
	499	);\r
	500	\r
	501	VOID\r
	502	EFIAPI\r
	503	ArmEnableVFP (\r
	504	VOID\r
	505	);\r
	506	\r
46d4d75c OM	507	/**\r
	508	Get the Secure Configuration Register value\r
	509	\r
	510	@return Value read from the Secure Configuration Register\r
	511	\r
	512	**/\r
1e57a462	513	UINT32\r
	514	EFIAPI\r
	515	ArmReadScr (\r
	516	VOID\r
	517	);\r
	518	\r
46d4d75c OM	519	/**\r
	520	Set the Secure Configuration Register\r
	521	\r
	522	@param Value Value to write to the Secure Configuration Register\r
	523	\r
	524	**/\r
1e57a462	525	VOID\r
	526	EFIAPI\r
	527	ArmWriteScr (\r
46d4d75c	528	IN UINT32 Value\r
1e57a462	529	);\r
	530	\r
	531	UINT32\r
	532	EFIAPI\r
	533	ArmReadMVBar (\r
	534	VOID\r
	535	);\r
	536	\r
	537	VOID\r
	538	EFIAPI\r
	539	ArmWriteMVBar (\r
	540	IN UINT32 VectorMonitorBase\r
	541	);\r
	542	\r
	543	UINT32\r
	544	EFIAPI\r
	545	ArmReadSctlr (\r
	546	VOID\r
	547	);\r
	548	\r
5ea2c2d3	549	UINTN\r
	550	EFIAPI\r
	551	ArmReadHVBar (\r
	552	VOID\r
	553	);\r
	554	\r
	555	VOID\r
	556	EFIAPI\r
	557	ArmWriteHVBar (\r
	558	IN UINTN HypModeVectorBase\r
	559	);\r
	560	\r
52d44f77 OM	561	\r
	562	//\r
	563	// Helper functions for accessing CPU ACTLR\r
	564	//\r
	565	\r
	566	UINTN\r
	567	EFIAPI\r
	568	ArmReadCpuActlr (\r
	569	VOID\r
	570	);\r
	571	\r
	572	VOID\r
	573	EFIAPI\r
	574	ArmWriteCpuActlr (\r
	575	IN UINTN Val\r
	576	);\r
	577	\r
	578	VOID\r
	579	EFIAPI\r
	580	ArmSetCpuActlrBit (\r
	581	IN UINTN Bits\r
	582	);\r
	583	\r
	584	VOID\r
	585	EFIAPI\r
	586	ArmUnsetCpuActlrBit (\r
	587	IN UINTN Bits\r
	588	);\r
	589	\r
1e57a462	590	#endif // __ARM_LIB__\r