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1e57a462 | 1 | /** @file\r |
2 | \r | |
3 | Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r | |
ff1f27c0 | 4 | Copyright (c) 2011 - 2016, ARM Ltd. All rights reserved.<BR>\r |
5cc25cff | 5 | Copyright (c) 2020, NUVIA Inc. All rights reserved.<BR>\r |
1e57a462 | 6 | \r |
4059386c | 7 | SPDX-License-Identifier: BSD-2-Clause-Patent\r |
1e57a462 | 8 | \r |
9 | **/\r | |
10 | \r | |
11 | #ifndef __ARM_LIB__\r | |
12 | #define __ARM_LIB__\r | |
13 | \r | |
14 | #include <Uefi/UefiBaseType.h>\r | |
15 | \r | |
25402f5d | 16 | #ifdef MDE_CPU_ARM\r |
70119d27 | 17 | #include <Chipset/ArmV7.h>\r |
25402f5d HL |
18 | #elif defined(MDE_CPU_AARCH64)\r |
19 | #include <Chipset/AArch64.h>\r | |
1e57a462 | 20 | #else\r |
25402f5d | 21 | #error "Unknown chipset."\r |
1e57a462 | 22 | #endif\r |
23 | \r | |
e0307a7d AB |
24 | #define EFI_MEMORY_CACHETYPE_MASK (EFI_MEMORY_UC | EFI_MEMORY_WC | \\r |
25 | EFI_MEMORY_WT | EFI_MEMORY_WB | \\r | |
26 | EFI_MEMORY_UCE)\r | |
27 | \r | |
1e57a462 | 28 | /**\r |
29 | * The UEFI firmware must not use the ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_* attributes.\r | |
30 | *\r | |
31 | * The Non Secure memory attribute (ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_*) should only\r | |
32 | * be used in Secure World to distinguished Secure to Non-Secure memory.\r | |
33 | */\r | |
34 | typedef enum {\r | |
35 | ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED = 0,\r | |
36 | ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_UNCACHED_UNBUFFERED,\r | |
37 | ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK,\r | |
38 | ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK,\r | |
829633e3 PL |
39 | \r |
40 | // On some platforms, memory mapped flash region is designed as not supporting\r | |
41 | // shareable attribute, so WRITE_BACK_NONSHAREABLE is added for such special\r | |
42 | // need.\r | |
43 | // Do NOT use below two attributes if you are not sure.\r | |
44 | ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK_NONSHAREABLE,\r | |
45 | ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK_NONSHAREABLE,\r | |
46 | \r | |
1e57a462 | 47 | ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH,\r |
48 | ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_THROUGH,\r | |
49 | ARM_MEMORY_REGION_ATTRIBUTE_DEVICE,\r | |
50 | ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_DEVICE\r | |
51 | } ARM_MEMORY_REGION_ATTRIBUTES;\r | |
52 | \r | |
53 | #define IS_ARM_MEMORY_REGION_ATTRIBUTES_SECURE(attr) ((UINT32)(attr) & 1)\r | |
54 | \r | |
55 | typedef struct {\r | |
56 | EFI_PHYSICAL_ADDRESS PhysicalBase;\r | |
57 | EFI_VIRTUAL_ADDRESS VirtualBase;\r | |
c357fd6a | 58 | UINT64 Length;\r |
1e57a462 | 59 | ARM_MEMORY_REGION_ATTRIBUTES Attributes;\r |
60 | } ARM_MEMORY_REGION_DESCRIPTOR;\r | |
61 | \r | |
62 | typedef VOID (*CACHE_OPERATION)(VOID);\r | |
63 | typedef VOID (*LINE_OPERATION)(UINTN);\r | |
64 | \r | |
65 | //\r | |
66 | // ARM Processor Mode\r | |
67 | //\r | |
68 | typedef enum {\r | |
69 | ARM_PROCESSOR_MODE_USER = 0x10,\r | |
70 | ARM_PROCESSOR_MODE_FIQ = 0x11,\r | |
71 | ARM_PROCESSOR_MODE_IRQ = 0x12,\r | |
72 | ARM_PROCESSOR_MODE_SUPERVISOR = 0x13,\r | |
73 | ARM_PROCESSOR_MODE_ABORT = 0x17,\r | |
74 | ARM_PROCESSOR_MODE_HYP = 0x1A,\r | |
75 | ARM_PROCESSOR_MODE_UNDEFINED = 0x1B,\r | |
76 | ARM_PROCESSOR_MODE_SYSTEM = 0x1F,\r | |
77 | ARM_PROCESSOR_MODE_MASK = 0x1F\r | |
78 | } ARM_PROCESSOR_MODE;\r | |
79 | \r | |
80 | //\r | |
81 | // ARM Cpu IDs\r | |
82 | //\r | |
83 | #define ARM_CPU_IMPLEMENTER_MASK (0xFFU << 24)\r | |
84 | #define ARM_CPU_IMPLEMENTER_ARMLTD (0x41U << 24)\r | |
85 | #define ARM_CPU_IMPLEMENTER_DEC (0x44U << 24)\r | |
86 | #define ARM_CPU_IMPLEMENTER_MOT (0x4DU << 24)\r | |
87 | #define ARM_CPU_IMPLEMENTER_QUALCOMM (0x51U << 24)\r | |
88 | #define ARM_CPU_IMPLEMENTER_MARVELL (0x56U << 24)\r | |
89 | \r | |
90 | #define ARM_CPU_PRIMARY_PART_MASK (0xFFF << 4)\r | |
91 | #define ARM_CPU_PRIMARY_PART_CORTEXA5 (0xC05 << 4)\r | |
92 | #define ARM_CPU_PRIMARY_PART_CORTEXA7 (0xC07 << 4)\r | |
93 | #define ARM_CPU_PRIMARY_PART_CORTEXA8 (0xC08 << 4)\r | |
94 | #define ARM_CPU_PRIMARY_PART_CORTEXA9 (0xC09 << 4)\r | |
95 | #define ARM_CPU_PRIMARY_PART_CORTEXA15 (0xC0F << 4)\r | |
96 | \r | |
97 | //\r | |
98 | // ARM MP Core IDs\r | |
99 | //\r | |
90ed18ca OM |
100 | #define ARM_CORE_AFF0 0xFF\r |
101 | #define ARM_CORE_AFF1 (0xFF << 8)\r | |
102 | #define ARM_CORE_AFF2 (0xFF << 16)\r | |
103 | #define ARM_CORE_AFF3 (0xFFULL << 32)\r | |
104 | \r | |
105 | #define ARM_CORE_MASK ARM_CORE_AFF0\r | |
106 | #define ARM_CLUSTER_MASK ARM_CORE_AFF1\r | |
1e57a462 | 107 | #define GET_CORE_ID(MpId) ((MpId) & ARM_CORE_MASK)\r |
108 | #define GET_CLUSTER_ID(MpId) (((MpId) & ARM_CLUSTER_MASK) >> 8)\r | |
e359565e | 109 | #define GET_MPID(ClusterId, CoreId) (((ClusterId) << 8) | (CoreId))\r |
1e57a462 | 110 | #define PRIMARY_CORE_ID (PcdGet32(PcdArmPrimaryCore) & ARM_CORE_MASK)\r |
111 | \r | |
4f92cfa4 RC |
112 | // The ARM Architecture Reference Manual for ARMv8-A defines up\r |
113 | // to 7 levels of cache, L1 through L7.\r | |
114 | #define MAX_ARM_CACHE_LEVEL 7\r | |
115 | \r | |
1e57a462 | 116 | UINTN\r |
117 | EFIAPI\r | |
118 | ArmDataCacheLineLength (\r | |
119 | VOID\r | |
120 | );\r | |
3402aac7 | 121 | \r |
1e57a462 | 122 | UINTN\r |
123 | EFIAPI\r | |
124 | ArmInstructionCacheLineLength (\r | |
125 | VOID\r | |
126 | );\r | |
168d7245 | 127 | \r |
c653fc2a AB |
128 | UINTN\r |
129 | EFIAPI\r | |
130 | ArmCacheWritebackGranule (\r | |
131 | VOID\r | |
132 | );\r | |
133 | \r | |
168d7245 OM |
134 | UINTN\r |
135 | EFIAPI\r | |
136 | ArmIsArchTimerImplemented (\r | |
137 | VOID\r | |
138 | );\r | |
139 | \r | |
64751727 | 140 | UINTN\r |
1e57a462 | 141 | EFIAPI\r |
64751727 | 142 | ArmCacheInfo (\r |
1e57a462 | 143 | VOID\r |
144 | );\r | |
145 | \r | |
146 | BOOLEAN\r | |
147 | EFIAPI\r | |
148 | ArmIsMpCore (\r | |
149 | VOID\r | |
150 | );\r | |
151 | \r | |
152 | VOID\r | |
153 | EFIAPI\r | |
154 | ArmInvalidateDataCache (\r | |
155 | VOID\r | |
156 | );\r | |
157 | \r | |
158 | \r | |
159 | VOID\r | |
160 | EFIAPI\r | |
161 | ArmCleanInvalidateDataCache (\r | |
162 | VOID\r | |
163 | );\r | |
164 | \r | |
165 | VOID\r | |
166 | EFIAPI\r | |
167 | ArmCleanDataCache (\r | |
168 | VOID\r | |
169 | );\r | |
170 | \r | |
1e57a462 | 171 | VOID\r |
172 | EFIAPI\r | |
173 | ArmInvalidateInstructionCache (\r | |
174 | VOID\r | |
175 | );\r | |
176 | \r | |
177 | VOID\r | |
178 | EFIAPI\r | |
179 | ArmInvalidateDataCacheEntryByMVA (\r | |
180 | IN UINTN Address\r | |
181 | );\r | |
182 | \r | |
183 | VOID\r | |
184 | EFIAPI\r | |
cf580da1 | 185 | ArmCleanDataCacheEntryToPoUByMVA (\r |
1e57a462 | 186 | IN UINTN Address\r |
187 | );\r | |
188 | \r | |
b7de7e3c EC |
189 | VOID\r |
190 | EFIAPI\r | |
cf580da1 AB |
191 | ArmInvalidateInstructionCacheEntryToPoUByMVA (\r |
192 | IN UINTN Address\r | |
193 | );\r | |
194 | \r | |
195 | VOID\r | |
196 | EFIAPI\r | |
197 | ArmCleanDataCacheEntryByMVA (\r | |
b7de7e3c EC |
198 | IN UINTN Address\r |
199 | );\r | |
200 | \r | |
1e57a462 | 201 | VOID\r |
202 | EFIAPI\r | |
203 | ArmCleanInvalidateDataCacheEntryByMVA (\r | |
204 | IN UINTN Address\r | |
205 | );\r | |
206 | \r | |
207 | VOID\r | |
208 | EFIAPI\r | |
209 | ArmEnableDataCache (\r | |
210 | VOID\r | |
211 | );\r | |
212 | \r | |
213 | VOID\r | |
214 | EFIAPI\r | |
215 | ArmDisableDataCache (\r | |
216 | VOID\r | |
217 | );\r | |
218 | \r | |
219 | VOID\r | |
220 | EFIAPI\r | |
221 | ArmEnableInstructionCache (\r | |
222 | VOID\r | |
223 | );\r | |
224 | \r | |
225 | VOID\r | |
226 | EFIAPI\r | |
227 | ArmDisableInstructionCache (\r | |
228 | VOID\r | |
229 | );\r | |
3402aac7 | 230 | \r |
1e57a462 | 231 | VOID\r |
232 | EFIAPI\r | |
233 | ArmEnableMmu (\r | |
234 | VOID\r | |
235 | );\r | |
236 | \r | |
237 | VOID\r | |
238 | EFIAPI\r | |
239 | ArmDisableMmu (\r | |
240 | VOID\r | |
241 | );\r | |
242 | \r | |
0ff0e414 OM |
243 | VOID\r |
244 | EFIAPI\r | |
245 | ArmEnableCachesAndMmu (\r | |
246 | VOID\r | |
247 | );\r | |
248 | \r | |
1e57a462 | 249 | VOID\r |
250 | EFIAPI\r | |
251 | ArmDisableCachesAndMmu (\r | |
252 | VOID\r | |
253 | );\r | |
254 | \r | |
1e57a462 | 255 | VOID\r |
256 | EFIAPI\r | |
257 | ArmEnableInterrupts (\r | |
258 | VOID\r | |
259 | );\r | |
260 | \r | |
261 | UINTN\r | |
262 | EFIAPI\r | |
263 | ArmDisableInterrupts (\r | |
264 | VOID\r | |
265 | );\r | |
47585ed5 | 266 | \r |
1e57a462 | 267 | BOOLEAN\r |
268 | EFIAPI\r | |
269 | ArmGetInterruptState (\r | |
270 | VOID\r | |
271 | );\r | |
272 | \r | |
0ff0e414 OM |
273 | VOID\r |
274 | EFIAPI\r | |
275 | ArmEnableAsynchronousAbort (\r | |
276 | VOID\r | |
277 | );\r | |
278 | \r | |
47585ed5 | 279 | UINTN\r |
280 | EFIAPI\r | |
0ff0e414 | 281 | ArmDisableAsynchronousAbort (\r |
47585ed5 | 282 | VOID\r |
283 | );\r | |
284 | \r | |
285 | VOID\r | |
286 | EFIAPI\r | |
287 | ArmEnableIrq (\r | |
288 | VOID\r | |
289 | );\r | |
290 | \r | |
0ff0e414 OM |
291 | UINTN\r |
292 | EFIAPI\r | |
293 | ArmDisableIrq (\r | |
294 | VOID\r | |
295 | );\r | |
296 | \r | |
1e57a462 | 297 | VOID\r |
298 | EFIAPI\r | |
299 | ArmEnableFiq (\r | |
300 | VOID\r | |
301 | );\r | |
302 | \r | |
303 | UINTN\r | |
304 | EFIAPI\r | |
305 | ArmDisableFiq (\r | |
306 | VOID\r | |
307 | );\r | |
3402aac7 | 308 | \r |
1e57a462 | 309 | BOOLEAN\r |
310 | EFIAPI\r | |
311 | ArmGetFiqState (\r | |
312 | VOID\r | |
313 | );\r | |
314 | \r | |
8dd618d2 OM |
315 | /**\r |
316 | * Invalidate Data and Instruction TLBs\r | |
317 | */\r | |
1e57a462 | 318 | VOID\r |
319 | EFIAPI\r | |
320 | ArmInvalidateTlb (\r | |
321 | VOID\r | |
322 | );\r | |
3402aac7 | 323 | \r |
1e57a462 | 324 | VOID\r |
325 | EFIAPI\r | |
326 | ArmUpdateTranslationTableEntry (\r | |
327 | IN VOID *TranslationTableEntry,\r | |
328 | IN VOID *Mva\r | |
329 | );\r | |
3402aac7 | 330 | \r |
1e57a462 | 331 | VOID\r |
332 | EFIAPI\r | |
333 | ArmSetDomainAccessControl (\r | |
334 | IN UINT32 Domain\r | |
335 | );\r | |
336 | \r | |
337 | VOID\r | |
338 | EFIAPI\r | |
339 | ArmSetTTBR0 (\r | |
340 | IN VOID *TranslationTableBase\r | |
341 | );\r | |
342 | \r | |
ff1f27c0 EL |
343 | VOID\r |
344 | EFIAPI\r | |
345 | ArmSetTTBCR (\r | |
346 | IN UINT32 Bits\r | |
347 | );\r | |
348 | \r | |
1e57a462 | 349 | VOID *\r |
350 | EFIAPI\r | |
351 | ArmGetTTBR0BaseAddress (\r | |
352 | VOID\r | |
353 | );\r | |
354 | \r | |
1e57a462 | 355 | BOOLEAN\r |
356 | EFIAPI\r | |
357 | ArmMmuEnabled (\r | |
358 | VOID\r | |
359 | );\r | |
3402aac7 | 360 | \r |
1e57a462 | 361 | VOID\r |
362 | EFIAPI\r | |
363 | ArmEnableBranchPrediction (\r | |
364 | VOID\r | |
365 | );\r | |
366 | \r | |
367 | VOID\r | |
368 | EFIAPI\r | |
369 | ArmDisableBranchPrediction (\r | |
370 | VOID\r | |
371 | );\r | |
372 | \r | |
373 | VOID\r | |
374 | EFIAPI\r | |
375 | ArmSetLowVectors (\r | |
376 | VOID\r | |
377 | );\r | |
378 | \r | |
379 | VOID\r | |
380 | EFIAPI\r | |
381 | ArmSetHighVectors (\r | |
382 | VOID\r | |
383 | );\r | |
384 | \r | |
385 | VOID\r | |
386 | EFIAPI\r | |
387 | ArmDataMemoryBarrier (\r | |
388 | VOID\r | |
389 | );\r | |
3402aac7 | 390 | \r |
1e57a462 | 391 | VOID\r |
392 | EFIAPI\r | |
cf93a378 | 393 | ArmDataSynchronizationBarrier (\r |
1e57a462 | 394 | VOID\r |
395 | );\r | |
3402aac7 | 396 | \r |
1e57a462 | 397 | VOID\r |
398 | EFIAPI\r | |
399 | ArmInstructionSynchronizationBarrier (\r | |
400 | VOID\r | |
401 | );\r | |
402 | \r | |
403 | VOID\r | |
404 | EFIAPI\r | |
405 | ArmWriteVBar (\r | |
4e57d6d7 | 406 | IN UINTN VectorBase\r |
1e57a462 | 407 | );\r |
408 | \r | |
4e57d6d7 | 409 | UINTN\r |
1e57a462 | 410 | EFIAPI\r |
411 | ArmReadVBar (\r | |
412 | VOID\r | |
413 | );\r | |
414 | \r | |
415 | VOID\r | |
416 | EFIAPI\r | |
417 | ArmWriteAuxCr (\r | |
418 | IN UINT32 Bit\r | |
419 | );\r | |
420 | \r | |
421 | UINT32\r | |
422 | EFIAPI\r | |
423 | ArmReadAuxCr (\r | |
424 | VOID\r | |
425 | );\r | |
426 | \r | |
427 | VOID\r | |
428 | EFIAPI\r | |
429 | ArmSetAuxCrBit (\r | |
430 | IN UINT32 Bits\r | |
431 | );\r | |
432 | \r | |
433 | VOID\r | |
434 | EFIAPI\r | |
435 | ArmUnsetAuxCrBit (\r | |
436 | IN UINT32 Bits\r | |
437 | );\r | |
438 | \r | |
439 | VOID\r | |
440 | EFIAPI\r | |
441 | ArmCallSEV (\r | |
442 | VOID\r | |
443 | );\r | |
444 | \r | |
445 | VOID\r | |
446 | EFIAPI\r | |
447 | ArmCallWFE (\r | |
448 | VOID\r | |
449 | );\r | |
450 | \r | |
451 | VOID\r | |
452 | EFIAPI\r | |
453 | ArmCallWFI (\r | |
25402f5d | 454 | \r |
1e57a462 | 455 | VOID\r |
456 | );\r | |
457 | \r | |
458 | UINTN\r | |
459 | EFIAPI\r | |
460 | ArmReadMpidr (\r | |
461 | VOID\r | |
462 | );\r | |
463 | \r | |
9401d6f4 OM |
464 | UINTN\r |
465 | EFIAPI\r | |
466 | ArmReadMidr (\r | |
467 | VOID\r | |
468 | );\r | |
469 | \r | |
1e57a462 | 470 | UINT32\r |
471 | EFIAPI\r | |
472 | ArmReadCpacr (\r | |
473 | VOID\r | |
474 | );\r | |
475 | \r | |
476 | VOID\r | |
477 | EFIAPI\r | |
478 | ArmWriteCpacr (\r | |
479 | IN UINT32 Access\r | |
480 | );\r | |
481 | \r | |
482 | VOID\r | |
483 | EFIAPI\r | |
484 | ArmEnableVFP (\r | |
485 | VOID\r | |
486 | );\r | |
487 | \r | |
46d4d75c OM |
488 | /**\r |
489 | Get the Secure Configuration Register value\r | |
490 | \r | |
491 | @return Value read from the Secure Configuration Register\r | |
492 | \r | |
493 | **/\r | |
1e57a462 | 494 | UINT32\r |
495 | EFIAPI\r | |
496 | ArmReadScr (\r | |
497 | VOID\r | |
498 | );\r | |
499 | \r | |
46d4d75c OM |
500 | /**\r |
501 | Set the Secure Configuration Register\r | |
502 | \r | |
503 | @param Value Value to write to the Secure Configuration Register\r | |
504 | \r | |
505 | **/\r | |
1e57a462 | 506 | VOID\r |
507 | EFIAPI\r | |
508 | ArmWriteScr (\r | |
46d4d75c | 509 | IN UINT32 Value\r |
1e57a462 | 510 | );\r |
511 | \r | |
512 | UINT32\r | |
513 | EFIAPI\r | |
514 | ArmReadMVBar (\r | |
515 | VOID\r | |
516 | );\r | |
517 | \r | |
518 | VOID\r | |
519 | EFIAPI\r | |
520 | ArmWriteMVBar (\r | |
521 | IN UINT32 VectorMonitorBase\r | |
522 | );\r | |
523 | \r | |
524 | UINT32\r | |
525 | EFIAPI\r | |
526 | ArmReadSctlr (\r | |
527 | VOID\r | |
528 | );\r | |
529 | \r | |
1e1d1697 MZ |
530 | VOID\r |
531 | EFIAPI\r | |
532 | ArmWriteSctlr (\r | |
533 | IN UINT32 Value\r | |
534 | );\r | |
535 | \r | |
5ea2c2d3 | 536 | UINTN\r |
537 | EFIAPI\r | |
538 | ArmReadHVBar (\r | |
539 | VOID\r | |
540 | );\r | |
541 | \r | |
542 | VOID\r | |
543 | EFIAPI\r | |
544 | ArmWriteHVBar (\r | |
545 | IN UINTN HypModeVectorBase\r | |
546 | );\r | |
547 | \r | |
52d44f77 OM |
548 | \r |
549 | //\r | |
550 | // Helper functions for accessing CPU ACTLR\r | |
551 | //\r | |
552 | \r | |
553 | UINTN\r | |
554 | EFIAPI\r | |
555 | ArmReadCpuActlr (\r | |
556 | VOID\r | |
557 | );\r | |
558 | \r | |
559 | VOID\r | |
560 | EFIAPI\r | |
561 | ArmWriteCpuActlr (\r | |
562 | IN UINTN Val\r | |
563 | );\r | |
564 | \r | |
565 | VOID\r | |
566 | EFIAPI\r | |
567 | ArmSetCpuActlrBit (\r | |
568 | IN UINTN Bits\r | |
569 | );\r | |
570 | \r | |
571 | VOID\r | |
572 | EFIAPI\r | |
573 | ArmUnsetCpuActlrBit (\r | |
574 | IN UINTN Bits\r | |
575 | );\r | |
576 | \r | |
734bd6cc AB |
577 | //\r |
578 | // Accessors for the architected generic timer registers\r | |
579 | //\r | |
580 | \r | |
581 | #define ARM_ARCH_TIMER_ENABLE (1 << 0)\r | |
582 | #define ARM_ARCH_TIMER_IMASK (1 << 1)\r | |
583 | #define ARM_ARCH_TIMER_ISTATUS (1 << 2)\r | |
584 | \r | |
585 | UINTN\r | |
586 | EFIAPI\r | |
587 | ArmReadCntFrq (\r | |
588 | VOID\r | |
589 | );\r | |
590 | \r | |
591 | VOID\r | |
592 | EFIAPI\r | |
593 | ArmWriteCntFrq (\r | |
594 | UINTN FreqInHz\r | |
595 | );\r | |
596 | \r | |
597 | UINT64\r | |
598 | EFIAPI\r | |
599 | ArmReadCntPct (\r | |
600 | VOID\r | |
601 | );\r | |
602 | \r | |
603 | UINTN\r | |
604 | EFIAPI\r | |
605 | ArmReadCntkCtl (\r | |
606 | VOID\r | |
607 | );\r | |
608 | \r | |
609 | VOID\r | |
610 | EFIAPI\r | |
611 | ArmWriteCntkCtl (\r | |
612 | UINTN Val\r | |
613 | );\r | |
614 | \r | |
615 | UINTN\r | |
616 | EFIAPI\r | |
617 | ArmReadCntpTval (\r | |
618 | VOID\r | |
619 | );\r | |
620 | \r | |
621 | VOID\r | |
622 | EFIAPI\r | |
623 | ArmWriteCntpTval (\r | |
624 | UINTN Val\r | |
625 | );\r | |
626 | \r | |
627 | UINTN\r | |
628 | EFIAPI\r | |
629 | ArmReadCntpCtl (\r | |
630 | VOID\r | |
631 | );\r | |
632 | \r | |
633 | VOID\r | |
634 | EFIAPI\r | |
635 | ArmWriteCntpCtl (\r | |
636 | UINTN Val\r | |
637 | );\r | |
638 | \r | |
639 | UINTN\r | |
640 | EFIAPI\r | |
641 | ArmReadCntvTval (\r | |
642 | VOID\r | |
643 | );\r | |
644 | \r | |
645 | VOID\r | |
646 | EFIAPI\r | |
647 | ArmWriteCntvTval (\r | |
648 | UINTN Val\r | |
649 | );\r | |
650 | \r | |
651 | UINTN\r | |
652 | EFIAPI\r | |
653 | ArmReadCntvCtl (\r | |
654 | VOID\r | |
655 | );\r | |
656 | \r | |
657 | VOID\r | |
658 | EFIAPI\r | |
659 | ArmWriteCntvCtl (\r | |
660 | UINTN Val\r | |
661 | );\r | |
662 | \r | |
663 | UINT64\r | |
664 | EFIAPI\r | |
665 | ArmReadCntvCt (\r | |
666 | VOID\r | |
667 | );\r | |
668 | \r | |
669 | UINT64\r | |
670 | EFIAPI\r | |
671 | ArmReadCntpCval (\r | |
672 | VOID\r | |
673 | );\r | |
674 | \r | |
675 | VOID\r | |
676 | EFIAPI\r | |
677 | ArmWriteCntpCval (\r | |
678 | UINT64 Val\r | |
679 | );\r | |
680 | \r | |
681 | UINT64\r | |
682 | EFIAPI\r | |
683 | ArmReadCntvCval (\r | |
684 | VOID\r | |
685 | );\r | |
686 | \r | |
687 | VOID\r | |
688 | EFIAPI\r | |
689 | ArmWriteCntvCval (\r | |
690 | UINT64 Val\r | |
691 | );\r | |
692 | \r | |
693 | UINT64\r | |
694 | EFIAPI\r | |
695 | ArmReadCntvOff (\r | |
696 | VOID\r | |
697 | );\r | |
698 | \r | |
699 | VOID\r | |
700 | EFIAPI\r | |
701 | ArmWriteCntvOff (\r | |
702 | UINT64 Val\r | |
703 | );\r | |
704 | \r | |
95d04ebc AB |
705 | UINTN\r |
706 | EFIAPI\r | |
707 | ArmGetPhysicalAddressBits (\r | |
708 | VOID\r | |
709 | );\r | |
710 | \r | |
5cc25cff LL |
711 | \r |
712 | ///\r | |
713 | /// ID Register Helper functions\r | |
714 | ///\r | |
715 | \r | |
716 | /**\r | |
717 | Check whether the CPU supports the GIC system register interface (any version)\r | |
718 | \r | |
719 | @return Whether GIC System Register Interface is supported\r | |
720 | \r | |
721 | **/\r | |
722 | BOOLEAN\r | |
723 | EFIAPI\r | |
724 | ArmHasGicSystemRegisters (\r | |
725 | VOID\r | |
726 | );\r | |
727 | \r | |
6e131aff RC |
728 | /** Checks if CCIDX is implemented.\r |
729 | \r | |
730 | @retval TRUE CCIDX is implemented.\r | |
731 | @retval FALSE CCIDX is not implemented.\r | |
732 | **/\r | |
733 | BOOLEAN\r | |
734 | EFIAPI\r | |
735 | ArmHasCcidx (\r | |
736 | VOID\r | |
737 | );\r | |
738 | \r | |
740b870d LL |
739 | #ifdef MDE_CPU_ARM\r |
740 | ///\r | |
741 | /// AArch32-only ID Register Helper functions\r | |
742 | ///\r | |
743 | /**\r | |
744 | Check whether the CPU supports the Security extensions\r | |
745 | \r | |
746 | @return Whether the Security extensions are implemented\r | |
747 | \r | |
748 | **/\r | |
749 | BOOLEAN\r | |
750 | EFIAPI\r | |
751 | ArmHasSecurityExtensions (\r | |
752 | VOID\r | |
753 | );\r | |
754 | #endif // MDE_CPU_ARM\r | |
755 | \r | |
1e57a462 | 756 | #endif // __ARM_LIB__\r |