[mirror_edk2.git] / ArmPkg / Include / Library / ArmLib.h

/** @file\r
\r
  Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
  Copyright (c) 2011 - 2016, ARM Ltd. All rights reserved.<BR>\r
  Copyright (c) 2020 - 2021, NUVIA Inc. All rights reserved.<BR>\r
\r
  SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
**/\r
\r
#ifndef ARM_LIB_H_\r
#define ARM_LIB_H_\r
\r
#include <Uefi/UefiBaseType.h>\r
\r
#ifdef MDE_CPU_ARM\r
  #include <Chipset/ArmV7.h>\r
#elif defined(MDE_CPU_AARCH64)\r
  #include <Chipset/AArch64.h>\r
#else\r
 #error "Unknown chipset."\r
#endif\r
\r
#define EFI_MEMORY_CACHETYPE_MASK   (EFI_MEMORY_UC | EFI_MEMORY_WC | \\r
                                     EFI_MEMORY_WT | EFI_MEMORY_WB | \\r
                                     EFI_MEMORY_UCE)\r
\r
/**\r
 * The UEFI firmware must not use the ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_* attributes.\r
 *\r
 * The Non Secure memory attribute (ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_*) should only\r
 * be used in Secure World to distinguished Secure to Non-Secure memory.\r
 */\r
typedef enum {\r
  ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED = 0,\r
  ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_UNCACHED_UNBUFFERED,\r
  ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK,\r
  ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK,\r
\r
  // On some platforms, memory mapped flash region is designed as not supporting\r
  // shareable attribute, so WRITE_BACK_NONSHAREABLE is added for such special\r
  // need.\r
  // Do NOT use below two attributes if you are not sure.\r
  ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK_NONSHAREABLE,\r
  ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK_NONSHAREABLE,\r
\r
  ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH,\r
  ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_THROUGH,\r
  ARM_MEMORY_REGION_ATTRIBUTE_DEVICE,\r
  ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_DEVICE\r
} ARM_MEMORY_REGION_ATTRIBUTES;\r
\r
#define IS_ARM_MEMORY_REGION_ATTRIBUTES_SECURE(attr) ((UINT32)(attr) & 1)\r
\r
typedef struct {\r
  EFI_PHYSICAL_ADDRESS          PhysicalBase;\r
  EFI_VIRTUAL_ADDRESS           VirtualBase;\r
  UINT64                        Length;\r
  ARM_MEMORY_REGION_ATTRIBUTES  Attributes;\r
} ARM_MEMORY_REGION_DESCRIPTOR;\r
\r
typedef VOID (*CACHE_OPERATION)(VOID);\r
typedef VOID (*LINE_OPERATION)(UINTN);\r
\r
//\r
// ARM Processor Mode\r
//\r
typedef enum {\r
  ARM_PROCESSOR_MODE_USER       = 0x10,\r
  ARM_PROCESSOR_MODE_FIQ        = 0x11,\r
  ARM_PROCESSOR_MODE_IRQ        = 0x12,\r
  ARM_PROCESSOR_MODE_SUPERVISOR = 0x13,\r
  ARM_PROCESSOR_MODE_ABORT      = 0x17,\r
  ARM_PROCESSOR_MODE_HYP        = 0x1A,\r
  ARM_PROCESSOR_MODE_UNDEFINED  = 0x1B,\r
  ARM_PROCESSOR_MODE_SYSTEM     = 0x1F,\r
  ARM_PROCESSOR_MODE_MASK       = 0x1F\r
} ARM_PROCESSOR_MODE;\r
\r
//\r
// ARM Cpu IDs\r
//\r
#define ARM_CPU_IMPLEMENTER_MASK          (0xFFU << 24)\r
#define ARM_CPU_IMPLEMENTER_ARMLTD        (0x41U << 24)\r
#define ARM_CPU_IMPLEMENTER_DEC           (0x44U << 24)\r
#define ARM_CPU_IMPLEMENTER_MOT           (0x4DU << 24)\r
#define ARM_CPU_IMPLEMENTER_QUALCOMM      (0x51U << 24)\r
#define ARM_CPU_IMPLEMENTER_MARVELL       (0x56U << 24)\r
\r
#define ARM_CPU_PRIMARY_PART_MASK         (0xFFF << 4)\r
#define ARM_CPU_PRIMARY_PART_CORTEXA5     (0xC05 << 4)\r
#define ARM_CPU_PRIMARY_PART_CORTEXA7     (0xC07 << 4)\r
#define ARM_CPU_PRIMARY_PART_CORTEXA8     (0xC08 << 4)\r
#define ARM_CPU_PRIMARY_PART_CORTEXA9     (0xC09 << 4)\r
#define ARM_CPU_PRIMARY_PART_CORTEXA15    (0xC0F << 4)\r
\r
//\r
// ARM MP Core IDs\r
//\r
#define ARM_CORE_AFF0         0xFF\r
#define ARM_CORE_AFF1         (0xFF << 8)\r
#define ARM_CORE_AFF2         (0xFF << 16)\r
#define ARM_CORE_AFF3         (0xFFULL << 32)\r
\r
#define ARM_CORE_MASK         ARM_CORE_AFF0\r
#define ARM_CLUSTER_MASK      ARM_CORE_AFF1\r
#define GET_CORE_ID(MpId)     ((MpId) & ARM_CORE_MASK)\r
#define GET_CLUSTER_ID(MpId)  (((MpId) & ARM_CLUSTER_MASK) >> 8)\r
#define GET_MPID(ClusterId, CoreId)   (((ClusterId) << 8) | (CoreId))\r
#define PRIMARY_CORE_ID       (PcdGet32(PcdArmPrimaryCore) & ARM_CORE_MASK)\r
\r
/** Reads the CCSIDR register for the specified cache.\r
\r
  @param CSSELR The CSSELR cache selection register value.\r
\r
  @return The contents of the CCSIDR_EL1 register for the specified cache, when in AARCH64 mode.\r
          Returns the contents of the CCSIDR register in AARCH32 mode.\r
**/\r
UINTN\r
ReadCCSIDR (\r
  IN UINT32 CSSELR\r
  );\r
\r
/** Reads the CCSIDR2 for the specified cache.\r
\r
  @param CSSELR The CSSELR cache selection register value\r
\r
  @return The contents of the CCSIDR2 register for the specified cache.\r
**/\r
UINT32\r
ReadCCSIDR2 (\r
  IN UINT32 CSSELR\r
  );\r
\r
/** Reads the Cache Level ID (CLIDR) register.\r
\r
  @return The contents of the CLIDR_EL1 register.\r
**/\r
UINT32\r
ReadCLIDR (\r
  VOID\r
  );\r
\r
UINTN\r
EFIAPI\r
ArmDataCacheLineLength (\r
  VOID\r
  );\r
\r
UINTN\r
EFIAPI\r
ArmInstructionCacheLineLength (\r
  VOID\r
  );\r
\r
UINTN\r
EFIAPI\r
ArmCacheWritebackGranule (\r
  VOID\r
  );\r
\r
UINTN\r
EFIAPI\r
ArmIsArchTimerImplemented (\r
  VOID\r
  );\r
\r
UINTN\r
EFIAPI\r
ArmCacheInfo (\r
  VOID\r
  );\r
\r
BOOLEAN\r
EFIAPI\r
ArmIsMpCore (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmInvalidateDataCache (\r
  VOID\r
  );\r
\r
\r
VOID\r
EFIAPI\r
ArmCleanInvalidateDataCache (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmCleanDataCache (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmInvalidateInstructionCache (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmInvalidateDataCacheEntryByMVA (\r
  IN  UINTN   Address\r
  );\r
\r
VOID\r
EFIAPI\r
ArmCleanDataCacheEntryToPoUByMVA (\r
  IN  UINTN   Address\r
  );\r
\r
VOID\r
EFIAPI\r
ArmInvalidateInstructionCacheEntryToPoUByMVA (\r
  IN  UINTN   Address\r
  );\r
\r
VOID\r
EFIAPI\r
ArmCleanDataCacheEntryByMVA (\r
IN  UINTN   Address\r
);\r
\r
VOID\r
EFIAPI\r
ArmCleanInvalidateDataCacheEntryByMVA (\r
  IN  UINTN   Address\r
  );\r
\r
VOID\r
EFIAPI\r
ArmEnableDataCache (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmDisableDataCache (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmEnableInstructionCache (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmDisableInstructionCache (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmEnableMmu (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmDisableMmu (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmEnableCachesAndMmu (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmDisableCachesAndMmu (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmEnableInterrupts (\r
  VOID\r
  );\r
\r
UINTN\r
EFIAPI\r
ArmDisableInterrupts (\r
  VOID\r
  );\r
\r
BOOLEAN\r
EFIAPI\r
ArmGetInterruptState (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmEnableAsynchronousAbort (\r
  VOID\r
  );\r
\r
UINTN\r
EFIAPI\r
ArmDisableAsynchronousAbort (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmEnableIrq (\r
  VOID\r
  );\r
\r
UINTN\r
EFIAPI\r
ArmDisableIrq (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmEnableFiq (\r
  VOID\r
  );\r
\r
UINTN\r
EFIAPI\r
ArmDisableFiq (\r
  VOID\r
  );\r
\r
BOOLEAN\r
EFIAPI\r
ArmGetFiqState (\r
  VOID\r
  );\r
\r
/**\r
 * Invalidate Data and Instruction TLBs\r
 */\r
VOID\r
EFIAPI\r
ArmInvalidateTlb (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmUpdateTranslationTableEntry (\r
  IN  VOID     *TranslationTableEntry,\r
  IN  VOID     *Mva\r
  );\r
\r
VOID\r
EFIAPI\r
ArmSetDomainAccessControl (\r
  IN  UINT32  Domain\r
  );\r
\r
VOID\r
EFIAPI\r
ArmSetTTBR0 (\r
  IN  VOID  *TranslationTableBase\r
  );\r
\r
VOID\r
EFIAPI\r
ArmSetTTBCR (\r
  IN  UINT32 Bits\r
  );\r
\r
VOID *\r
EFIAPI\r
ArmGetTTBR0BaseAddress (\r
  VOID\r
  );\r
\r
BOOLEAN\r
EFIAPI\r
ArmMmuEnabled (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmEnableBranchPrediction (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmDisableBranchPrediction (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmSetLowVectors (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmSetHighVectors (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmDataMemoryBarrier (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmDataSynchronizationBarrier (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmInstructionSynchronizationBarrier (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmWriteVBar (\r
  IN  UINTN   VectorBase\r
  );\r
\r
UINTN\r
EFIAPI\r
ArmReadVBar (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmWriteAuxCr (\r
  IN  UINT32    Bit\r
  );\r
\r
UINT32\r
EFIAPI\r
ArmReadAuxCr (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmSetAuxCrBit (\r
  IN  UINT32    Bits\r
  );\r
\r
VOID\r
EFIAPI\r
ArmUnsetAuxCrBit (\r
  IN  UINT32    Bits\r
  );\r
\r
VOID\r
EFIAPI\r
ArmCallSEV (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmCallWFE (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmCallWFI (\r
\r
  VOID\r
  );\r
\r
UINTN\r
EFIAPI\r
ArmReadMpidr (\r
  VOID\r
  );\r
\r
UINTN\r
EFIAPI\r
ArmReadMidr (\r
  VOID\r
  );\r
\r
UINT32\r
EFIAPI\r
ArmReadCpacr (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmWriteCpacr (\r
  IN  UINT32   Access\r
  );\r
\r
VOID\r
EFIAPI\r
ArmEnableVFP (\r
  VOID\r
  );\r
\r
/**\r
  Get the Secure Configuration Register value\r
\r
  @return   Value read from the Secure Configuration Register\r
\r
**/\r
UINT32\r
EFIAPI\r
ArmReadScr (\r
  VOID\r
  );\r
\r
/**\r
  Set the Secure Configuration Register\r
\r
  @param Value   Value to write to the Secure Configuration Register\r
\r
**/\r
VOID\r
EFIAPI\r
ArmWriteScr (\r
  IN  UINT32   Value\r
  );\r
\r
UINT32\r
EFIAPI\r
ArmReadMVBar (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmWriteMVBar (\r
  IN  UINT32   VectorMonitorBase\r
  );\r
\r
UINT32\r
EFIAPI\r
ArmReadSctlr (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmWriteSctlr (\r
  IN  UINT32   Value\r
  );\r
\r
UINTN\r
EFIAPI\r
ArmReadHVBar (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmWriteHVBar (\r
  IN  UINTN   HypModeVectorBase\r
  );\r
\r
\r
//\r
// Helper functions for accessing CPU ACTLR\r
//\r
\r
UINTN\r
EFIAPI\r
ArmReadCpuActlr (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmWriteCpuActlr (\r
  IN  UINTN Val\r
  );\r
\r
VOID\r
EFIAPI\r
ArmSetCpuActlrBit (\r
  IN  UINTN    Bits\r
  );\r
\r
VOID\r
EFIAPI\r
ArmUnsetCpuActlrBit (\r
  IN  UINTN    Bits\r
  );\r
\r
//\r
// Accessors for the architected generic timer registers\r
//\r
\r
#define ARM_ARCH_TIMER_ENABLE           (1 << 0)\r
#define ARM_ARCH_TIMER_IMASK            (1 << 1)\r
#define ARM_ARCH_TIMER_ISTATUS          (1 << 2)\r
\r
UINTN\r
EFIAPI\r
ArmReadCntFrq (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmWriteCntFrq (\r
  UINTN   FreqInHz\r
  );\r
\r
UINT64\r
EFIAPI\r
ArmReadCntPct (\r
  VOID\r
  );\r
\r
UINTN\r
EFIAPI\r
ArmReadCntkCtl (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmWriteCntkCtl (\r
  UINTN   Val\r
  );\r
\r
UINTN\r
EFIAPI\r
ArmReadCntpTval (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmWriteCntpTval (\r
  UINTN   Val\r
  );\r
\r
UINTN\r
EFIAPI\r
ArmReadCntpCtl (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmWriteCntpCtl (\r
  UINTN   Val\r
  );\r
\r
UINTN\r
EFIAPI\r
ArmReadCntvTval (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmWriteCntvTval (\r
  UINTN   Val\r
  );\r
\r
UINTN\r
EFIAPI\r
ArmReadCntvCtl (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmWriteCntvCtl (\r
  UINTN   Val\r
  );\r
\r
UINT64\r
EFIAPI\r
ArmReadCntvCt (\r
  VOID\r
  );\r
\r
UINT64\r
EFIAPI\r
ArmReadCntpCval (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmWriteCntpCval (\r
  UINT64   Val\r
  );\r
\r
UINT64\r
EFIAPI\r
ArmReadCntvCval (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmWriteCntvCval (\r
  UINT64   Val\r
  );\r
\r
UINT64\r
EFIAPI\r
ArmReadCntvOff (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmWriteCntvOff (\r
  UINT64   Val\r
  );\r
\r
UINTN\r
EFIAPI\r
ArmGetPhysicalAddressBits (\r
  VOID\r
  );\r
\r
\r
///\r
///  ID Register Helper functions\r
///\r
\r
/**\r
  Check whether the CPU supports the GIC system register interface (any version)\r
\r
  @return   Whether GIC System Register Interface is supported\r
\r
**/\r
BOOLEAN\r
EFIAPI\r
ArmHasGicSystemRegisters (\r
  VOID\r
  );\r
\r
/** Checks if CCIDX is implemented.\r
\r
   @retval TRUE  CCIDX is implemented.\r
   @retval FALSE CCIDX is not implemented.\r
**/\r
BOOLEAN\r
EFIAPI\r
ArmHasCcidx (\r
  VOID\r
  );\r
\r
#ifdef MDE_CPU_ARM\r
///\r
/// AArch32-only ID Register Helper functions\r
///\r
/**\r
  Check whether the CPU supports the Security extensions\r
\r
  @return   Whether the Security extensions are implemented\r
\r
**/\r
BOOLEAN\r
EFIAPI\r
ArmHasSecurityExtensions (\r
  VOID\r
  );\r
#endif // MDE_CPU_ARM\r
\r
#endif // ARM_LIB_H_\r
Commit	Line	Data
1e57a462	1	/** @file\r
	2	\r
	3	Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
ff1f27c0	4	Copyright (c) 2011 - 2016, ARM Ltd. All rights reserved.<BR>\r
a63914d3	5	Copyright (c) 2020 - 2021, NUVIA Inc. All rights reserved.<BR>\r
1e57a462	6	\r
4059386c	7	SPDX-License-Identifier: BSD-2-Clause-Patent\r
1e57a462	8	\r
	9	**/\r
	10	\r
cc15a619 PG	11	#ifndef ARM_LIB_H_\r
cc15a619 PG	12	#define ARM_LIB_H_\r
1e57a462	13	\r
	14	#include <Uefi/UefiBaseType.h>\r
	15	\r
25402f5d	16	#ifdef MDE_CPU_ARM\r
70119d27	17	#include <Chipset/ArmV7.h>\r
25402f5d HL	18	#elif defined(MDE_CPU_AARCH64)\r
25402f5d HL	19	#include <Chipset/AArch64.h>\r
1e57a462	20	#else\r
25402f5d	21	#error "Unknown chipset."\r
1e57a462	22	#endif\r
1e57a462	23	\r
e0307a7d AB	24	#define EFI_MEMORY_CACHETYPE_MASK (EFI_MEMORY_UC \| EFI_MEMORY_WC \| \\r
	25	EFI_MEMORY_WT \| EFI_MEMORY_WB \| \\r
	26	EFI_MEMORY_UCE)\r
	27	\r
1e57a462	28	/**\r
	29	* The UEFI firmware must not use the ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_* attributes.\r
	30	*\r
	31	* The Non Secure memory attribute (ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_*) should only\r
	32	* be used in Secure World to distinguished Secure to Non-Secure memory.\r
	33	*/\r
	34	typedef enum {\r
	35	ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED = 0,\r
	36	ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_UNCACHED_UNBUFFERED,\r
	37	ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK,\r
	38	ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK,\r
829633e3 PL	39	\r
	40	// On some platforms, memory mapped flash region is designed as not supporting\r
	41	// shareable attribute, so WRITE_BACK_NONSHAREABLE is added for such special\r
	42	// need.\r
	43	// Do NOT use below two attributes if you are not sure.\r
	44	ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK_NONSHAREABLE,\r
	45	ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK_NONSHAREABLE,\r
	46	\r
1e57a462	47	ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH,\r
	48	ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_THROUGH,\r
	49	ARM_MEMORY_REGION_ATTRIBUTE_DEVICE,\r
	50	ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_DEVICE\r
	51	} ARM_MEMORY_REGION_ATTRIBUTES;\r
	52	\r
	53	#define IS_ARM_MEMORY_REGION_ATTRIBUTES_SECURE(attr) ((UINT32)(attr) & 1)\r
	54	\r
	55	typedef struct {\r
	56	EFI_PHYSICAL_ADDRESS PhysicalBase;\r
	57	EFI_VIRTUAL_ADDRESS VirtualBase;\r
c357fd6a	58	UINT64 Length;\r
1e57a462	59	ARM_MEMORY_REGION_ATTRIBUTES Attributes;\r
	60	} ARM_MEMORY_REGION_DESCRIPTOR;\r
	61	\r
	62	typedef VOID (*CACHE_OPERATION)(VOID);\r
	63	typedef VOID (*LINE_OPERATION)(UINTN);\r
	64	\r
	65	//\r
	66	// ARM Processor Mode\r
	67	//\r
	68	typedef enum {\r
	69	ARM_PROCESSOR_MODE_USER = 0x10,\r
	70	ARM_PROCESSOR_MODE_FIQ = 0x11,\r
	71	ARM_PROCESSOR_MODE_IRQ = 0x12,\r
	72	ARM_PROCESSOR_MODE_SUPERVISOR = 0x13,\r
	73	ARM_PROCESSOR_MODE_ABORT = 0x17,\r
	74	ARM_PROCESSOR_MODE_HYP = 0x1A,\r
	75	ARM_PROCESSOR_MODE_UNDEFINED = 0x1B,\r
	76	ARM_PROCESSOR_MODE_SYSTEM = 0x1F,\r
	77	ARM_PROCESSOR_MODE_MASK = 0x1F\r
	78	} ARM_PROCESSOR_MODE;\r
	79	\r
	80	//\r
	81	// ARM Cpu IDs\r
	82	//\r
	83	#define ARM_CPU_IMPLEMENTER_MASK (0xFFU << 24)\r
	84	#define ARM_CPU_IMPLEMENTER_ARMLTD (0x41U << 24)\r
	85	#define ARM_CPU_IMPLEMENTER_DEC (0x44U << 24)\r
	86	#define ARM_CPU_IMPLEMENTER_MOT (0x4DU << 24)\r
	87	#define ARM_CPU_IMPLEMENTER_QUALCOMM (0x51U << 24)\r
	88	#define ARM_CPU_IMPLEMENTER_MARVELL (0x56U << 24)\r
	89	\r
	90	#define ARM_CPU_PRIMARY_PART_MASK (0xFFF << 4)\r
	91	#define ARM_CPU_PRIMARY_PART_CORTEXA5 (0xC05 << 4)\r
	92	#define ARM_CPU_PRIMARY_PART_CORTEXA7 (0xC07 << 4)\r
	93	#define ARM_CPU_PRIMARY_PART_CORTEXA8 (0xC08 << 4)\r
	94	#define ARM_CPU_PRIMARY_PART_CORTEXA9 (0xC09 << 4)\r
	95	#define ARM_CPU_PRIMARY_PART_CORTEXA15 (0xC0F << 4)\r
	96	\r
	97	//\r
	98	// ARM MP Core IDs\r
	99	//\r
90ed18ca OM	100	#define ARM_CORE_AFF0 0xFF\r
	101	#define ARM_CORE_AFF1 (0xFF << 8)\r
	102	#define ARM_CORE_AFF2 (0xFF << 16)\r
	103	#define ARM_CORE_AFF3 (0xFFULL << 32)\r
	104	\r
	105	#define ARM_CORE_MASK ARM_CORE_AFF0\r
	106	#define ARM_CLUSTER_MASK ARM_CORE_AFF1\r
1e57a462	107	#define GET_CORE_ID(MpId) ((MpId) & ARM_CORE_MASK)\r
1e57a462	108	#define GET_CLUSTER_ID(MpId) (((MpId) & ARM_CLUSTER_MASK) >> 8)\r
e359565e	109	#define GET_MPID(ClusterId, CoreId) (((ClusterId) << 8) \| (CoreId))\r
1e57a462	110	#define PRIMARY_CORE_ID (PcdGet32(PcdArmPrimaryCore) & ARM_CORE_MASK)\r
1e57a462	111	\r
a63914d3 RC	112	/** Reads the CCSIDR register for the specified cache.\r
	113	\r
	114	@param CSSELR The CSSELR cache selection register value.\r
	115	\r
	116	@return The contents of the CCSIDR_EL1 register for the specified cache, when in AARCH64 mode.\r
	117	Returns the contents of the CCSIDR register in AARCH32 mode.\r
	118	**/\r
	119	UINTN\r
	120	ReadCCSIDR (\r
	121	IN UINT32 CSSELR\r
	122	);\r
	123	\r
	124	/** Reads the CCSIDR2 for the specified cache.\r
	125	\r
	126	@param CSSELR The CSSELR cache selection register value\r
	127	\r
	128	@return The contents of the CCSIDR2 register for the specified cache.\r
	129	**/\r
	130	UINT32\r
	131	ReadCCSIDR2 (\r
	132	IN UINT32 CSSELR\r
	133	);\r
	134	\r
	135	/** Reads the Cache Level ID (CLIDR) register.\r
	136	\r
	137	@return The contents of the CLIDR_EL1 register.\r
	138	**/\r
	139	UINT32\r
	140	ReadCLIDR (\r
	141	VOID\r
	142	);\r
4f92cfa4	143	\r
1e57a462	144	UINTN\r
	145	EFIAPI\r
	146	ArmDataCacheLineLength (\r
	147	VOID\r
	148	);\r
3402aac7	149	\r
1e57a462	150	UINTN\r
	151	EFIAPI\r
	152	ArmInstructionCacheLineLength (\r
	153	VOID\r
	154	);\r
168d7245	155	\r
c653fc2a AB	156	UINTN\r
	157	EFIAPI\r
	158	ArmCacheWritebackGranule (\r
	159	VOID\r
	160	);\r
	161	\r
168d7245 OM	162	UINTN\r
	163	EFIAPI\r
	164	ArmIsArchTimerImplemented (\r
	165	VOID\r
	166	);\r
	167	\r
64751727	168	UINTN\r
1e57a462	169	EFIAPI\r
64751727	170	ArmCacheInfo (\r
1e57a462	171	VOID\r
	172	);\r
	173	\r
	174	BOOLEAN\r
	175	EFIAPI\r
	176	ArmIsMpCore (\r
	177	VOID\r
	178	);\r
	179	\r
	180	VOID\r
	181	EFIAPI\r
	182	ArmInvalidateDataCache (\r
	183	VOID\r
	184	);\r
	185	\r
	186	\r
	187	VOID\r
	188	EFIAPI\r
	189	ArmCleanInvalidateDataCache (\r
	190	VOID\r
	191	);\r
	192	\r
	193	VOID\r
	194	EFIAPI\r
	195	ArmCleanDataCache (\r
	196	VOID\r
	197	);\r
	198	\r
1e57a462	199	VOID\r
	200	EFIAPI\r
	201	ArmInvalidateInstructionCache (\r
	202	VOID\r
	203	);\r
	204	\r
	205	VOID\r
	206	EFIAPI\r
	207	ArmInvalidateDataCacheEntryByMVA (\r
	208	IN UINTN Address\r
	209	);\r
	210	\r
	211	VOID\r
	212	EFIAPI\r
cf580da1	213	ArmCleanDataCacheEntryToPoUByMVA (\r
1e57a462	214	IN UINTN Address\r
	215	);\r
	216	\r
b7de7e3c EC	217	VOID\r
b7de7e3c EC	218	EFIAPI\r
cf580da1 AB	219	ArmInvalidateInstructionCacheEntryToPoUByMVA (\r
	220	IN UINTN Address\r
	221	);\r
	222	\r
	223	VOID\r
	224	EFIAPI\r
	225	ArmCleanDataCacheEntryByMVA (\r
b7de7e3c EC	226	IN UINTN Address\r
	227	);\r
	228	\r
1e57a462	229	VOID\r
	230	EFIAPI\r
	231	ArmCleanInvalidateDataCacheEntryByMVA (\r
	232	IN UINTN Address\r
	233	);\r
	234	\r
	235	VOID\r
	236	EFIAPI\r
	237	ArmEnableDataCache (\r
	238	VOID\r
	239	);\r
	240	\r
	241	VOID\r
	242	EFIAPI\r
	243	ArmDisableDataCache (\r
	244	VOID\r
	245	);\r
	246	\r
	247	VOID\r
	248	EFIAPI\r
	249	ArmEnableInstructionCache (\r
	250	VOID\r
	251	);\r
	252	\r
	253	VOID\r
	254	EFIAPI\r
	255	ArmDisableInstructionCache (\r
	256	VOID\r
	257	);\r
3402aac7	258	\r
1e57a462	259	VOID\r
	260	EFIAPI\r
	261	ArmEnableMmu (\r
	262	VOID\r
	263	);\r
	264	\r
	265	VOID\r
	266	EFIAPI\r
	267	ArmDisableMmu (\r
	268	VOID\r
	269	);\r
	270	\r
0ff0e414 OM	271	VOID\r
	272	EFIAPI\r
	273	ArmEnableCachesAndMmu (\r
	274	VOID\r
	275	);\r
	276	\r
1e57a462	277	VOID\r
	278	EFIAPI\r
	279	ArmDisableCachesAndMmu (\r
	280	VOID\r
	281	);\r
	282	\r
1e57a462	283	VOID\r
	284	EFIAPI\r
	285	ArmEnableInterrupts (\r
	286	VOID\r
	287	);\r
	288	\r
	289	UINTN\r
	290	EFIAPI\r
	291	ArmDisableInterrupts (\r
	292	VOID\r
	293	);\r
47585ed5	294	\r
1e57a462	295	BOOLEAN\r
	296	EFIAPI\r
	297	ArmGetInterruptState (\r
	298	VOID\r
	299	);\r
	300	\r
0ff0e414 OM	301	VOID\r
	302	EFIAPI\r
	303	ArmEnableAsynchronousAbort (\r
	304	VOID\r
	305	);\r
	306	\r
47585ed5	307	UINTN\r
47585ed5	308	EFIAPI\r
0ff0e414	309	ArmDisableAsynchronousAbort (\r
47585ed5	310	VOID\r
	311	);\r
	312	\r
	313	VOID\r
	314	EFIAPI\r
	315	ArmEnableIrq (\r
	316	VOID\r
	317	);\r
	318	\r
0ff0e414 OM	319	UINTN\r
	320	EFIAPI\r
	321	ArmDisableIrq (\r
	322	VOID\r
	323	);\r
	324	\r
1e57a462	325	VOID\r
	326	EFIAPI\r
	327	ArmEnableFiq (\r
	328	VOID\r
	329	);\r
	330	\r
	331	UINTN\r
	332	EFIAPI\r
	333	ArmDisableFiq (\r
	334	VOID\r
	335	);\r
3402aac7	336	\r
1e57a462	337	BOOLEAN\r
	338	EFIAPI\r
	339	ArmGetFiqState (\r
	340	VOID\r
	341	);\r
	342	\r
8dd618d2 OM	343	/**\r
	344	* Invalidate Data and Instruction TLBs\r
	345	*/\r
1e57a462	346	VOID\r
	347	EFIAPI\r
	348	ArmInvalidateTlb (\r
	349	VOID\r
	350	);\r
3402aac7	351	\r
1e57a462	352	VOID\r
	353	EFIAPI\r
	354	ArmUpdateTranslationTableEntry (\r
	355	IN VOID *TranslationTableEntry,\r
	356	IN VOID *Mva\r
	357	);\r
3402aac7	358	\r
1e57a462	359	VOID\r
	360	EFIAPI\r
	361	ArmSetDomainAccessControl (\r
	362	IN UINT32 Domain\r
	363	);\r
	364	\r
	365	VOID\r
	366	EFIAPI\r
	367	ArmSetTTBR0 (\r
	368	IN VOID *TranslationTableBase\r
	369	);\r
	370	\r
ff1f27c0 EL	371	VOID\r
	372	EFIAPI\r
	373	ArmSetTTBCR (\r
	374	IN UINT32 Bits\r
	375	);\r
	376	\r
1e57a462	377	VOID *\r
	378	EFIAPI\r
	379	ArmGetTTBR0BaseAddress (\r
	380	VOID\r
	381	);\r
	382	\r
1e57a462	383	BOOLEAN\r
	384	EFIAPI\r
	385	ArmMmuEnabled (\r
	386	VOID\r
	387	);\r
3402aac7	388	\r
1e57a462	389	VOID\r
	390	EFIAPI\r
	391	ArmEnableBranchPrediction (\r
	392	VOID\r
	393	);\r
	394	\r
	395	VOID\r
	396	EFIAPI\r
	397	ArmDisableBranchPrediction (\r
	398	VOID\r
	399	);\r
	400	\r
	401	VOID\r
	402	EFIAPI\r
	403	ArmSetLowVectors (\r
	404	VOID\r
	405	);\r
	406	\r
	407	VOID\r
	408	EFIAPI\r
	409	ArmSetHighVectors (\r
	410	VOID\r
	411	);\r
	412	\r
	413	VOID\r
	414	EFIAPI\r
	415	ArmDataMemoryBarrier (\r
	416	VOID\r
	417	);\r
3402aac7	418	\r
1e57a462	419	VOID\r
1e57a462	420	EFIAPI\r
cf93a378	421	ArmDataSynchronizationBarrier (\r
1e57a462	422	VOID\r
1e57a462	423	);\r
3402aac7	424	\r
1e57a462	425	VOID\r
	426	EFIAPI\r
	427	ArmInstructionSynchronizationBarrier (\r
	428	VOID\r
	429	);\r
	430	\r
	431	VOID\r
	432	EFIAPI\r
	433	ArmWriteVBar (\r
4e57d6d7	434	IN UINTN VectorBase\r
1e57a462	435	);\r
1e57a462	436	\r
4e57d6d7	437	UINTN\r
1e57a462	438	EFIAPI\r
	439	ArmReadVBar (\r
	440	VOID\r
	441	);\r
	442	\r
	443	VOID\r
	444	EFIAPI\r
	445	ArmWriteAuxCr (\r
	446	IN UINT32 Bit\r
	447	);\r
	448	\r
	449	UINT32\r
	450	EFIAPI\r
	451	ArmReadAuxCr (\r
	452	VOID\r
	453	);\r
	454	\r
	455	VOID\r
	456	EFIAPI\r
	457	ArmSetAuxCrBit (\r
	458	IN UINT32 Bits\r
	459	);\r
	460	\r
	461	VOID\r
	462	EFIAPI\r
	463	ArmUnsetAuxCrBit (\r
	464	IN UINT32 Bits\r
	465	);\r
	466	\r
	467	VOID\r
	468	EFIAPI\r
	469	ArmCallSEV (\r
	470	VOID\r
	471	);\r
	472	\r
	473	VOID\r
	474	EFIAPI\r
	475	ArmCallWFE (\r
	476	VOID\r
	477	);\r
	478	\r
	479	VOID\r
	480	EFIAPI\r
	481	ArmCallWFI (\r
25402f5d	482	\r
1e57a462	483	VOID\r
	484	);\r
	485	\r
	486	UINTN\r
	487	EFIAPI\r
	488	ArmReadMpidr (\r
	489	VOID\r
	490	);\r
	491	\r
9401d6f4 OM	492	UINTN\r
	493	EFIAPI\r
	494	ArmReadMidr (\r
	495	VOID\r
	496	);\r
	497	\r
1e57a462	498	UINT32\r
	499	EFIAPI\r
	500	ArmReadCpacr (\r
	501	VOID\r
	502	);\r
	503	\r
	504	VOID\r
	505	EFIAPI\r
	506	ArmWriteCpacr (\r
	507	IN UINT32 Access\r
	508	);\r
	509	\r
	510	VOID\r
	511	EFIAPI\r
	512	ArmEnableVFP (\r
	513	VOID\r
	514	);\r
	515	\r
46d4d75c OM	516	/**\r
	517	Get the Secure Configuration Register value\r
	518	\r
	519	@return Value read from the Secure Configuration Register\r
	520	\r
	521	**/\r
1e57a462	522	UINT32\r
	523	EFIAPI\r
	524	ArmReadScr (\r
	525	VOID\r
	526	);\r
	527	\r
46d4d75c OM	528	/**\r
	529	Set the Secure Configuration Register\r
	530	\r
	531	@param Value Value to write to the Secure Configuration Register\r
	532	\r
	533	**/\r
1e57a462	534	VOID\r
	535	EFIAPI\r
	536	ArmWriteScr (\r
46d4d75c	537	IN UINT32 Value\r
1e57a462	538	);\r
	539	\r
	540	UINT32\r
	541	EFIAPI\r
	542	ArmReadMVBar (\r
	543	VOID\r
	544	);\r
	545	\r
	546	VOID\r
	547	EFIAPI\r
	548	ArmWriteMVBar (\r
	549	IN UINT32 VectorMonitorBase\r
	550	);\r
	551	\r
	552	UINT32\r
	553	EFIAPI\r
	554	ArmReadSctlr (\r
	555	VOID\r
	556	);\r
	557	\r
1e1d1697 MZ	558	VOID\r
	559	EFIAPI\r
	560	ArmWriteSctlr (\r
	561	IN UINT32 Value\r
	562	);\r
	563	\r
5ea2c2d3	564	UINTN\r
	565	EFIAPI\r
	566	ArmReadHVBar (\r
	567	VOID\r
	568	);\r
	569	\r
	570	VOID\r
	571	EFIAPI\r
	572	ArmWriteHVBar (\r
	573	IN UINTN HypModeVectorBase\r
	574	);\r
	575	\r
52d44f77 OM	576	\r
	577	//\r
	578	// Helper functions for accessing CPU ACTLR\r
	579	//\r
	580	\r
	581	UINTN\r
	582	EFIAPI\r
	583	ArmReadCpuActlr (\r
	584	VOID\r
	585	);\r
	586	\r
	587	VOID\r
	588	EFIAPI\r
	589	ArmWriteCpuActlr (\r
	590	IN UINTN Val\r
	591	);\r
	592	\r
	593	VOID\r
	594	EFIAPI\r
	595	ArmSetCpuActlrBit (\r
	596	IN UINTN Bits\r
	597	);\r
	598	\r
	599	VOID\r
	600	EFIAPI\r
	601	ArmUnsetCpuActlrBit (\r
	602	IN UINTN Bits\r
	603	);\r
	604	\r
734bd6cc AB	605	//\r
	606	// Accessors for the architected generic timer registers\r
	607	//\r
	608	\r
	609	#define ARM_ARCH_TIMER_ENABLE (1 << 0)\r
	610	#define ARM_ARCH_TIMER_IMASK (1 << 1)\r
	611	#define ARM_ARCH_TIMER_ISTATUS (1 << 2)\r
	612	\r
	613	UINTN\r
	614	EFIAPI\r
	615	ArmReadCntFrq (\r
	616	VOID\r
	617	);\r
	618	\r
	619	VOID\r
	620	EFIAPI\r
	621	ArmWriteCntFrq (\r
	622	UINTN FreqInHz\r
	623	);\r
	624	\r
	625	UINT64\r
	626	EFIAPI\r
	627	ArmReadCntPct (\r
	628	VOID\r
	629	);\r
	630	\r
	631	UINTN\r
	632	EFIAPI\r
	633	ArmReadCntkCtl (\r
	634	VOID\r
	635	);\r
	636	\r
	637	VOID\r
	638	EFIAPI\r
	639	ArmWriteCntkCtl (\r
	640	UINTN Val\r
	641	);\r
	642	\r
	643	UINTN\r
	644	EFIAPI\r
	645	ArmReadCntpTval (\r
	646	VOID\r
	647	);\r
	648	\r
	649	VOID\r
	650	EFIAPI\r
	651	ArmWriteCntpTval (\r
	652	UINTN Val\r
	653	);\r
	654	\r
	655	UINTN\r
	656	EFIAPI\r
	657	ArmReadCntpCtl (\r
	658	VOID\r
	659	);\r
	660	\r
	661	VOID\r
	662	EFIAPI\r
	663	ArmWriteCntpCtl (\r
	664	UINTN Val\r
	665	);\r
	666	\r
	667	UINTN\r
	668	EFIAPI\r
669	ArmReadCntvTval (\r
670	VOID\r
671	);\r
672	\r
673	VOID\r
674	EFIAPI\r
675	ArmWriteCntvTval (\r
676	UINTN Val\r
677	);\r
678	\r
679	UINTN\r
680	EFIAPI\r
681	ArmReadCntvCtl (\r
682	VOID\r
683	);\r
684	\r
685	VOID\r
686	EFIAPI\r
687	ArmWriteCntvCtl (\r
688	UINTN Val\r
689	);\r
690	\r
691	UINT64\r
692	EFIAPI\r
693	ArmReadCntvCt (\r
694	VOID\r
695	);\r
696	\r
697	UINT64\r
698	EFIAPI\r
699	ArmReadCntpCval (\r
700	VOID\r
701	);\r
702	\r
703	VOID\r
704	EFIAPI\r
705	ArmWriteCntpCval (\r
706	UINT64 Val\r
707	);\r
708	\r
709	UINT64\r
710	EFIAPI\r
711	ArmReadCntvCval (\r
712	VOID\r
713	);\r
714	\r
715	VOID\r
716	EFIAPI\r
717	ArmWriteCntvCval (\r
718	UINT64 Val\r
719	);\r
720	\r
721	UINT64\r
722	EFIAPI\r
723	ArmReadCntvOff (\r
724	VOID\r
725	);\r
726	\r
727	VOID\r
728	EFIAPI\r
729	ArmWriteCntvOff (\r
730	UINT64 Val\r
731	);\r
732	\r
95d04ebc AB	733	UINTN\r
	734	EFIAPI\r
	735	ArmGetPhysicalAddressBits (\r
	736	VOID\r
	737	);\r
	738	\r
5cc25cff LL	739	\r
	740	///\r
	741	/// ID Register Helper functions\r
	742	///\r
	743	\r
	744	/**\r
	745	Check whether the CPU supports the GIC system register interface (any version)\r
	746	\r
	747	@return Whether GIC System Register Interface is supported\r
	748	\r
	749	**/\r
	750	BOOLEAN\r
	751	EFIAPI\r
	752	ArmHasGicSystemRegisters (\r
	753	VOID\r
	754	);\r
	755	\r
6e131aff RC	756	/** Checks if CCIDX is implemented.\r
	757	\r
	758	@retval TRUE CCIDX is implemented.\r
	759	@retval FALSE CCIDX is not implemented.\r
	760	**/\r
	761	BOOLEAN\r
	762	EFIAPI\r
	763	ArmHasCcidx (\r
	764	VOID\r
	765	);\r
	766	\r
740b870d LL	767	#ifdef MDE_CPU_ARM\r
	768	///\r
	769	/// AArch32-only ID Register Helper functions\r
	770	///\r
	771	/**\r
	772	Check whether the CPU supports the Security extensions\r
	773	\r
	774	@return Whether the Security extensions are implemented\r
	775	\r
	776	**/\r
	777	BOOLEAN\r
	778	EFIAPI\r
	779	ArmHasSecurityExtensions (\r
	780	VOID\r
	781	);\r
	782	#endif // MDE_CPU_ARM\r
	783	\r
cc15a619	784	#endif // ARM_LIB_H_\r