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ArmPkg/ArmPkg.dec: Redefined PcdSystemMemory(Base|Size) as UINT64
[mirror_edk2.git] / ArmPkg / Include / Library / ArmLib.h
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1e57a462 1/** @file\r
2\r
3 Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
4 Copyright (c) 2011 - 2012, ARM Ltd. All rights reserved.<BR>\r
5\r
6 This program and the accompanying materials\r
7 are licensed and made available under the terms and conditions of the BSD License\r
8 which accompanies this distribution. The full text of the license may be found at\r
9 http://opensource.org/licenses/bsd-license.php\r
10\r
11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
12 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
13\r
14**/\r
15\r
16#ifndef __ARM_LIB__\r
17#define __ARM_LIB__\r
18\r
19#include <Uefi/UefiBaseType.h>\r
20\r
25402f5d
HL		 21#ifdef MDE_CPU_ARM\r
22 #ifdef ARM_CPU_ARMv6\r
23 #include <Chipset/ARM1176JZ-S.h>\r
24 #else\r
25 #include <Chipset/ArmV7.h>\r
26 #endif\r
27#elif defined(MDE_CPU_AARCH64)\r
28 #include <Chipset/AArch64.h>\r
1e57a462 29#else\r
25402f5d 30 #error "Unknown chipset."\r
1e57a462 31#endif\r
32\r
33typedef enum {\r
34 ARM_CACHE_TYPE_WRITE_BACK,\r
35 ARM_CACHE_TYPE_UNKNOWN\r
36} ARM_CACHE_TYPE;\r
37\r
38typedef enum {\r
39 ARM_CACHE_ARCHITECTURE_UNIFIED,\r
40 ARM_CACHE_ARCHITECTURE_SEPARATE,\r
41 ARM_CACHE_ARCHITECTURE_UNKNOWN\r
42} ARM_CACHE_ARCHITECTURE;\r
43\r
44typedef struct {\r
45 ARM_CACHE_TYPE Type;\r
46 ARM_CACHE_ARCHITECTURE Architecture;\r
47 BOOLEAN DataCachePresent;\r
48 UINTN DataCacheSize;\r
49 UINTN DataCacheAssociativity;\r
50 UINTN DataCacheLineLength;\r
51 BOOLEAN InstructionCachePresent;\r
52 UINTN InstructionCacheSize;\r
53 UINTN InstructionCacheAssociativity;\r
54 UINTN InstructionCacheLineLength;\r
55} ARM_CACHE_INFO;\r
56\r
57/**\r
58 * The UEFI firmware must not use the ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_* attributes.\r
59 *\r
60 * The Non Secure memory attribute (ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_*) should only\r
61 * be used in Secure World to distinguished Secure to Non-Secure memory.\r
62 */\r
63typedef enum {\r
64 ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED = 0,\r
65 ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_UNCACHED_UNBUFFERED,\r
66 ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK,\r
67 ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK,\r
68 ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH,\r
69 ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_THROUGH,\r
70 ARM_MEMORY_REGION_ATTRIBUTE_DEVICE,\r
71 ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_DEVICE\r
72} ARM_MEMORY_REGION_ATTRIBUTES;\r
73\r
74#define IS_ARM_MEMORY_REGION_ATTRIBUTES_SECURE(attr) ((UINT32)(attr) & 1)\r
75\r
76typedef struct {\r
77 EFI_PHYSICAL_ADDRESS PhysicalBase;\r
78 EFI_VIRTUAL_ADDRESS VirtualBase;\r
c357fd6a 79 UINT64 Length;\r
1e57a462 80 ARM_MEMORY_REGION_ATTRIBUTES Attributes;\r
81} ARM_MEMORY_REGION_DESCRIPTOR;\r
82\r
83typedef VOID (*CACHE_OPERATION)(VOID);\r
84typedef VOID (*LINE_OPERATION)(UINTN);\r
85\r
86//\r
87// ARM Processor Mode\r
88//\r
89typedef enum {\r
90 ARM_PROCESSOR_MODE_USER = 0x10,\r
91 ARM_PROCESSOR_MODE_FIQ = 0x11,\r
92 ARM_PROCESSOR_MODE_IRQ = 0x12,\r
93 ARM_PROCESSOR_MODE_SUPERVISOR = 0x13,\r
94 ARM_PROCESSOR_MODE_ABORT = 0x17,\r
95 ARM_PROCESSOR_MODE_HYP = 0x1A,\r
96 ARM_PROCESSOR_MODE_UNDEFINED = 0x1B,\r
97 ARM_PROCESSOR_MODE_SYSTEM = 0x1F,\r
98 ARM_PROCESSOR_MODE_MASK = 0x1F\r
99} ARM_PROCESSOR_MODE;\r
100\r
101//\r
102// ARM Cpu IDs\r
103//\r
104#define ARM_CPU_IMPLEMENTER_MASK (0xFFU << 24)\r
105#define ARM_CPU_IMPLEMENTER_ARMLTD (0x41U << 24)\r
106#define ARM_CPU_IMPLEMENTER_DEC (0x44U << 24)\r
107#define ARM_CPU_IMPLEMENTER_MOT (0x4DU << 24)\r
108#define ARM_CPU_IMPLEMENTER_QUALCOMM (0x51U << 24)\r
109#define ARM_CPU_IMPLEMENTER_MARVELL (0x56U << 24)\r
110\r
111#define ARM_CPU_PRIMARY_PART_MASK (0xFFF << 4)\r
112#define ARM_CPU_PRIMARY_PART_CORTEXA5 (0xC05 << 4)\r
113#define ARM_CPU_PRIMARY_PART_CORTEXA7 (0xC07 << 4)\r
114#define ARM_CPU_PRIMARY_PART_CORTEXA8 (0xC08 << 4)\r
115#define ARM_CPU_PRIMARY_PART_CORTEXA9 (0xC09 << 4)\r
116#define ARM_CPU_PRIMARY_PART_CORTEXA15 (0xC0F << 4)\r
117\r
118//\r
119// ARM MP Core IDs\r
120//\r
1e57a462 121#define ARM_CORE_MASK 0xFF\r
122#define ARM_CLUSTER_MASK (0xFF << 8)\r
123#define GET_CORE_ID(MpId) ((MpId) & ARM_CORE_MASK)\r
124#define GET_CLUSTER_ID(MpId) (((MpId) & ARM_CLUSTER_MASK) >> 8)\r
e359565e 125#define GET_MPID(ClusterId, CoreId) (((ClusterId) << 8) | (CoreId))\r
1e57a462 126// Get the position of the core for the Stack Offset (4 Core per Cluster)\r
127// Position = (ClusterId * 4) + CoreId\r
128#define GET_CORE_POS(MpId) ((((MpId) & ARM_CLUSTER_MASK) >> 6) + ((MpId) & ARM_CORE_MASK))\r
129#define PRIMARY_CORE_ID (PcdGet32(PcdArmPrimaryCore) & ARM_CORE_MASK)\r
130\r
131ARM_CACHE_TYPE\r
132EFIAPI\r
133ArmCacheType (\r
134 VOID\r
135 );\r
136\r
137ARM_CACHE_ARCHITECTURE\r
138EFIAPI\r
139ArmCacheArchitecture (\r
140 VOID\r
141 );\r
142\r
143VOID\r
144EFIAPI\r
145ArmCacheInformation (\r
146 OUT ARM_CACHE_INFO *CacheInfo\r
147 );\r
148\r
149BOOLEAN\r
150EFIAPI\r
151ArmDataCachePresent (\r
152 VOID\r
153 );\r
154 \r
155UINTN\r
156EFIAPI\r
157ArmDataCacheSize (\r
158 VOID\r
159 );\r
160 \r
161UINTN\r
162EFIAPI\r
163ArmDataCacheAssociativity (\r
164 VOID\r
165 );\r
166 \r
167UINTN\r
168EFIAPI\r
169ArmDataCacheLineLength (\r
170 VOID\r
171 );\r
172 \r
173BOOLEAN\r
174EFIAPI\r
175ArmInstructionCachePresent (\r
176 VOID\r
177 );\r
178 \r
179UINTN\r
180EFIAPI\r
181ArmInstructionCacheSize (\r
182 VOID\r
183 );\r
184 \r
185UINTN\r
186EFIAPI\r
187ArmInstructionCacheAssociativity (\r
188 VOID\r
189 );\r
190 \r
191UINTN\r
192EFIAPI\r
193ArmInstructionCacheLineLength (\r
194 VOID\r
195 );\r
168d7245
OM		 196\r
197UINTN\r
198EFIAPI\r
199ArmIsArchTimerImplemented (\r
200 VOID\r
201 );\r
202\r
203UINTN\r
204EFIAPI\r
205ArmReadIdPfr0 (\r
206 VOID\r
207 );\r
208\r
209UINTN\r
210EFIAPI\r
211ArmReadIdPfr1 (\r
212 VOID\r
213 );\r
214\r
1e57a462 215UINT32\r
216EFIAPI\r
217Cp15IdCode (\r
218 VOID\r
219 );\r
220 \r
221UINT32\r
222EFIAPI\r
223Cp15CacheInfo (\r
224 VOID\r
225 );\r
226\r
227BOOLEAN\r
228EFIAPI\r
229ArmIsMpCore (\r
230 VOID\r
231 );\r
232\r
233VOID\r
234EFIAPI\r
235ArmInvalidateDataCache (\r
236 VOID\r
237 );\r
238\r
239\r
240VOID\r
241EFIAPI\r
242ArmCleanInvalidateDataCache (\r
243 VOID\r
244 );\r
245\r
246VOID\r
247EFIAPI\r
248ArmCleanDataCache (\r
249 VOID\r
250 );\r
251\r
252VOID\r
253EFIAPI\r
254ArmCleanDataCacheToPoU (\r
255 VOID\r
256 );\r
257\r
258VOID\r
259EFIAPI\r
260ArmInvalidateInstructionCache (\r
261 VOID\r
262 );\r
263\r
264VOID\r
265EFIAPI\r
266ArmInvalidateDataCacheEntryByMVA (\r
267 IN UINTN Address\r
268 );\r
269\r
270VOID\r
271EFIAPI\r
272ArmCleanDataCacheEntryByMVA (\r
273 IN UINTN Address\r
274 );\r
275\r
276VOID\r
277EFIAPI\r
278ArmCleanInvalidateDataCacheEntryByMVA (\r
279 IN UINTN Address\r
280 );\r
281\r
282VOID\r
283EFIAPI\r
284ArmEnableDataCache (\r
285 VOID\r
286 );\r
287\r
288VOID\r
289EFIAPI\r
290ArmDisableDataCache (\r
291 VOID\r
292 );\r
293\r
294VOID\r
295EFIAPI\r
296ArmEnableInstructionCache (\r
297 VOID\r
298 );\r
299\r
300VOID\r
301EFIAPI\r
302ArmDisableInstructionCache (\r
303 VOID\r
304 );\r
305 \r
306VOID\r
307EFIAPI\r
308ArmEnableMmu (\r
309 VOID\r
310 );\r
311\r
312VOID\r
313EFIAPI\r
314ArmDisableMmu (\r
315 VOID\r
316 );\r
317\r
318VOID\r
319EFIAPI\r
320ArmDisableCachesAndMmu (\r
321 VOID\r
322 );\r
323\r
324VOID\r
325EFIAPI\r
326ArmInvalidateInstructionAndDataTlb (\r
327 VOID\r
328 );\r
329\r
330VOID\r
331EFIAPI\r
332ArmEnableInterrupts (\r
333 VOID\r
334 );\r
335\r
336UINTN\r
337EFIAPI\r
338ArmDisableInterrupts (\r
339 VOID\r
340 );\r
47585ed5 341\r
1e57a462 342BOOLEAN\r
343EFIAPI\r
344ArmGetInterruptState (\r
345 VOID\r
346 );\r
347\r
47585ed5 348UINTN\r
349EFIAPI\r
350ArmDisableIrq (\r
351 VOID\r
352 );\r
353\r
354VOID\r
355EFIAPI\r
356ArmEnableIrq (\r
357 VOID\r
358 );\r
359\r
1e57a462 360VOID\r
361EFIAPI\r
362ArmEnableFiq (\r
363 VOID\r
364 );\r
365\r
366UINTN\r
367EFIAPI\r
368ArmDisableFiq (\r
369 VOID\r
370 );\r
371 \r
372BOOLEAN\r
373EFIAPI\r
374ArmGetFiqState (\r
375 VOID\r
376 );\r
377\r
378VOID\r
379EFIAPI\r
380ArmInvalidateTlb (\r
381 VOID\r
382 );\r
383 \r
384VOID\r
385EFIAPI\r
386ArmUpdateTranslationTableEntry (\r
387 IN VOID *TranslationTableEntry,\r
388 IN VOID *Mva\r
389 );\r
390 \r
391VOID\r
392EFIAPI\r
393ArmSetDomainAccessControl (\r
394 IN UINT32 Domain\r
395 );\r
396\r
397VOID\r
398EFIAPI\r
399ArmSetTTBR0 (\r
400 IN VOID *TranslationTableBase\r
401 );\r
402\r
403VOID *\r
404EFIAPI\r
405ArmGetTTBR0BaseAddress (\r
406 VOID\r
407 );\r
408\r
6f050ad6 409RETURN_STATUS\r
1e57a462 410EFIAPI\r
411ArmConfigureMmu (\r
412 IN ARM_MEMORY_REGION_DESCRIPTOR *MemoryTable,\r
6f050ad6 413 OUT VOID **TranslationTableBase OPTIONAL,\r
1e57a462 414 OUT UINTN *TranslationTableSize OPTIONAL\r
415 );\r
416 \r
417BOOLEAN\r
418EFIAPI\r
419ArmMmuEnabled (\r
420 VOID\r
421 );\r
422 \r
423VOID\r
424EFIAPI\r
425ArmSwitchProcessorMode (\r
426 IN ARM_PROCESSOR_MODE Mode\r
427 );\r
428\r
429ARM_PROCESSOR_MODE\r
430EFIAPI\r
431ArmProcessorMode (\r
432 VOID\r
433 );\r
434 \r
435VOID\r
436EFIAPI\r
437ArmEnableBranchPrediction (\r
438 VOID\r
439 );\r
440\r
441VOID\r
442EFIAPI\r
443ArmDisableBranchPrediction (\r
444 VOID\r
445 );\r
446\r
447VOID\r
448EFIAPI\r
449ArmSetLowVectors (\r
450 VOID\r
451 );\r
452\r
453VOID\r
454EFIAPI\r
455ArmSetHighVectors (\r
456 VOID\r
457 );\r
458\r
459VOID\r
460EFIAPI\r
461ArmDataMemoryBarrier (\r
462 VOID\r
463 );\r
464 \r
465VOID\r
466EFIAPI\r
467ArmDataSyncronizationBarrier (\r
468 VOID\r
469 );\r
470 \r
471VOID\r
472EFIAPI\r
473ArmInstructionSynchronizationBarrier (\r
474 VOID\r
475 );\r
476\r
477VOID\r
478EFIAPI\r
479ArmWriteVBar (\r
480 IN UINT32 VectorBase\r
481 );\r
482\r
483UINT32\r
484EFIAPI\r
485ArmReadVBar (\r
486 VOID\r
487 );\r
488\r
489VOID\r
490EFIAPI\r
491ArmWriteAuxCr (\r
492 IN UINT32 Bit\r
493 );\r
494\r
495UINT32\r
496EFIAPI\r
497ArmReadAuxCr (\r
498 VOID\r
499 );\r
500\r
501VOID\r
502EFIAPI\r
503ArmSetAuxCrBit (\r
504 IN UINT32 Bits\r
505 );\r
506\r
507VOID\r
508EFIAPI\r
509ArmUnsetAuxCrBit (\r
510 IN UINT32 Bits\r
511 );\r
512\r
513VOID\r
514EFIAPI\r
515ArmCallSEV (\r
516 VOID\r
517 );\r
518\r
519VOID\r
520EFIAPI\r
521ArmCallWFE (\r
522 VOID\r
523 );\r
524\r
525VOID\r
526EFIAPI\r
527ArmCallWFI (\r
25402f5d 528\r
1e57a462 529 VOID\r
530 );\r
531\r
532UINTN\r
533EFIAPI\r
534ArmReadMpidr (\r
535 VOID\r
536 );\r
537\r
538UINT32\r
539EFIAPI\r
540ArmReadCpacr (\r
541 VOID\r
542 );\r
543\r
544VOID\r
545EFIAPI\r
546ArmWriteCpacr (\r
547 IN UINT32 Access\r
548 );\r
549\r
550VOID\r
551EFIAPI\r
552ArmEnableVFP (\r
553 VOID\r
554 );\r
555\r
1e57a462 556UINT32\r
557EFIAPI\r
558ArmReadScr (\r
559 VOID\r
560 );\r
561\r
562VOID\r
563EFIAPI\r
564ArmWriteScr (\r
565 IN UINT32 SetWayFormat\r
566 );\r
567\r
568UINT32\r
569EFIAPI\r
570ArmReadMVBar (\r
571 VOID\r
572 );\r
573\r
574VOID\r
575EFIAPI\r
576ArmWriteMVBar (\r
577 IN UINT32 VectorMonitorBase\r
578 );\r
579\r
580UINT32\r
581EFIAPI\r
582ArmReadSctlr (\r
583 VOID\r
584 );\r
585\r
5ea2c2d3 586UINTN\r
587EFIAPI\r
588ArmReadHVBar (\r
589 VOID\r
590 );\r
591\r
592VOID\r
593EFIAPI\r
594ArmWriteHVBar (\r
595 IN UINTN HypModeVectorBase\r
596 );\r
597\r
1e57a462 598#endif // __ARM_LIB__\r
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